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Aachen, Germany, 2004

**A Pulse-Width-Modulation Based Sliding Mode Controller for Buck Converters
**

Siew-Chong Tan, Y. M. Lai, Martin K. H. Cheung, and Chi K. Tse Department of Electronic & Information Engineering The Hong Kong Polytechnic University Hong Kong, China email: ensctan@eie.polyu.edu.hk

Abstract— This paper presents the design and analysis of a pulse-width-modulation based sliding mode voltage controller for buck converters from a circuit design perspective. A practical design approach which aims at systematizing the procedure for the selection of the control parameters is introduced. Additionally, a simple analog form of the controller for practical realization is provided. It is found that this controller adopts a structure similar to the conventional pulse-width-modulated voltage mode controller. Simulation and experimental results show that the response of the converter agrees with the theoretical design.

I. I NTRODUCTION Sliding mode (SM) controllers are well known for their robustness and stability. Most of the previously proposed SM controllers for switching power converters are hysteresismodulation (HM) (or delta-modulation) based [1]–[6]. Naturally, they inherit the typical disadvantages of having variableswitching-frequency operation and being highly control sensitive to noise. Possible solutions are to incorporate constant timer circuits into the hysteretic SM controller to ensure constant switching frequency operation [5], or to use adaptive hysteresis band that varies with parameter changes to control and ﬁxate the switching frequency [6]. However, these solutions require additional components and are unattractive for low cost voltage conversion applications. An alternative solution to this is to change the modulation method of the SM controllers from HM to pulse-widthmodulation (PWM). To the authors’ knowledge, this concept was ﬁrst published in [7]. The idea is based on the assumption that at a high switching frequency, the control action of a sliding mode controller is equivalent to the duty cycle control action of a PWM controller. Hence, the migration of a sliding mode controller from being HM based to PWM based is made possible. This proof was rigourously shown in a companion paper [8] by the same authors. However, the work presented is theoretical, and falls short of a practical consideration on its implementation. In another paper [9], some possible practical methods of implementing a SM controller on buck type converters are described. Termed as the indirect implementations of sliding mode control, it is basically a straightforward circuit representation of the idea provided in [7]. Although the discussion in [9] gives a clear direction as to how such controllers may be developed, it provides only an overview of the PWM based SM controller.

0-7803-8399-0/04/$20.00 ©2004 IEEE.

Hence, in this paper, we present the design of a PWM based sliding mode voltage controlled (SMVC) buck converter, with emphasis on its practical and implementation details, from a circuit design perspective, using the theoretical groundwork established in [7] and [8]. In contrast to [7], the design of this controller at circuit level involves a different set of engineering difﬁculty and consideration. Additionally, we introduce a practical approach to the design and selection of the sliding coefﬁcients of the controller. This approach systematizes the design procedure. It should be noted that it can also be employed for the design of other PWM based SM power converters. Finally, an analog form of the controller that is suitable for practical realization is provided. This controller can be easily implemented from the derived mathematical expressions with only a few operational ampliﬁers and analog ICs. Simulations and experiments are performed on the proposed converter to validate the theoretical design. II. THEORETICAL DERIVATION This section covers the theoretical aspects of the SMVC converter. A practical method of designing the sliding coefﬁcients is also introduced. A. Mathematical Model of an Ideal Sliding Mode PID Voltage Controlled Buck Converter

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Fig. 1.

Basic structure of an SMVC buck converter system.

Fig. 1 shows an SMVC buck converter. Here, the voltage error x1 , the voltage error dynamics (or the rate of change of voltage error) x2 , and the integral of voltage error x3 , can be expressed as x1 x2 x3 = Vref − βVo β Vo = x1 = ˙ − C RL = x1 dt uVi − Vo dt L (1)

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the peak capacitor current iˆ is the maxiC mum inductor current ripple during steady state operation. C (10) 0 0 1 0 1 1 A = ⎣− LC − RL C 0⎦ . 2 2 which can be rearranged to give βVo + LC α3 (Vref − βVo ) 1 α1 α2 + . it is appropriate to have a control law that adopts a switching function such as 1 (1 + sign(S)) (3) u = 2 where S is the instantaneous state variable’s trajectory. However. Germany. (3). even with the errorreducing integral controllers (i.e. Since in practice α1 > RL C . However. we propose to ﬁrst tighten the design constraints by absorbing the actual operating parameters into the inequality. Due to the limitation of ﬁnite switching frequency. α2 . S i. Then. LC 1 0 0 0 ⎤ ⎡ ⎤ ⎡ 0 x1 D = ⎣ Vref ⎦ . (4) with JT = [α1 α2 α3 ] and α1 . 2 2 Multiplying (5) by (4) gives the Lyapunov function candidate ˙ SS 1 1 = S JT Ax + JT B + JT B sign(S) + JT D 2 2 1 1 = S JT Ax + JT B + JT D + |S|JT B. other than stability. For our system’s model. (9) (8) where RL(max) is the maximum load resistance and Vi(min) is the minimum input voltage. the actual output voltage Vo is ideally a pure DC waveform whose magnitude is equal to the desired output voltage Vod ≡ Vref β . one may assume that at steady state operation. the ˙ Lyapunov function is evaluated as S S < 0. 2004 where C. and the time derivative of (4) to give 1 1 ˙ (5) S = JT Ax + JT B + JT B sign(S) + JT D. B. B = ⎣− βVi ⎦ . LC x3 0 The basic idea of SM control is to design a certain sliding surface in its control law that will direct the trajectory of the state variables towards a desired origin when coincided. Next. which the converter is designed for. and load resistance respectively. Vi . inductance. It is important to take this error into consideration for the design of the 3648 . which can be written as ˙ SS>0 = JT Ax + JT B + JT D < 0 (7) ˙ S<0 = JT Ax + JT D > 0. and RL are the capacitance. input. 0 < LC α3 (Vref − βVo )−βL α2 α1 1 − α2 RL C iC +βVo < βVi . Stability Condition With Design Parameters Consideration To alleviate the above problem. The above inequalities give the conditions for stability and provide a range of employable sliding coefﬁcients. and α3 representing the control parameters termed as sliding coefﬁcients. and is described as S = α1 x1 + α2 x2 + α3 x3 = JT x. < α2 RL C βL iˆ C and the right inequality of (9) is implied by LC α3 (Vref − βVo ) + βL α2 α1 1 − α2 RL C iˆ + βVo < βVi C (12) (11) which can be rearranged to give βVo + LC α3 (Vref − βVo ) 1 βVi α1 α2 − + . equations (11) and (13) can be recombined and further tightened by considering the range of input and loading conditions of the converter to give ⎧ ref ⎪ Vo + LC α3 Vβ − Vo ⎪ α1 α2 1 ⎪ ⎪ + < ⎪ ⎪α ⎪ 2 RL(max) C ⎪ L iˆ C ⎪ ⎪ ⎪ ⎪ ⎪ ref ⎪ for Vi(min) ≥ 2 Vo + LC α3 Vβ − Vo ⎪ α2 ⎨ (14) ⎪ ⎪ Vref α3 ⎪ ⎪α Vo + LC α2 β − Vo ⎪ 1 Vi(min) 1 ⎪ ⎪ − + < ⎪ ⎪ RL(max) C ⎪ α2 ⎪ L iˆ L iˆ C C ⎪ ⎪ ⎪ ⎪ Vref α3 ⎩ < 2 V + LC −V for V i(min) o α2 β o (6) To achieve global reachability and asymptotic stability. PID). and sensed output voltage respectively. there will always be some steady state DC error between Vo and Vod . and x = ⎣x2 ⎦ . and βVo are the reference.e.. Theoretically. the left inequality α2 of (9) is implied by 0 < LC α3 (Vref − βVo ) − βL α2 α1 1 − α2 RL C iˆ + βVo . This is performed by ﬁrstly combining (2). Stability Analysis in Circuit Terms As in all other SM control schemes. the determination of the ranges of employable sliding coefﬁcients for the SMVC converter must go through the process of analyzing the stability behavior of the controller/converter system using the Lyapunov’s Direct Method [11].2004 35th Annual IEEE Power Electronics Specialists Conference Aachen. (13) < α2 RL C ˆ ˆ βL iC βL iC where iˆ is the peak magnitude of the bidirectional capacitor C current ﬂow. C. PI. and u = 1 or 0 is the switching state of power switch SW . Additionally. this is not true in practice. This is done by decomposing (9) into two sections of inequalities and considering them as individual cases with respect to the polarity of the capacitor 1 current ﬂow. no information relating the sliding coefﬁcients to the converter performance is provided. Vref . L. the state space model of the system can be derived as ˙ x where ⎡ = Ax + Bu + D ⎤ ⎡ ⎤ (2) where iC is the capacitor current. JT Ax + JT B + JT D < 0 < JT Ax + JT D or rearranged in scalar representation.

is normally limited to a range of within ±5 % of Vod .95 Vod or Vo = Vod into the appropriate parts.2004 35th Annual IEEE Power Electronics Specialists Conference Aachen. A. the DC average of Vo is always lower than Vod . the following design equations are obtained: α1 α3 = 4πfBW and = 4π 2 fBW 2 . but give no detail on the selection of the parameters. the bandwidth of the controller’s response fBW is fBW = 1 ωn = 2π 2π α3 . (26) where A1 and A2 are determined by the initial conditions of the system.95 + 0. for the practical implementation of PWM based SMVC controller. (b) for PWM based SMVC converters. we have d2 x1 dx1 + ωn 2 x1 = 0 + 2ζωn 2 dt dt (17) (21) where ueq is continuous and 0 < ueq < 1.e. Now.05 LC α3 Vod α2 By rearranging (19) and substituting ζ = 1 into the damping ratio. it may also be written in the form ˆ 0 < Vc < Vramp . Derivation of PWM Control Law It was previously derived in [8] that the control method [10] in sliding mode control is effectively a duty cycle control. inequality (15) provides only the general stability information. the control parameters α1 .e JT Ax + JT Bueq + JT D = 0. and over-damped (ζ > 1). and (C) the term LC α3 is always positive. Now.e. In a critically-damped system. 2004 ref controller since the factor LC α3 Vβ − Vo is relatively α2 large in comparison to Vo . and α3 are now bounded by inequalities that have more stringent stability constraints than in (9).95 + 0. Selection of Sliding Coefﬁcients Clearly. α2 we can rewrite the stability condition (14) for PWM based SMVC converter as ⎧ 1 0. D. we choose to design the controller for critically-damped response1 . The equation relating sliding coefﬁcients to the characteristic response of the converter during sliding mode operation can be easily found by substituting S = 0 into (4).05 LC α3 Vod ⎪ α2 ⎪ ⎨ (15) ⎪ ⎪ 1 + 0. α2 (19) Comparing the equivalent control and the duty ratio control [8]. α2 . i. for t ≥ 0 (18) where Vc is the control signal to the pulse-width modulator ˆ and Vramp is the peak magnitude of the constant ramp signal. it is worth mentioning that the design equations in (20) for the SMVC controller are applicable to all other types of second order converters. the design of the sliding coefﬁcients is now dependent on the bandwidth of the desired frequency response in conjunction with the stability condition (15). the duty cycle D is expressed as ueq ∗ = βL − iC + βVo + D= Vc ˆramp V (25) 1 α1 α2 (23) α3 where ωn = α2 is the undamped natural frequency and √α1 ζ = 2 α2 α3 is the damping ratio. In terms of PWM based controlled system.05 LC α3 Vod ⎪ α1 Vi(min) ⎪ α2 1 ⎪ ⎪ − + ⎪α < ⎪ 2 RL(max) C ⎪ L iˆ L iˆ ⎪ C C ⎪ ⎪ ⎪ ⎪ ⎩ for Vi(min) < 1... (16) α1 x1 + α2 dt Rearranging the time differentiation of (16) into a standard second-order system form. and when optimally designed. i. Germany. III. 3649 . For ease of discussion. the difference between Vo and Vod is small. considering that (a) in controllers with integral control function. I MPLEMENTATION OF PWM BASED SMVC C ONTROLLER This section details the implementation of PWM based SMVC buck converter. x1 (t) = (A1 + A2 t)e−ωn t . the following relationships can be established Vc = ueq ∗ and ˆ Vramp = βVi (27) 1 The design for an under-damped controller can be performed using a similar procedure as discussed hereafter. critically-damped (ζ = 1). i. From [10]. Substituting (22) into the inequality and multiplying by βVi gives 0 < ueq ∗ < βVi where α3 LC (Vref − βVo ) RL C α2 (24) which will provide the ideal average sliding motion on the manifold S = 0. the equivalent control input ueq can be formulated ˙ by setting the time differentiation of (4) as S = 0. dx1 + α3 x1 dt = 0. (20) α2 α2 Thus.95 Vod ⎪α ⎪ 1 < + ⎪ ⎪ α2 RL(max) C ⎪ ⎪ L iˆ C ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ for Vi(min) ≥ 1. Additionally. Since D is also continuous and bounded by 0 < D < 1. Thus. Recall that there are three possible types of response in a linear second-order system: under-damped (0 ≤ ζ < 1). solving for u yields ueq = − JT B JT [Ax + D] LC α1 1 Vo α3 LC = − + x1 (22) x2 + βVi α2 RL C Vi α2 βVi −1 by substituting Vo = 0.

Vo is always less than Vod . i. Vo has dV a deviation of 0. B. Furthermore. Brieﬂy. output voltage ripple Vo ≈ ±4 mV (i. RL = 3 Ω). For the entire load range of 3 Ω ≤ RL ≤ 24 Ω. Germany.. i.90 % L from full load to minimum load.5 A to 4 A. It basically adopts the structure of a voltage mode PWM controlled converter. Due to the higher magnitude of the sliding coefﬁcients. the load regulation dRo is 0. Schematic diagram of the proposed PWM based SMVC buck converter. there is no major difference between these waveforms and the experimental waveforms in Figs. 3 and 4. RL = 3 Ω). RV2 RV1 VREF Fig.72 % from L full load to minimum load. IV.035 % of Vod ). i. The calculated critical inductance is Lcrit = 36 µH. The controller is designed for maximum load current (i. This discrepancy is mainly due to the presence of parasitic resistance and equivalent series inductance (ESL) of the capacitor in the practical converter. 3 and 4 show the simulated (left) and experimental (right) waveforms during steady state operation. The controller design is based on (24) and (27). RL = 3 Ω).189 V. Thus. and for the experiment. for the SMVC converter with the 20 kHz bandwidth controller operating at full load (i. < 0. S IMULATION AND E XPERIMENTAL R ESULTS TABLE I S PECIFICATION OF B UCK C ONVERTER Description Input voltage Capacitance Capacitor ESR Inductance Inductor resistance Switching frequency Minimum load resistance Maximum load resistance Desired output voltage Parameter Vi C rC L rL fS RL(min) RL(max) Vod Nominal Value 24 V 150 µF 21 mΩ 100 µH 0.12 Ω 200 kHz 3Ω 24 Ω 12 V The proposed design approach and analog controller for the PWM based SMVC buck converter are veriﬁed through simulation2 and experiment. 5 shows the corresponding set of experimental waveforms for the SMVC converter with the 10 kHz bandwidth controller operating at full load (i. Fig. inspection of the sliding coefﬁcients’s appropriateness using stability condition (15). Except for Vc .e. To study the compliance of the design equations with the performance and its relationship with the transient response. 2004 Sw L L R1 Vo R2 C R Vi D C H RL C(mea) RI2 Isolated Drive RI1 RINV RINV INV RSUM RSUM RSUM UI PWM RV2 SUM Vo RV1 Vramp RSUM UV continuous conduction mode for Vi = 18 V to 30 V and iR = 0. Steady State Performance Figs.2004 35th Annual IEEE Power Electronics Specialists Conference Aachen.956 µs). the simulated and experimental waveforms are in good agreement.e.e. Interestingly. The speciﬁcation of the converter is given in Table 1.e. 6 shows a plot of the measured DC output voltage against the different operating load resistances. It can be seen that except for some ringing noise in the experimentally captured Vc and Vo waveforms. Steady State DC Error at Different Loading Conditions Fig. and formulation of the control equations by substituting the calculated parameters into (24) and (27). the steady state DC output voltage at full load operation is 11. the converter employing the 20 kHz bandwidth controller has a steady state DC output voltage of 11. τ20 kHz = 7.e.e. this controller also inherits the input feed-forward voltage control scheme of conventional PWM voltage mode control in its operation since the input ramp signal Vramp for modulation has peak magnitude that is proportional to the input voltage Vi (refer to (27)). it also shows that the converter has satisfactory load regulation.e. B. The minimum required capacitance is Cmin = 9 µF. For the converter employing the 10 kHz bandwidth controller. Implementation of Controller Fig.e. The converter is designed to operate in 2 The simulation is performed using Matlab/Simulink. This agrees with the previous assumption that the output voltage of PWM based system is always below the desired voltage. Vo ≈ ±8 mV (i. 2. which corresponds to a -3. ﬁrst order response time constant τ10 kHz = 15. the design of this controller can be summarized as follows: selection of the desired frequency response’s bandwidth. calculation of the corresponding sliding coefﬁcients using (20). The main difference is that for the simulation. it can be concluded that the 20 kHz bandwidth controller has better load variation property than the 10 kHz bandwidth controller. The plot also shows that even though Vo increases with RL .e. 2 shows the schematic diagram of the proposed PWM based SMVC buck converter.661 V. The step size taken for all simulations is 10 ns. the controller is designed for two different bandwidths: at one twentieth and at one tenth of the switching frequency fS . which corresponds to a -2. At full load operation (i. Vc of the 20 kHz bandwidth controller has a higher peak-to-peak value than Vc of the 10 kHz bandwidth controller. fBW = 10 kHz (i. minimum load resistance RL(min) ) A. which are not modeled in the simulation program.915 µs) and fBW = 20 kHz (i. 3650 .e.058 % deviation from Vod .07 % of Vod ). The maximum allowable peak-to-peak ripple voltage is 50 mV.151 V deviation in Vo for the entire load range of 3 Ω ≤ dV RL ≤ 24 Ω.633 V.825 % deviation from Vod . the load regulation dRo is only 0. < 0.e. having only a 0.

2004 Gate Pulse u (5 V /DIV) Control Signal VC (2 V/DIV) Fig. and the corresponding inductor current iL and output voltage ripple Vo for SMVC converter with the 20 kHz bandwidth controller operating at constant load resistance RL = 3 Ω. 5. Germany.2004 35th Annual IEEE Power Electronics Specialists Conference Aachen. Ramp Input Vr amp (2 V/DIV) 3651 Gate Pulse u (5V /DIV) CV L u pmarV L ( 1 A DI/ V ) G ( t 5 a V e DI/ P u V sl ) e nI d u c t o r u V r a R m a p m ( 2p V nI p DI/ u V t ) C V n o t r o Sl gi n al C ( 2 V DI/ V ) R pi pl O u t ep ( 1u 0 t mV V ol t a DI/ g V e ) ( 5 V DI/ V ) C u r r e n t u G a t e P ul s e u Vramp VC ~ Vo iL u u ~ Vo iL Vramp VC u . and generated gate pulse u (left) and waveforms of gate pulse u. Simulated (left) and experimental (right) waveforms of gate pulse u. for the SMVC converter with the 10 kHz bandwidth controller operating at load resistance RL = 3 Ω. Gate Pulse u (5 V /DIV) Inductor Output Voltage Current i L (1 A/DIV) Ripple (20 mV /DIV) Gate Pulse u (5V /DIV) Control Signal V C (2 V/DIV) Fig. 3. input ramp Vramp . 4. and generated gate pulse u for SMVC converter with the 20 kHz bandwidth controller operating at constant load resistance RL = 3 Ω. Inductor Output Voltage Current i L (1 A/DIV) Ripple (20 mV /DIV) ~ Vo Ramp Input V ra mp (2 V/DIV) Fig. input ramp Vramp . Simulated (left) and experimental (right) waveforms of control signal Vc . Experimental waveforms of control signal Vc . and the corresponding inductor current iL and output voltage ripple Vo (right).

V V ol t a DI/ g V e ) nI d u c t o r C u r r e n t nI d u c t o r C u r r e n t .7 11. Fig.84 11.62 11.8 Measured Output Voltage (V) 11.1 e snop ser detamitse s 021 s 401 Vm 022 Vm 002 L ( 2 A DI/ V ) Ri p pO el u ( t 2p 0u t 0V mo t V al DI/ g e V ) L ( 2 A DI/ V ) Ri O p p u t el p ( t 0 u 2. operating at 5 kHz step load change between RL = 3 Ω and RL = 12 Ω.72 11.1 s 37 Vm 052 s 38 A 33. 7. 2004 11.64 11.68 11.2 Vm 232 L ( 2 A DI/ V ) Ri p pO el u ( t 2p 0u t 0V mo t V al DI/ g e V ) L ( 2 A DI/ V ) Ri O p p u t el p ( t 0 u 2. 6.66 11. Plot of measured DC output voltage Vo against load resistance RL for SMVC buck converter with both the 10 kHz and 20 kHz bandwidth controllers.1 A 0. Germany.76 11. Simulated waveforms of output voltage ripple Vo and inductor current iL of the SMVC converter with the 10 kHz bandwidth controller (left) and the 20 kHz bandwidth controller (right).78 11. Fig.82 11. 3652 A 27. Experimental waveforms of output voltage ripple Vo and inductor current iL of the SMVC converter with the 10 kHz bandwidth controller (left) and the 20 kHz bandwidth controller (right).6 0 2 4 6 8 10 12 14 16 18 Load Resistance (Ohms) 20 22 24 frequency bandwidth = 10 kHz frequency bandwidth = 20 kHz Fig.2004 35th Annual IEEE Power Electronics Specialists Conference Aachen.74 11. 8. operating at 5 kHz step load change between RL = 3 Ω and RL = 12 Ω. V V ol t a DI/ g V e ) nI d u c t o r C u r r e n t nI d u c t o r C u r r e n t A 63.

[7] H. 7 and 8 show respectively the simulated and experimental output voltage ripple (top) and inductor current (bottom) waveforms of the converter for both the 10 kHz bandwidth controller (left) and the 20 kHz bandwidth controller (right). pp. vol.93% of Vod ) and a steady state settling time of 83 µs for the 20 kHz bandwidth controller.” in Proceedings.83% of Vod ) and a steady state settling time of 120 µs for the 10 kHz bandwidth controller.J. Li. “On the design of sliding mode control schemes for quantum resonant converters. 10. 111– 115.J.” IEEE Transactions on Automatic Control. Malesani. pp. the output voltage has an overshoot ripple of 200 mV (1. “A geometric approach to pulse-width modulated control in nolinear dynamical systems. It is found that the PWM based SM controller adopts a similar structure to that of a conventional PWM voltage mode controller.Q. Sliding Mode Control in Electromechanical Systems. 2. A. and the parameters’ deviation of the actual experimental circuits from the simulation program due to the variation of the actual components used in the setup. 1999. [9] V.M. [4] P. G-T379). This approach uses an equation that is derived from analyzing the dynamic behavior of the converter during sliding mode operation. 1989.” IEEE Transactions on Power Electronics. 8. May 1995. during the load changes. Mattavelli. vol. Menezes. pp. Ch. Nguyen and C. “Analysis of switching frequency reduction methods applied to sliding mode controlled DC-DC converters.: Taylor and Francis. and P. J. 2000.J. Guldner. Ilic. G. 184–187. A. and P. 1985. Applied Nonlinear Control. vol. Cortizo. Lopez. The description of the design methodology takes into account the different aspects of converter’s operating conditions. pp. IEEE Applied Power Electronics Conference and Exposition (APEC).M. 12 no.2004 35th Annual IEEE Power Electronics Specialists Conference Aachen. Feb 1992.E. March 1996. As shown in Fig. 10 no. 15. Nov. 1988. C ONCLUSION A PWM based SMVC buck converter is presented from a circuit design perspective. Castilla. As illustrated in Fig. “A geometric approach to the feedback control of switch mode DC-to-DC power supplies. pp. These are mainly due to the modeling imperfection of the simulation program.X. Feb. vol. June 1995. 7.” IEEE Transactions on Power Electronics. pp. Jan. Matas. “Indirect implementations of sliding-mode control law in buck-type converters. Nguyen and C. “Tracking control of buck converter using sliding-mode with adaptive hysteresis. 3.” in Proceedings. [6] V. Cardoso.K. 960–973. [3] L.08% of Vod ) and a steady state settling time of 73 µs for the 20 kHz bandwidth controller. and an overshoot ripple of 250 mV (2. and J. Slotine and W. 96–102. Sira-Ramirez. IEEE Applied Power Electronics Conference and Exposition (APEC). Figs. Sabanoivc. vol. Shi . [2] M. Lopez. Rossetto. U. Lee. Venkataramanan. 1997.C.: Prentice Hall. [5] B. Tenti. 35 no. Rossetto.” IEEE Transactions on Circuits and Systems.R. Moreira. [11] J. [8] H. Spiazzi. A practical approach to the design of the sliding coefﬁcients is also proposed in this paper. 1291–1298. 3. 403–410. 1. Englewood Cliffs. 1991. pp. pp. vol. Lee. Sira-Ramirez and M. “Sliding mode control of DC-to-DC converters. London. de Vicuna. However.” IEEE Transactions on Power Electronics.” in IEEE Power Electronics Specialists Conference Record (PESC). “Sliding Control”. 7. N. and S. L. L. 15 no. 1.F. 34 no. “Small-signal analysis of DCDC converters with sliding mode control. “Performance optimization of Cuk converters by sliding-mode control.” in Proceedings. Dynamic Performance The dynamic performance of the controllers is studied using a load resistance that alternates between quarter load (12 Ω) and full load (3 Ω) at a constant frequency of 5 kHz. in addition to the stability conditions of the system. and an overshoot ripple of 232 mV (1. Oct. and G.67% of Vod ) and a steady state settling time of 104 µs for the 10 kHz bandwidth controller. [10] V. 302–309. 1086–1093. The simulation and experimental results show that the response of the converter agrees with the theoretical design. M. the simulated output voltage has an overshoot ripple of 220 mV (1. Spiazzi. Germany.C. and J. L. vol. during the load changes. 2004 C. Utkin. R EFERENCES ´ [1] R. Control and Instrumentations (IECON). pp. Furthermore. B. it should also be mentioned that there are some slight disagreements between the experimental and simulation results in terms of the overshoot ripple magnitudes and the settling times. IEEE Conference on Industrial Electronics. there is no ringing or oscillations in transience. V. 3653 . Cuk. O. consistent with a critically-damped response. An analog form of the controller is also presented. 251–258. ACKNOWLEDGMENT The work described in this paper was supported by a grant provided by The Hong Kong Polytechnic University (Project No.Q.

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