You are on page 1of 19

Release Notes For ModelSim SE 6.

6c

Aug 23 2010
Copyright 1991-2010 Mentor Graphics Corporation
All rights reserved.
This document contains information that is proprietary to Mentor
Graphics
Corporation. The original recipient of this document may duplicate
this
document in whole or in part for internal business purposes only,
provided
that this entire notice appears in all copies. In duplicating any part
of
this document the recipient agrees to make every reasonable effort to
prevent the unauthorized use and distribution of the proprietary
information.
TRADEMARKS: The trademarks, logos and service marks ("Marks") used
herein
are the property of Mentor Graphics Corporation or other third
parties.
No one is permitted to use these Marks without the prior written
consent
of Mentor Graphics or the respective third-party owner. The use
herein
of a third-party Mark is not an attempt to indicate Mentor Graphics
as a
source of a product, but is intended to indicate a product from, or
associated with, a particular third party. The following are
trademarks of
of Mentor Graphics Corporation: Questa, ModelSim, JobSpy, and Signal
Spy.
A current list of Mentor Graphics trademarks may be viewed at
www.mentor.com/terms_conditions/trademarks.cfm.
End-User License Agreement: You can print a copy of the End-User
License
Agreement from: www.mentor.com/terms_conditions/enduser.cfm.
_______________________________________________________________________
Product Installation and Licensing Information
Detailed product installation and licensing information plus install
notes, release notes, and reference documentation can be viewed at:
[1]http://www.model.com/modelsim-downloads
Then select your ModelSim Product Version:
ModelSim PE - [2]http://www.model.com/modelsim-pe-downloads
ModelSim DE - [3]http://www.model.com/modelsim-de-downloads
ModelSim SE - [4]http://www.model.com/modelsim-se-downloads

How to Get Support For information on how to obtain technical support


visit a support page at:
[5]http://www.model.com/modelsim-support
[6]http://supportnet.mentor.com

Release Notes Archives For release notes of previous versions visit:


[7]http://www.model.com/modelsim-downloads
Then select your ModelSim Product Version or find them in the installed
modeltech tree in <path to modeltech installation>/docs/rlsnotes.
Contact ModelSim
For non-support related questions please contact us at:
[8]http://www.model.com/contact
_______________________________________________________________________
Index to Release Notes
[9]Key Information
[10]User Interface Defects Repaired in 6.6c
[11]Verilog Defects Repaired in 6.6c
[12]PLI Defects Repaired in 6.6c
[13]VHDL Defects Repaired in 6.6c
[14]FLI Defects Repaired in 6.6c
[15]VITAL Defects Repaired in 6.6c
[16]SystemC Defects Repaired in 6.6c
[17]Assertion Defects Repaired in 6.6c
[18]Mixed Language Defects Repaired in 6.6c
[19]Coverage Defects Repaired in 6.6c
[20]General Defects Repaired in 6.6c
[21]Mentor Graphics DRs Repaired in 6.6c
[22]Known Defects in 6.6c
[23]Product Changes to 6.6c
[24]New Features Added to 6.6c
_______________________________________________________________________
Key Information
* PLATFORM AND COMPILER SUPPORT
Windows 7 32-bit support has been added for this release. (Please
see the LICENSING section below for special instructions on using
your hardware key.)
ModelSim Deluxe is supported on 32-bit linux and 32-bit Windows
platforms. 32-bit ModelSim Deluxe will run, and is supported, on
64-bit Windows 7. However, it does not run as a 64-bit binary.
SystemC has dependencies on C++ compiler versions. In release 6.6,
the default compiler versions for linux have changed to
gcc-4.3.3-linux and gcc-4.3.3-linux_x86_64. The following versions
will be supported in 6.6:
+ gcc-4.3.3-linux
+ gcc-4.1.2-linux
+ gcc-4.0.2-linux
+ gcc-4.3.3-linux_x86_64
+ gcc-4.1.2-linux_x86_64
+ gcc-4.0.2-linux_x86_64
+ gcc-4.1.2-sunos510
+ gcc-4.1.2-sunos510x86
+ gcc-4.2.1-mingw32vc9
The following linux versions of gcc will be discontinued in the 6.7
release.
+ gcc-4.1.2-linux
+ gcc-4.0.2-linux
+ gcc-4.1.2-linux_x86_64
+ gcc-4.0.2-linux_x86_64
+ gcc-4.1.2-sunos58
+ gcc-4.1.2-sunos59
Support was be discontinued for the following operating systems in
the 6.7 release.
+ Solaris 8
+ Solaris 9
No operating systems were discontinued in the 6.6 release.
For a complete list of supported platforms and SystemC compilers
see the Installation and Licensing Guide under the section
Supported Platforms.
* PRODUCT SUPPORT
ModelSim Deluxe supports VHDL and Verilog languages and the
features SystemC and assertions. It runs on 32-bit linux and 32-bit
Windows platforms only.
The profiling feature is now supported on the linux_x86_64
platform.
The ModelSim LE product has been discontinued starting with the 6.6
release.
This release includes a new dongle driver installer for Windows.
The new dongle driver versions that will be installed are as
follows:
+ Aladdin (FLEXID=9-) driver version 4.96
+ Dallas (FLEXID=8-) driver version 3.2.1.11
+ Sentinel (FLEXID=6-)/(FLEXID=7-) driver version 5.41
The new dongle driver installer will install these drivers only if
they are newer than the currently installed dongle drivers on your
Windows system.
COMPILATION COMPATIBILITY
You must recompile or refresh your models if you are moving forward
from 6.5x or earlier release versions.
See "Regenerating your design libraries" in the User's Manual for more
information on refreshing your models.
The vcom compiler default language has been changed from VHDL-1987 to
VHDL-2002. To choose a specific language version:
* select the appropriate version from the compiler options menu in
the GUI,
* invoke vcom using switches -87, -93, or -2002, or
* set the VHDL93 variable in the [vcom] section of modelsim.ini.
Appropriate values for VHDL93 are:
+ 0, 87, or 1987 for VHDL-1987;
+ 1, 93, or 1993 for VHDL-1993;
+ 2, 02, or 2002 for VHDL-2002.
LICENSING
Windows 7 32-bit support has been added for this release. Please note
that if you need to use a hardware key to provide the hostid for
licensing on Windows 7, it must be a USB hardware key. Parallel port
hardware keys are not supported. If you need to replace your hardware
key, please go to http://supportnet.mentor.com and open a Service
Request to replace your parallel port hardware key with a USB hardware
key.
The 6.6 release uses the following licensing versions: FLEXnet v10.8.5;
Mentor Graphics Licensing MSL v2009_2 with MGLS v8.7_4.2 and PCLS
2009.268. For this release of the product, the FLEXnet licensing
software being used is version 10.8.5. For floating licenses it will be
necessary to verify that the vendor daemon (i.e., mgcld) and the
license server (i.e., lmgrd) have FLEXnet versions equal to or greater
than 10.8.5. The vendor daemons and lmgrd that are shipped with this
release will be FLEXnet version 10.8.5. If the current FLEXnet version
of your vendor daemon and lmgrd are less than 10.8.5 then it will be
necessary to stop your license server and restart it using the vendor
daemon and lmgrd contained in this release. If you use node locked
licenses you don't need to do anything.
Use the following license versions:
* FLEXnet v10.8.5
* MSL v2009_2
* MGLS v8.7_4.2
* PCLS 2009.268
GENERAL INFORMATION
The ModelSim DE 6.6 release notes incorrectly stated that the "Event
Traceback" feature was supported. This feature is not supported in
ModelSim DE.
Note regarding using OVM and code coverage together: in order to
prevent reduced performance by having code coverage on for the OVM
package, if you are turning on code coverage on the vopt command line,
you need to specify an instance path for code coverage. This can be the
design top level. Otherwise code coverage will be on for the ovm
package. Use the option of the form:
vopt ... +cover=sbce+/top ...
where /top is your design top level instance.
Executables in bin directory will default to 32-bit mode on 64-bit
Linux machines unless MTI_VCO_MODE is set to 64. vco will behave in a
similar fashion.
Event order differences between an optimized and unoptimized design
have been reduced with this release. Specifically, event propagation
through Verilog zero-delay continuous assignment and primitive networks
has been changed such that optimizations involving these networks are
much less likely to result in behavioral differences. However, note
that a design depending on the old event ordering may not behave the
same with this release. Both, the unoptimized and optimized behavior
may change, but should match each other more closely. Ideally, "races"
should be removed from the design, but, if desired, the user may revert
back to the old event ordering by specifying the -noimmedca vsim option
or by setting the following line in the modelsim.ini file:
ImmediateContinuousAssign = 0
Support for PDF files on the Solaris x86 platform is limited. Adobe has
not shipped a PDF reader for Solaris x86 since version 4.05 and no
longer supports that version. Some third-party readers are available,
including GNOME PDF and xPDF which ships with the Solaris x86 companion
DVD. If you still cannot access a PDF version of a document, you can go
to SupportNet using a non-Solaris x86 UNIX-based system, a Linux-based
system, or a Windows-based system to view Mentor Graphics PDF
documentation.
The vlog, vcom and vopt command line options are now case sensitive
which makes them consistent with the vsim command line options.
The default time unit for SystemC can be set using the "ScTimeUnit"
variable in the modelsim.ini file.
By default ScTimeUnit is set to 1 ns. The default time unit in SystemC
can also be set using the sc_set_default_time_unit() function
before any time based object like sc_clock or sc_time is created.
Starting in the 6.1 release, the vsim -dpiexportobj option has changed
behavior.
This primarily affects Windows and AIX platforms. The changes are
listed below:
* An extension is now automatically added to the object filename.
* There is no longer a need to add "-c -do 'quit -f'" to the vsim
-dpiexportobj command line.
The examples/systemverilog/dpi/simple_calls runtest.bat files have been
modified to show the correct flow.
Beginning in the 5.8 release, SDF files compressed in the Unix compress
format (.Z) are no longer supported, but the GNU zip format (.gz)is
supported.
Therefore, we only read in compressed SDF files that are created with
the GNU zip (gzip) extension. A file is not require to have a .gz
extension, but it will error on files that have a .Z extension.
Beginning with the 5.6 release (on Windows platforms only), attempts to
link in libvsim.lib or tk83.lib using the Microsoft Visual C++ linker
version 5.0 will fail with a message similar to:
"Invalid file or disk full: cannot seek to 0xaa77b00".
Microsoft Visual C++ version 6.0 does not have this problem.
Acrobat reader version 4.0 or greater must be used to read any .pdf
file contained in version 5.5c or greater.
The following browsers are unsupported for the HTML documentation:
* Netscape versions 4.x and 6.x
* Opera versions 6.x and 7.x
We regret we cannot support these browsers for use with the HTML
documentation. We recommend upgrading to a new browser:
Sun Solaris: Upgrade to Firefox:
* http://www.mozilla.org/
* http://wwws.sun.com/software/solaris/browser/index.html
Linux: Upgrade to Firefox:
* http://www.mozilla.org/
Windows: Upgrade to Firefox or Internet Explorer 6 or newer:
* http://browser.netscape.com/ns8/download/default.jsp
* http://www.microsoft.com/windows/ie/default.mspx/
* http://www.mozilla.org/
AVM
AVM 3.0 update 3 is now integrated into 6.4 release of the simulator.
If you have a avm-based design compiled in 6.3 series, you need to
re-compile your design. If not, when you attempt to simulate your
design, you will see a message similar to this:
# ** Error: (vsim-13) Recompile work.action_pkg because mtiAvm.avm_pkg
has changed.
Starting in 6.4, AVM class components derived from avm_named_component
will be added to the instance workspace along with modules and other
elaborated design units. The string names given to the components will
be used as instance names and must be legal identifiers by Verilog
rules. These class components will be added to the workspace after the
configure phase of do_test()
Class properties are logged and may be added to other windows such as
the Waveform. Variables inside the methods of the class are automatic
and do not get logged. Not all class property data types are supported.
You may see a warning like this:
(vsim-4027) Logging is not supported for Associative Array item:
/tb_transactor_pkg::tb_stimulus::m_children
Then you can suppress "-suppress 4027"
Starting in 6.3, the SystemVerilog libraries are delivered in compiled
form. Users no longer have to compile or link to special libraries;
they only need to import avm_pkg::*; (as they always have) to use the
AVM facilities. The default library search path includes the compiled
AVM libraries. In addition to the compiled form, the source code for
the compiled libraries is delivered in <install_dir>/verilog_src/avm.
If you compile the AVM source into your own libraries, that will take
precedence of the pre-compiled form.
The 6.3 series simulator only supports the AVM 2.0 Update 2 and AVM 3.0
releases; it does not support AVM 2.0 and 2.0 Update 1 releases.
Please note that in February 2007, there was a change in the naming
scheme of the AVM release. AVM 2.0a has been renamed AVM 2.0 update 1.
The contents of both releases are the same.
Below is a matrix illustrating the compatibility between the simulator
and the different AVM releases.
Simulator Version AVM Version
6.2 through 6.2d 2.0
6.2e and higher 6.2 series 2.0 update 1
6.3 and higher 2.0 update 2, 3.0 and all 3.0 updates
_______________________________________________________________________
User Interface Defects Repaired in 6.6c
* Using the Structure window's View > Datasets... menu while it was
undocked would generate a Tcl error. This problem has been fixed.
* A Tcl error could occur when opening a saved dataset that was not
created with the -debugdb option after a signal was added into a
Dataflow window.
* A paused macro (do file) will abort the macro prematurely after a
run command is given at the paused prompt. This issue has been
resolved.
* Opening a text file in the built-in editor would cause the GUI to
hang if the file contained "." as the very first character. This
problem has been resolved.
* Radix define default radix gives an error. This issue is now fixed.
* Saving a layout that is in maximized mode and having undocked
windows could result in continuous window flashing. The flashing
could be stopped by clicking on one of the window tabs. This issue
has been resolved.
* When a macro execution is paused (the "Pause" prompt is given),
execution of another macro (do) file causes the paused macro to
resume execution. This issue has been fixed. After the macro file
completes, execution will return to the "Pause" prompt of the prior
macro.
* When a macro (do file) pauses execution (the Pause prompt is
given), some of the toolbar buttons are disabled. This issue has
been resolved.
* A check was added to reuse an existing debug database when the
-debugDB switch is used on a design that has not changed since the
last time the database was created. A note is printed indicating
the database is being reused rather than created.
* vsim does not clean up jobspy job information from the jobspy
daemon when $finish is used to exit the simulator. This has been
fixed.
* After some Drag-and-Drop operations, the Wave window will freeze
and stop drawing. This issue has been resolved.
* When restarting the simulation or loading a wave format file, any
signals expanded in the Wave window are collapsed instead of being
restored to their original expand state. This issue has been
resolved.
* In some cases, particularly with MVC protocols, the transaction
engine could corrupt the WLF file, resulting in the inability to
load the file for post-simulation debug. This has been fixed. For
earlier releases, the work-around is to issue [dataset save sim
vsim.wlf] just before quitting the simulation. That will correctly
flush the file in most cases.
* Selecting any of the choices from the "Test Analysis" sub-menu for
the Verification Tracker window did not work correctly when
multiple items in the window were selected. It now works correctly.
* Selecting any of the choices from the "Test Analysis" sub-menu for
the Cover Directives window did not work correctly when multiple
items in the window were selected. It now works correctly.
* The "Rank Most Effective Tests..." menu item has been added to the
"Test Analysis" sub-menu for the Instance Coverage, Structure, and
Covergroups windows.
* The Missed Coverage windows gave Tcl errors when attempting to
configure columns. "Change ColumnLayout" has been disabled from the
toolbar for these windows, since they each only have one column.
* When all of the filters for the Verification Tracker or
Verification Browser windows were removed, they would sometimes
reappear in future sessions. They are now correctly removed from
the .modelsim file upon quitting.
* Under rare circumstances, the Covergroups window would only display
the first 100 items. This has been repaired.
* Several windows use a hierarchy widget which allows the user to
hide/show columns from a "Column Configuration" dialog, accessible
by clicking on the triangle in the header of the first column.
Under some circumstances, a Tcl error occurred when clicking on
"OK" for that dialog. This has been fixed.
* GUI update is very slow in viewcov mode when Objects window is
opened. This issue is now fixed.
* On the Windows platform it was possible that the diff.exe
executable installed under the modeltech directory would be
accessed via the PATH variable instead of the one available in the
user's Unix-like installation (e.g. Cygwin). This has been fixed by
moving the diff.exe into a unique location within the modeltech
tree.
* Significantly improved performance when logging large datasets.
_______________________________________________________________________
Verilog Defects Repaired in 6.6c
* Fixed unpack error from streaming operator when stream width is
larger than target variable(s).
* The vlog compiler no longer allows tasks and functions to first
declare an input or output in the ANSI-style argument list and then
redeclare the port in the task/function body.
* vopt would print an internal error for an always_comb with a
reference to a port which was aliased to a concatenation due to
inlining.
* The 'const' keyword must be used in conjunction with the 'var'
keyword or an explicit data type in declarations.
* Using the output from $psprintf as a $display argument when source
is compiled without -sv could cause the simulator to crash.
* A variable initialized by a builtin method in an unnamed initial
block would cause an "Unresolved reference" error during
elaboration.
* vlog no longer issues a syntax error when compiling hierarchical
modport references.
* vsim would sometimes crash when a forward typedef declaration was
used as a static prefix. For example:
typedef class CVal;
...
CVal::create();
* A 'new' assignment inside a module which was inlined would cause an
internal error.
* An out-of-bounds index into an externally referenced memory, when
used as the right-hand-side of a continuous assignment, could cause
a crash.
* Some source code errors would incorrectly halt vlog source
processing when the -skipprotectedmodule was specified.
* In cases where a struct was defined inside a class and a
non-existent field of the struct was referenced in an inline
randomization constraint, vsim would crash rather than reporting an
error that the field name was not found.
* Array manipulator methods 'min' and 'max' did not work properly
with arrays of real (floating-point) numbers.
* A continuous assignment to a bit-select of a vector net within a
nested module in an optimized design resulted in an elaboration
crash.
* Task enables with a mismatch between the number of named ports and
the number of formals would generate errors in vlog for all formal
ports of the task.
* An event on an element of a 2-dimensional wire array did not
trigger properly.
* The -enumbaseinit flag was not being observed when the enum methods
next() and prev() were called on values not within the enum type.
* Warning messages 2224 and 8440 which report illegal writes to
clocking block inputs may be upgraded to an error using the vlog
option -error 2224 and the vsim option -error 8440.
* The user interface force command on a Verilog bit vector (bit []
var) once again interprets the value as a binary number. The
anomalous state of a force or change on an int type being done with
a binary and on a bit type being done with decimal is corrected.
* vlog would crash when attempting to expand nested macros where the
macro definitions required arguments but the use of these macros
did not provide any arguments.
* Under certain circumstance, an output net of a buffer or inverter
appears stuck at X even if it is hierarchically referenced in HDL.
* DPI exportwrapper generation are now suppressed for the locked work
library.
* Fixed the compiler error detection on the usage of illegal DPI
argument type such as dynamic arrays embedded in the struct. Such
errors were not caught for certain scenarios.
* A non-blocking assignment between two memories, where the
directions of the indices were not the same, would result in the
elements being stored in the reverse order.
* vopt issued an internal error with designs that contained unsigned
parameters.
* The -E switch for vlog now preserves the tick before the celldefine
pragma.
* vsim would sometimes generate errors like:
# ** INTERNAL ERROR: pkgref: export lookup failed for package
#1
for designs that were compiled with vlog -incr -quiet.
* vsim would sometimes generate invalid elaboration errors like:
# ** Error: (vsim-8249) extended_class_test2.sv (18): Type of
argument 'arg1' for virtual method 'foo' in subclass 'child' does
not match the type of argument in superclass 'parent__1'.
when a typedef was inherited from the superclass.
* vlog and vopt would sometimes generates errors like:
Internal error: ../../../src/vlog/vmkdecl.c(2431) refno==pkgIdx
* Fixed the use model for locked work library required in distributed
simulations involving DPI exports. Added a new vsim switch
-dpiexportonly to support this use model.
* vlog was generating an incorrect error when a class property was
referenced in an inline randomization constraint and the property
name was also declared as a type in an imported package or parent
scope.
* In cases of duplicate variable event expressions in an always
block, subsequent always block trigger events could be ignored.
* Passing a slice of a queue to a class method would result in either
a crash or an incorrect value seen inside the method.
* The string methods atoi, atohex, atooct, and atobin previously
stopped processing a string when an underscore was seen. They now
ignore underscores, as specified in the LRM.
* A slice of a multi-dimensional packed net array was not being
referenced correctly.
* In some cases where an automatic variable was used in an inline
randomization constraint inside a fork..join_none block the value
of the automatic variable was incorrect at the time randomize() was
called. In some cases this resulted in a bad class handle
dereference error, and in other cases it generated a bad
randomization result.
* When using a multidimensional foreach loop where the outer
dimension type was a simple integer range, vopt could fail during
design analysis.
* When an assignment pattern has 'type' entries, and more than one
matches, we now use the last matching value, where, before, we used
the first. Example:
const logic [1:0] c = '{logic:1'b1, logic:1'b0}; // Should assign
0's.
* Exponentiation of 0 to a negative number (0**-1) now results in 'x'
as the result.
* In some unusual cases, vsim would report the following internal
error when loading a SystemVerilog package:
# ** INTERNAL ERROR: (vsim-8603) Package 'P3' has exported 6 items,
but 5 items were expected.
* Verilog -incr compiles would not in all cases recompile design
units that depended upon $unit when $unit itself was recompiled.
* In the case of packed structs and unions, the DPI header did not
generate proper array dimensions of svBitVecVal. This issue is now
fixed.
* An expression of the form 'random() % 10 > 0', when passed as an
argument to a task with argument type 'bit', would result in the
wrong value being passed.
* In some replicate statements, 4 state replicates were used when 2
state replicates were necessary.
* vopt would sometimes generate an error like the following when
referring to objects declared in the $unit scope:
** Error: (vopt-7029) test.sv(-1): Hierarchical reference
('test_sv_unit.i') not allowed to a package; use '::' for package
references.
* vlog and vopt generated an internal error like the following when a
superclass parameter value was referenced using
current_class::PARAM with a parameterized superclass:
** Error: test.sv(21): Internal error:
../../../src/vlog/vgentd.c(403) sig_allocatedOf(sig) ||
sig_is_importedOf(sig)
* An array index could be incorrectly sign-extended even when the
type of the index was unsigned. Example:
val = i1.gen_slice[0].geni.mbus[~i1.data.id]
In the above, the value of 'i1.data.id' was 0, and its inverse
should have been 1. But the inverse was incorrectly extended to 32-
bits of 1's.
* Fixed crash in vopt involving inlining of port expressions and
incorrect sharing of implicit wires.
* Initial value would not be propagated to the destination signal
when $init_signal_driver was used with a an object of type Verilog
reg as the source and a Verilog net as the destination. This has
been fixed.
* vlog and vopt would sometimes generate internal errors like:
** Error: test.sv(4): Internal error:
../../../src/vlog/vgencode.c(96) vl_save_stack_on_wait
in cases where an automatic variable was used in a complex
expression in an indexed part-select.
* vlog would sometimes generate an internal error like:
** Error: sip_shared_lib.sv.strip(27460): Internal error:
../../../src/vlog/vgencode.c(53) loc != NULL
in cases where a superclass type name was used as a static prefix
to refer to non-static properties and methods of a class instance.
* The change command could give the wrong result with a bit vector.
* vopt incorrectly reported an unresolved reference to "this" in a
named begin..end block in a class method when calling a superclass
method. The error only occurred when the superclass was defined in
a package and the sub-class was not defined in a package or $unit.
* Optimized cells with more than 32 timing checks could crash during
simulation.
* vopt would crash in certain cases where a port was referenced in an
always_comb and that module was inlined.
_______________________________________________________________________
PLI Defects Repaired in 6.6c
_______________________________________________________________________
VHDL Defects Repaired in 6.6c
* Globally static composite constant declarations local to a method
of a protected type were not being initialized correctly, resulting
in a simulator crash if they were referenced.
* A subprogram declared locally in a method of a protected type could
not call itself recursively because a compiler error would be
issued. Since it's legal, the compiler has been fixed to allow it.
* Incorrect values could be computed if an alias of an operator is
declared and the bounds of its operands are outside the bounds of
the original operator. The compiler was incorrectly using the
original meaning of the operator to evaluate expressions, instead
of using its new meaning. For example, with the following
declaration:
alias "-" is "not" [bit return bit];
the expression -(x) would return -1 when x is '1', rather than '0'.
* Designs involving a protected type method and another subprogram
declared in a PROCESS statement declarative region could
occasionally cause the simulator to crash when the design was
loaded.
* vsim would sometimes crash when a complex port map was used in a
configuration to map portions of a component port to an entity,
when there was a direct mapping to the component port in the
instantiation from an array actual with a different, but compatible
type.
* When a user attempts to wait on the edge of signal in a postponed
process, the correct behavior is most often not to ever resume. The
reason is that edge detection is often written with s'event, which
is true in the delta cycle it occurs, but doesn't remain true at
the end of a time slice when postponed processes execute. In the
simulator because of optimizations, we incorrectly resumed anyway.
We now behave correctly and that could be surprising. Where it is
possible to detect the misguided attempt at runtime without undue
cost, we now also provide a helpful warning.
* When using external names, it could resolve to an object with the
same name but declared in a different scope. This would only happen
if the object is a constant, variable, generic, or an alias. The
object must share the same names with a constant, variable,
generic, or an alias that is declared in a scope that encloses the
target object's scope.
* In some cases driving a signal which is a external name can cause
the simulator to crash. The external signal must be an array signal
and only a portion of the signals is being driven by this
statement. Also the longest static name of the target must be the
whole signals.
* Subelement association to an out or inout signal parameter would
result in the following error:
** Error: a.vhd(21): Signal "x" cannot be target of variable
assignment statement.
** Error: a.vhd(21): Signal "s" cannot be target of variable
assignment statement.
* Attempting to use a +acc+ option to vopt with a design pathname
that contained a VHDL for-generate label and index would not work.
For example +acc+/top/do_segment(0)/u1 would cause a command line
parsing error. The workaround was to use square brackets. Now, the
use of parentheses is supported to the extent that the index value
is an integer. If the for-generate index is of an enumeration type,
the position number of the intended enumeration literal must still
be used.
* Incorrect code could be generated for an assert statement appearing
within a subprogram specified by a protected type declared within a
generate block.
* The simulator could incorrectly report out-of-range errors for
for-loop and for-generate loop bounds even when the loops were
determined to be unreachable due to surrounding conditional
statements.
* Reduced the memory needed to compile large VHDL netlists in
-novopt. Also reduced the memory needed for large VHDL netlists in
vopt.
* For a signal, 'transaction was only recognized on the first
assignment of a constant value to the signal. If the assignment was
repeated during the simulation, 'transaction was not recognized.
_______________________________________________________________________
FLI Defects Repaired in 6.6c
* mti_GetSignalSubelement could crash if used on a signal of record
type.
_______________________________________________________________________
VITAL Defects Repaired in 6.6c
_______________________________________________________________________
SystemC Defects Repaired in 6.6c
* sc_get_int_param() would fail to get values for 2-state
SystemVerilog parameters.
* Black boxes with no SystemC design units in them can now be
instantiated from SystemC.
* All the multi socket classes in the TLM 2.0 library are no longer
dependent on the Boost library.
_______________________________________________________________________
Assertion Defects Repaired in 6.6c
_______________________________________________________________________
Mixed Language Defects Repaired in 6.6c
* A VHDL signal connected to a large number of Verilog module ports
also connected to "tran" primitives resulted in poor simulator
performance and possibly a crash or hang.
* When the SystemVerilog bind construct was used to bind to a black
box compiled in a different library than the bind statement, vopt
would fail to find the bind target and error out. This has been
fixed.
* When the SystemVerilog bind construct was used to bind to a VHDL
target compiled in a library containing mixed-case characters, vopt
would fail to find the bind target and error out. This has been
fixed.
* Using SystemC control/observe with an element of SystemC signal
array would result in incorrect values being propagated to/from the
HDL signal. This has been fixed.
* Using an element of an array indexed by an enumerated type as
SignalSpy source or destination object would result in an 'object
not found' error in vsim. This has been fixed.
* SignalSpy calls were not restored completely after restoring a
checkpoint using the vsim -restore command. This problem was
visible when using $enable_signal_spy (or $disable_signal_spy) on
existing SignalSpy mappings after restoring simulation from a
checkpoint. This has been fixed.
* If any controlling configuration library mapping is in effect at
the time a bind statement is encountered, vopt would ignore this
library mapping while searching for the bind target. This has been
fixed.
* Using $init_signal_spy with an element of a Verilog unpacked array
of integers as the destination object and a user-defined VHDL enum
as the source object would cause vsim to error out with a 'type
mismatch' error. This has been fixed.
* vopt exited with errors when VHDL or Verilog packages were
instantiations from Verilog design-units.
_______________________________________________________________________
Coverage Defects Repaired in 6.6c
* The commands
coverage ranktest ... and
vcover ranktest ... will produce more accurate ranking numbers.
* In some cases while using vopt flow, the text report for an
instance does not contain exclusion information if there is an
exclusion. The reason behind this error is some optimizations done
by vopt. Currently the text report for instances while using vopt
flow should contain all available exclusion information.
* The vcover merge was taking a long time in writing out the final
merged database.
* Added automatic exclusions of code coverage expr/cond rows that
correspond to the select inputs of ternary expressions being "don't
care". Added a vlog/vopt option -noexcludeternary to not
autoexclude. Added a vsim option -noexcludeternary to turn off the
autoexclusions in the entire design. (This was added in 6.6b.)
* Due to some optimizations same state transitions of FSM would
sometimes not be covered. This has been fixed and is available
under the option -coverenhanced.
* When a current state variable of FSM is a field of a record and the
complete record has been assigned with a next state variable, FSM
would sometimes not be recognized. This has been fixed.
* Coverage reports would sometimes incorrectly report that
short-circuiting is enabled for expressions defined inside VHDL
generate blocks even when the design was compiled with the
-nocovershort option of vcom. This has been fixed.
* Coverage detail report was printing extra blank lines for branch,
condition, and expression coverage items.
* Some FEC rows were incorrectly included in the UDP section of
coverage report.
_______________________________________________________________________
General Defects Repaired in 6.6c
* The simulator used the last entry specified for a softname in the
MGC_LOCATION_MAP. Other Mentor Graphics tools use the first
softname. The simulator now uses the first softname as well.
* Removed symlink for bin/gdb. gdb is no longer distributed in /
directory. Instead it is distributed in /external directory.
_______________________________________________________________________
Mentor Graphics DRs Repaired in 6.6c
* Simulator does not return to the Paused state after completion of a
"do file".
* dts0100692291 - Segmentation violation in statement NEW in method
of a protected type.
* dts0100693211 - always_comb internal vopt error with port aliased
to concat.
* dts0100694015 - Error with custom radix "-default" value.
* dts0100694585 - vsim elab crash with type::fn() lookup.
* dts0100694587 - Signal 11 crash in VsInClassScope().
* dts0100695760 - Illegal assign statement using clocking block
inputs is not being flagged as an error.
* dts0100697203 - VHDL ALIAS of unary operator function.
* dts0100698371 - Posedge on 2-D memory words inside generate not
triggering.
* dts0100698462 - View > Verification Management > Run Browser window
flashes non-stop.
* dts0100698812 - Incorrect simulation results with vopt.
Hierarchical references not preserved during pruneclktree.
* dts0100701176 - Memory allocation issue with vcover merge.
* dts0100702708 - Package dependencies corrupted by vlog -quiet
-incr.
* dts0100702875 - Subrange of a dynamic array is lost in function.
* dts0100704542 - Subelement association on out signal parameter
fails.
* dts0100704576 - Randomize() with {} scope issue.
* dts0100704806 - 2-D array assignment not occurring correctly with
-novopt.
* dts0100706310 - Initial call to populate a static associative array
gets optimized away.
* dts0100706976 - dpiheader generation missed svBitVecVal array
dimension for SV packed struct.
* dts0100708247 - "Cover Groups" GUI window does not display ALL
coverpoint instances.
* dts0100708342 - With a Project open, double clicking a file opens a
new simulation session.
* dts0100708440 - INTERNAL ERROR: pkgref: export lookup failed for
package.
* dts0100692691 - The stop-sync button causes the GUI to exit.
* dts0100695068 - Profiling icon is not available after a break.
* dts0100701524 - Wave window freezes after dragging object from sim
window.
* dts0100388690 - Enhancement to have the record remain expanded
after restarting simulation.
* dts0100707598 - WLF file crash.
* dts0100690860 - Unresolved reference to enum in unnamed block.
* dts0100693550 - Internal error: ../../../src/vlog/vrslvexpr.c(5283)
aliasOf(e).
* dts0100667531 - SV queue methods do not work correctly with real
data types.
* dts0100518778 - Error 211 Segmentation Violation on-loading when
design is optimized.
* dts0100693265 - next() function from enum returns wrong value with
-enumbaseinit.
* dts0100699009 - Array assignment problem with NBA.
* dts0100702269 - Incorrect implementation of atohex().
* dts0100702584 - SV array assignment pattern.
* dts0100698601 - INTERNAL ERROR: (vsim-8603) Package 'Package_Name'
has exported 599 items, but 597 items were expected.
* dts0100695499 - vopt miscompiles auto task enable within
fork/join_any block.
* dts0100704492 - Bit replicates assert during vl_reg_replicate.
* dts0100692688 - Recursive subprogram locally in a method of a
protected type.
* dts0100685061 - Segfault with non-shared variable of protected
type.
* dts0100703043 - Fatal error when passing parameter from SV to
SystemC.
* dts0100702880 - Crash with mixed language tran primitives.
* dts0100671761 - Fatal: Unexpected signal: 11 with Power Aware
simulation.
* dts0100701505 - MGC_LOCATION_MAP, different interpretation compared
to Falcon based tools like DA_IC.
* dts0100680412 - Symlink in /bin for "gdb" is broken.
_______________________________________________________________________
Known Defects in 6.6c
* On Windows platform, If Destructor breakpoint on SystemC object is
set via command "bp -c < function_name >", Debugger sometimes does
not stop at the breakpoint.
* On Windows platform, if breakpoint is set on a SystemC object
destructor, Debugger sometimes crashes while quitting simulation.
This crash can be avoided by setting env variable SC_NO_LIB_UNLOAD,
which will prevent unloading of the shared library.
* The simulator will hang if it tries to create a WLF file while
running on a Linux 64-bit operating system from a working directory
which does not support large files. One common instance of this is
executing an add wave command, when the working directory was
created under an older 32-bit Linux OS.
This is a Linux operating system bug and cannot be fixed by the
simulator.
A workaround for release 6.3 and above is to execute the simulator
with command line option -wlfnolock.
* The stack unwinder on the linux_x86_64 OS is unreliable. The
unwinder is the fundamental facility provided by the OS for
sampling where program execution is at. The unwinder is necessary
for gathering performance data. This is a known issue with this
specific OS and is why performance data will be incorrect or
non-existent on this platform.
* Users should be mindful of enabling both performance profiling and
memory profiling at the same time. Memory profiling requires much
overhead process, and it can skew the results of the performance
profiling data.
* On certain (RedHat) Linux Operating System versions the "-restore"
feature occasionally fails. This is due to the memory allocation
security (anti-hacking) feature of Linux. RedHat Enterprise release
v.3 update3 was the first version to have this security feature. In
these Linux releases two consecutive program invocations do not get
the same memory allocation foot-print. For the "-restore" feature
the simulator relies on having the same memory allocation
foot-print. Users are advised to re-try this feature a few times as
on average 3 out of 5 attempts are successful. In recent Linux
versions, an override for this anti-hacking feature is provided.
Please use it at your own discretion.
* Support of debugging C code during a quit command was disabled on
Windows. The corresponding C Debug command cdbg stop_on_quit was
also disabled on Windows.
* Specparams can be learned during the learn flow, but cannot be
found on consumption. The workaround is to use full +acc
deoptimization.
* On Red Hat Enterprise Linux release 5 platform, If SIGSEGV signal
occurs during the simulation and if CDEBUG is on, C-debugger traps
the signal, and when continued, vsim gets terminated right away,
instead of exiting with proper error status.
* The vpiPorts iteration on vpiEnumNet, vpiIntegerNet, and
vpiStructNet VPI objects has been disabled as it was incomplete and
unsafe to use.
* The following sequence of operations may cause a 'database locked'
error message:
$ vsim -debugdb <design>
VSIM 1> view schematic
VSIM 2> quit -sim
ModelSim> vsim -debugdb <design>
The workaround is to exit the simulator UI completely rather than
using just 'quit -sim'.
* The value annotation in the Schematic window has some known
limitations.
+ MUX output values are not shown in all cases.
+ Net slices are annotated with the full value of the net, not
the value of the slice. Gates that have a slice of a net as
input do not show a value on the output.
+ RTL function output values are not shown in all cases.
+ Concatenation symbols will not show output values.
+ Anytime a net is missing a value, downstream gates will also
not display any output value.
_______________________________________________________________________
Product Changes to 6.6c
* The file list specified by vlog's -f switch now accepts line
continuation.
* The vcover merge ... -combine option now has two new variant
options:
Both may be used to merge two or more different runs of a single
test, or re-joining stripped versions of a UCDB file (optional).
1. -combinemax: When using this argument, for nodes with
conflicting toggle information, the maximum count is saved in
the UCDB.
2. -combinemin: When using this argument, for nodes with
conflicting toggle information, the minimum count is saved in
the UCDB.
* The files and directories in the pre-compiled libraries (std, ieee,
pa_lib etc) are now write-protected.
* Several behavioral enhancements have been made to the Results
Analysis front-end commands:
+ An -append option has been added to the triage dbfile command
which will allow additional messages to be posted to the
database even if other messages exist under the same testname
as the message being inserted.
+ A -debug option has been added to the triage dbfile and triage
transform commands to display every message exported during
the course of the command.
+ The triage query command now returns its results instead of
simply echoing them to the transcript (so triage query can now
be used in scripts).
+ When the -wlfattr and/or -logattr options are used on the
triage dbfile command, the contents of the indicated UCDB
attributes are placed into the "wlfname" and "logname" columns
of the test table.
+ An error is generated if the -wlfattr or -logattr options are
used twice in the same command (they may, of course, be used
together -- once each).
+ If a WLF or plain-text LOG file is included directly on the
command line or in an "input file" designated by the
-inputsfile option, and that same file is referred to by a
test data record imported from a UCDB file specified in the
same command, the UCDB reference is ignored with a warning
(previously resulted in an error).
+ Any time a transformation overrides the value of the "time" or
"wlftimeunit" fields for a message, the value of
"normalizetime" is also changed unless the transformation also
happens to override "normalizetime".
+ The text of several error and informational messages has
changed to use more consistent terminology.
* SystemVerilog only. In some special situations structure literals
will be allowed to be written without the tick "'" preceding the
opening left curly-brace. This relaxation of the IEEE 1800
specification can be disabled with the flag -pedanticerrors.
* The default for VHDL Vital has been changed to VITAL 2000. To get
the behavior of previous releases you need to do the follow vmap
command
vmap IEEE $MODEL_TECH/../vital1995
If a design refers to both IEEE and VITAL2000 for the VITAL
libraries, then the logical library VITAL2000 must be remapped to
IEEE.
vmap VITAL2000 $MODEL_TECH/../ieee
* The new UCDB API adds two "levels of attribute indirection": where
an attribute can be a handle to:
1. refer to some other set of attributes or
2. refer to an array of attributes.
* Deprecated the q flag from the set of vopt +acc specifier
characters. vopt +acc=q is a synonym for vopt +acc=v
+floatgenerics, and thus is not a proper member of the orthogonal
+acc specifiers.
* The default behavior for the vsim command when the only argument is
a wlf file is to open a Wave window and add all signals in the
design to the window. This behavior has been changed. The signals
will no longer be added to the wave window. The user can change
this default behavior by modifying the PrefWave(OpenLogAutoAddWave)
setting. A true (1) value will enable the automatic add operation,
a false (0) value disabled this action.
* Wildcard matching for the UCDB API routines ucdb_PathCallBack() and
ucdb_MatchCallBack() have been enhanced.
Wildcarding:
* matches any substring within a level of hierar
chy
? preceding character is optional
[< int >:< int >] matches an integer index within the range
(< int|* > to < int|* >) matches an integer index within the range
(< int|* > downto < int|* >) matches an integer index within the range
* The 'vcover' tools have been extended to handle -warning, -error,
-note, and -suppress options. Note: Many vcover messages are
internal and use "printf" directly. These messages do not use the
message system (i.e. they do not have message numbers) and cannot
be controlled by these options.
* The -pedanticerrors flag will promote warnings in the LRM group of
messages to errors.
* Executables in the bin directory will default to 32-bit mode on
64-bit Linux machines unless MTI_VCO_MODE is set to 64. vco will
behave in a similar fashion.
* The acc and tf routines have been deprecated by the IEEE as of the
2005 standards. The tf_nodeinfo support for providing direct
pointer access to memories by way of the memoryval_p pointer has
now been removed. Although other information provided by
tf_nodeinfo will not be impacted, the memoryval_p will now provide
a null pointer for any memory.
* VHDL "for generate" equivalent blocks now have design pathnames
more in line with the LRM requirement. The name at each iteration
is constructed in the form [label] '(' [literal] ')', where [label]
is the generate statement label and [literal] is the value of the
generate parameter at that particular iteration. Prior releases
constructed the name using the generate statement label and the
position number of the value of the generate parameter at a
particular iteration and the [vsim] section GenerateFormat variable
(default value "%s__%d").
* Cross selection has been enhanced to include index and subfield
selection. When a signal is selected in one window, for example,
the Wave window, the corresponding signal is also selected in the
Objects window. If an index or field of a record is selected, the
item in the Objects window will be expanded and the appropriate
index or field will be selected.
* vlog will always create a package in the design library when the
-mfcu and the -cuname options are specified.
* The coverage system default behavior in the area of SystemVerilog
covergroups has changed. Specifically, it has changed to be
compliant with the latest IEEE 1800-2009 clarifications and
changes. The vsim switch -cvg63 reverts to the pre-6.6 behavior.
The switch -nocvg63 explicitly forces the new behavior.
This change has several aspects, each of which can be individually
reverted by SystemVerilog source code changes. The list of changes,
briefly, is as follows:
1. The default algorithm used to calculate the coverage score for
a covergroup type changes to an average-of-instances
algorithm, where the tool previously defaulted to the
merge-instances algorithm. This can now be controlled directly
by the type_option.merge_instances covergroup syntax. A
consequence of this change is that, by default, the supporting
data for the merge-instances algorithm is no longer collected.
Another visible consequence is that coverage numbers may
differ from previous versions, because they are calculated
using a different algorithm.
2. The reporting of per-instance data is also affected. In this
case, the 1800-specified behavior is that per-instance
reporting is suppressed if option.per_instance is 0 (the
default), and database storage of per-instance data is
optional in this case. In fact, the tool will save the
per-instance data, irrespective of this option, but the
reporting is affected and can be restored by setting
option.per_instance to 1.
3. The behavior of the get_inst_coverage() method also changes.
This was previously ambiguous where per_instance was set to 0.
The ambiguity was that if this option is set to have the
effect of not tracking the per-instance data, what response
should the tool provide, when this untracked data is queried
using get_inst_coverage()? The previous resolution to this
ambiguity was to default the get_inst_coverage() method
behavior to the get_coverage() method in this case. This
behavior is no longer ambiguous as the per-instance data is
now always tracked and always available from
get_inst_coverage(), even if per_instance is false. If
required, however, the original behavior can be restored by
setting the option.get_inst_coverage to 1.
* When using Causality Traceback after simulating with the -novopt
switch you will only have access to the Show Driver option in the
Source window. The Show Cause and Show Root Cause options will
display a warning.
* The "missing timescale" elaboration warnings (messages 3009 and
3010) are now elaboration errors. Having missing timescales
resulted in reduced performance in some cases, and the warnings
were easily overlooked. These errors can be reduced to warnings
with the vsim option -warning 3009,3010, and the +nowarnTSCALE
option continues to suppress the elaboration check. In addition, to
eliminate false errors the elaboration check no longer considers
modules that do not contain delays.
* Relaxed the checking of undefined DPI import C functions at
elaboration time. A warning is issued instead of a fatal error. If
the undefined DPI import C functions are called on runtime, a
runtime fatal error will be issued.
* Messages issued for SystemVerilog source code in packages may
produce different line numbers than previous versions of the
simulator.
* The random initial values generated by using +initreg option used
to be the same for different instantiations of a design unit. Now,
the simulator generates different random initial values for
different instances of a design unit when this option is enabled.
_______________________________________________________________________
New Features Added to 6.6c
* The radix signal command has been extended to support fixed point
radix using new option -fpoint.
radix signal <signal_name> -fpoint <number_of_fraction_bits>
* vlog's -E option now emits source code for files read via the -y
and -v switches.
* sccom, vopt and vsim have a new '-cppinstall <[gcc|g++] version> '
switch to specify the GNU compiler version supported and
distributed by Questa. To use
<product/install/directory>/gcc-4.3.3-linux/bin/g++, use <sccom |
vopt | vsim|> -cppinstall 4.3.3.
* Resolution of source and destination objects in all SignalSpy tasks
originating from Verilog regions now follows Verilog semantics.

#Mentor Graphics Search Data


#meta="doc.type.documentation.rn,product.version.6.6c,product.name.modelsim-se"