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2, FEBRUARY 2010

Operating With Reduced AC Power in the

DC-Link Capacitor

Isaac Soares de Freitas, Member, IEEE, Cursino Brandão Jacobina, Senior Member, IEEE,

and Euzeli Cipriano dos Santos Jr., Member, IEEE

put and output ac power synchronization to reduce the low fre-

quency ac power and the dc-link voltage fluctuation of a single-

phase full-bridge converter. The control technique is based on a

technique in which the load voltage is synchronized with the input

grid voltage for both constant (Mode I) and variable (Mode II)

phase angle. Such approach allows for a reduction in the capacitor

size. A capacitor bank design approach is also proposed. The tech-

nique has been achieved for the same input and output converter

frequency. Simulated and experimental results are addressed.

Fig. 1. Single-phase to single-phase full-bridge dc-link converter.

Index Terms—AC–AC power conversion, ac–dc power conver-

sion, pulsewidth modulated power converters.

INGLE-PHASE ac–ac power converter with a dc-link ca- eliminated. In this case, the input grid current is not sinusoidal

S pacitor can be obtained by using four legs (full-bridge con-

verter), three legs (shared-leg converter) and two legs (half-

and the dc-link voltage presents a noticeable fluctuation. The

dc-link capacitor can be also eliminated in bidirectional ac–ac

bridge converter) [1]–[3]. The full-bridge topology is shown in matrix or sparse matrix converter topologies, but in this case

Fig. 1. A wide class of single-phase equipments can be built from several bidirectional power switches are required [18].

single-phase ac–ac dc-link converters. This is the case of line Unlike three-phase converters, single-phase ones have low

voltage regulators, universal active power filters, standby power frequency ac power in the dc-link capacitor, which implies in

supplies, and uninterruptible power supplies [1], [2], [4]–[9]. additional complexity. Therefore, large capacitors are required

Single-phase ac–ac dc-link converters can also be found as part to maintain the dc-link ripple inside an acceptable range. The

of three-phase equipments [3]. This kind of converter provides dc-link capacitor of a diode rectifier single-phase-based con-

sinusoidal input current with unitary power factor, and it is effec- verter is reduced when the ac output voltage is synchronized

tive to protect the load against line disturbances. Consequently, with the dc-link ripple voltage [19]. Input–output voltage syn-

it is recommended to furnish stable ac voltage to critical loads, chronization technique has already been used in [20] to re-

such as computers, telecommunication systems, and biomedi- duce the extra ac capacitor power of a half-bridge single-phase

cal instrumentations. Most of these applications have same input converter.

and output converter frequencies. This paper presents a synchronization technique between in-

The reduction of the dc-link capacitor size and of the dc-link put and output ac powers, which permits to reduce the ac dc-link

voltage fluctuation is an important issue in the case of unidirec- power and, consequently, the dc-link capacitor size, of a single-

tional power switch three-phase two-level converters [10]–[15] phase full-bridge converter (Fig. 1). In such scheme, the outer

and multilevel converters [16], [17]. Among these papers, it can loop synchronization determines the input and output reference

converter voltages, which in turn, are the input of the pulse width

modulation strategy. That technique can be directly adapted and

Manuscript received January 6, 2009; revised March 2, 2009 and May 16, employed for three-leg and two-leg ac–ac dc-link converters

2009. Current version published February 12, 2010. This work was supported

by the National Council for Scientific and Technological Development, by the to reduce the ac capacitor power. The technique is suitable for

Coordination for the Improvement of Higher Education Personnel, and by the applications in which the grid and the load operate at same fre-

Foundation for Research Support of the State of Paraı́ba, Joao Pessoa, Brazil. quency. In this case, it is required the control of the input grid

Recommended for publication by Associate Editor J. R. Espinoza.

I. S. de Freitas is with the Department of Electrical Engineering, Federal Uni- current and the load voltage to follow sinusoidal constant fre-

versity of Paraiba, João Pessoa 58059-900, Brazil (e-mail: isaac@ct.ufpb.br). quency reference signals with unitary input power factor and

C. B. Jacobina and E. C. dos Santos, Jr., are with the Department of Electrical constant amplitude, respectively. This requirement is found for

Engineering, Federal University of Campina Grande, Campina Grande 58109-

970, Brazil (e-mail: jacobina@dee.ufcg.edu.br; euzeli@dee.ufcg.edu.br). example in line voltage regulators, universal active power filters,

Digital Object Identifier 10.1109/TPEL.2009.2031225 and uninterruptible power supplies.

0885-8993/$26.00 © 2010 IEEE

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DE FREITAS et al.: SINGLE-PHASE TO SINGLE-PHASE FULL-BRIDGE CONVERTER OPERATING 273

II. CONVERTER VOLTAGES (1 − µs ) tos ] of the switching period (T ). The apportioning fac-

The full-bridge converter (shown in Fig. 1) is connected to the tor can be changed as a function of the modulation index to

grid by the filter reactance Xg . It comprises an eight switches reduce the harmonic distortion (THD) of the converter volt-

power converter and a dc-link composed of a capacitor bank. ages [24], [25].

The output converter side is connected to the single-phase load Once the pole voltages have been defined, pulsewidths τg 1 ,

by the filter impedance Zf . Switch pairs qg 1 − q g 1 , qg 2 − q g 2 , τg 2 , τl1 , and τl2 can be calculated by using [21]

ql1 − q l1 , and ql2 − q l2 have complementary conduction states. T T

τj = + vj∗0 for j = g1, g2, l1, or l2 (11)

The conduction state of all switches can be represented by a 2 E

homonymous binary variable qg 1 , qg 2 , ql1 , and ql2 , where q = 1 where E = vc∗ is the reference dc-link voltage.

indicates a closed switch while q = 0 indicates an open one. Alternatively, gating signals can be generated by comparing

The converter grid voltage vg and the converter load voltage ∗

modulating signals vg∗10 , vg∗20 , vl10 ∗

, and vl20 with a high fre-

vl can be expressed as a function of the converter pole voltages quency triangular carrier signal.

vg 10 , vg 20 , vl10 , and vl20 , that depend on the power devices

conduction states, that is IV. DC-LINK CAPACITOR POWER AND VOLTAGE

vg = vg 10 − vg 20 = (qg 1 − qg 2 ) vc (1) From Fig. 1 and neglecting the switching fre-

quency effect, the system voltages and currents in

vl = vl10 − vl20 = (ql1 − ql2 ) vc (2)

steady state are eg (t) = Eg cos(ωg t), vg (t) = Vg cos(ωg t −

where, vc denotes the dc-link capacitor voltage. θg ), ig (t) = Ig cos (ωg t + φg ), vl (t) = Vl cos(ωl t + ε), and

il (t) = Il cos(ωl t + ε + φl ), where Vg , Vl , Ig , and Il are the

grid and load converter voltages and currents amplitude, re-

III. PULSEWIDTH MODULATION (PWM) STRATEGY

spectively; θg is the power angle, ε is a general load voltage

Carrier-based PWM [21]–[23] can be used to generate the phase angle, and φg and φl are the input and output power fac-

gating signals for the system as shown in Fig. 1. tor angles, respectively. The input and output power are given by

Considering that vg∗ and vl∗ are the desired reference voltages, pg (t) = vg (t) ig (t) and pl (t) = vl (t) il (t), respectively. Ne-

the reference pole voltages can be expressed as glecting the converter power losses, the dc-link capacitor power

can be written as

vg∗10 = vg∗ + vg∗20 (3)

Vg Ig Vl Il

∗

vl10 = vl∗ + vl20

∗

. (4) pc (t) = pg (t) − pl (t) = cos (θg + φg ) − cos(φl )

2 2

Relations (3)–(4) can be reformulated as Vg Ig

+ cos (2ωg t − θg + φg )

2

vg∗10 = vg∗ + vµg

∗

(5)

Vl Il

vg∗20 = vµg

∗

(6) − cos (2ωl t + 2ε + φl ) . (12)

2

∗

vl10 = vl∗ + ∗

vµl (7) Assuming no capacitor losses, the average value of pc in

∗

vl20 = ∗

vµl . (8) steady state must be zero. This means that the input and output

active power are the same. Hence, the first term in brackets must

The problem to be solved is how to determine vg∗10 , vg∗20 , be zero. Then

∗ ∗

vl10 ,and vl20 once the desired voltages vg∗ and vl∗ have been Vg Ig cos (θg + φg ) = Vl Il cos(φl ). (13)

∗ ∗

specified. The voltages vµg and vµl can be calculated by taking

the apportioning factor µs into account, i.e., and, therefore,

cos φl

∗ 1 ∗ ∗ pc (t) = Nl cos (2ωg t − θg + φg )

vµs = vc µs − − µs vsm ax + (µs − 1) vsm in (9) cos (θg + φg )

2

∗ ∗

− Nl cos (2ωl t + 2ε + φl ) (14)

where vsm ax = max (ϑs ) and vsm in = min (ϑs ), and ϑs =

{vs∗ , 0}, for s = g or l. Equation (9) was derived by using the where Nl = 1/2Vl Il is the load apparent power.

same approach as used to obtain the equivalent one for the From (14), the capacitor voltage can be achieved by solving

three-phase PWM modulator [24], [25]. dvc

The apportioning factor µs (0 ≤ µs ≤ 1) is given by pc = vc ic = Cvc , (15)

dt

tois i.e.,

µs = (10)

tos dvc Nl cos φl

vc = cos (2ωg t − θg + φg )

dt C cos (θg + φg )

and indicates the distribution of the free-wheeling period tos

(period in which voltages vs10 and vs20 are equal, for s = g

− cos (2ωl t + 2ε + φl ) (16)

or l) between the beginning (tois = µs tos ) and the end [tof s =

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274 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

Nl cos φl Nl Xcl fl cos φl

vc dvc = cos (2ωg t − θg + φg ) vcm in ≃E− +1 . (24)

C cos (θg + φg ) 2E fg cos (θg + φg )

Therefore,

− cos (2ωl t + 2ε + φl ) dt + ϑo (17)

Nl Xcl fl cos φl

∆vcm ax ≃ +1 . (25)

E fg cos (θg + φg )

cos φl

vc2 = Nl Xcg sin (2ωg t − θg + φg )

cos (θg + φg ) From (25), it can be seen that the increase of the capacitance

size reduces the peak-to-peak voltage.

− Xcl sin (2ωl t + 2ε + φl ) + ϑo (18) For same grid and load frequencies (ωg = ωl = ω) and uni-

tary input power factor (cos φg = 1), (22) can be written as

where Xcg = ω g1C , Xcl = ω l1C and ϑo is a dc value. follows:

Therefore, the capacitor voltage can be written as follows: Nl X c

vc (t) ≃ E + kε cos (2ωt + β) (26)

2E

vc = ϑ o + ∆ (19)

where

where

kε = kφ2 − 2kφ cos (θg + 2ε + φl ) + 1

cos φl fl

∆ = Nl Xcl sin (2ωg t − θg + φg ) cos φl 1

cos (θg + φg ) fg kφ = , Xc = and

cos θg ωC

− sin (2ωl t + 2ε + φl ) (20)

cos φl − cos (2ε + φl )

β = arctan .

cos φl tan θg + sin (2ε + φl )

and fl and fg are the load and grid frequencies, respectively.

√

By expanding (19) in Taylor series around vc = ϑo = E Consequently, for same input and output frequencies, the ac

(once the dc-link voltage is well known as being composed of voltage can be reduced by increasing the capacitor C, or through

a dc value overlapped by a small ac component) the dc-link reducing kε by proper choosing the value of phase angle dis-

voltage can be expressed as follows: placement ε.

The maximum and minimum values of vc (t) are given by

∞ n+1 n

∆ ∆2 (−1) ∆ n

Nl X c

vc = E + − + (2j −3). vcm ax ≃ E + kε (27)

2E 8E 3 n = 3 n! 2n E 2n −1 j = 2 2E

(21) Nl X c

vcm in ≃ E − kε . (28)

The power series in (21) shows that the capacitor voltage is 2E

composed of a dc component and an ac component with in- Consequently, the maximum capacitor voltage fluctuation

finite number of frequencies. However, for practical values of ∆vcm ax = vcm ax − vcm in is given by

the capacitor size and the dc-link reference voltage, the capac-

itor voltage is well represented by the first two terms in (21) Nl X c

∆vcm ax ≃ kε . (29)

(i.e., E + ∆/2E). This approximation results in the following E

expression: Next, it will be shown in a synchronization technique, be-

tween input and output voltages, that results in reduction of

Nl Xcl fl cos φl

vc ≃ E + sin (2ωg t − θg + φg ) kε .

2E fg cos (θg + φg ) This analysis can be expanded to take into account the ex-

istence of harmonic in the input voltage. In this case, it can

− sin (2ωl t + 2ε + φl ) . (22) be shown that the maximum capacitor voltage fluctuation has

an additional smaller term proportional to the amplitude of the

Therefore, the value of the ac capacitor voltage frequency is harmonic and the inverse of its frequency.

near twice that of the input and output frequencies.

In order to analyze voltage fluctuation, let us define V. SYNCHRONIZATION TECHNIQUE

the maximum (peak-to-peak) capacitor voltage as ∆vcm ax =

vcm ax − vcm in , where vcm ax and vcm in are the maximum In the case of same grid and load frequencies, i.e., ωg =

and minimum values of vc (t) given by (22). The maxi- ωl = ω, input and output voltages synchronization can be used

mum value (vcm ax ) occurs when sin (2ωg t − θg + φg ) = 1 to reduce kε and the capacitor voltage fluctuation as well.

and sin (2ωl t + 2ε + φl ) = −1, simultaneously, and the min- The term kε reaches its maximum and minimum value for

imum value (vcm in ) occurs when sin (2ωg t − θg + φg ) = −1 ε = − (θg + φl + π) /2 and ε = −(θg + φl )/2, respectively.

and sin (2ωl t + 2ε + φl ) = 1, simultaneously. Hence, This can be also seen from the expression (14) for dc-link ca-

pacitor power.

Nl Xcl fl cos φl The boost filter reactance Xg can be chosen based on the

vcm ax ≃ E + +1 (23)

2E fg cos (θg + φg ) input current ripple and voltage drop along the inductor for

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DE FREITAS et al.: SINGLE-PHASE TO SINGLE-PHASE FULL-BRIDGE CONVERTER OPERATING 275

In order to correctly apply the input voltage with amplitude

Vg and the output voltage with amplitude Vl , the dc-link voltage

vc has to be larger than both Vg and Vl at any instant. Therefore,

the minimum value of vc given in (24) must satisfy

vcm in ≥ max(Vg , Vl ). (30)

By choosing the case limit, i.e., vcm in = max(Vg , Vl ), the

impedance Xcl can be written from (24) as

E − max (Vg , Vl )

Xcl = . (31)

2

Nl fl 2N l X g cos φ l

2E fg cos φl 1+ E g2 +1

Once load and grid voltages are specified, the average value of

the capacitor voltage must be chosen based on the acceptable dc

voltage fluctuation (E − max (Vg , Vl )). Hence, the impedance

Xcl , and consequently the capacitor C, can be calculated from

(31).

On other hand, when grid and load frequencies are the same,

from (28) the impedance Xc can be written as

E − max (Vg , Vl )

Xc = Nl

. (32)

2E kε

By using Mode II of the synchronization technique (ε =

θ +φ

− g2 l), expression (32) can be written as

E − max (Vg , Vl )

Xc = N l cos φ l

. (33)

2E cos θ g − 1

Fig. 2. (a) k ε as a function of the load power factor φ l for ε = 0, ε = −(θg +

φ l )/2 and ε = −(θg + φ l + π)/2. (b) Optimum angle ε and the power angle Therefore, the capacitor can be designed from (33) based on:

θg as a function of load power factor. the maximum value of dc power (Pl = Nl cos φl ); the chosen

dc-link voltage (E); the maximum acceptable voltage fluctua-

tion (E − max (Vg , Vl )); the maximum load power factor angle

(φlm ax ); and the maximum power angle (θg m ax = ±12◦ ).

maximum load power. It was shown by [26] that a boost filter

The capacitor size reduction achieved with the synchroniza-

reactance of Xg = 0.2 pu satisfy both design requirements. If

tion technique (32), when compared to the general case (31),

Xg = 0.2 pu, then the power angle θg is limited to θg m ax ≃ 12◦ ,

can be indicated by

i.e., |θg | ≤ 12◦ , when the system power varies from no-load to

full-load condition. C2 Xcl kε

δc = = = cos φ l f l

(34)

√ Assuming rated conditions (Nl = 1 pu and Vl = Eg = C1 Xc cos θ g f g +1

2 pu for root mean square voltages at 1 pu), kε is illus-

trated in Fig. 2(a) for ε = 0◦ , ε = − (θg + φl ) /2, and ε = where C1 and C2 are the required capacitance value for same

− (θg + φl + π) /2, as a function of load power factor (φl ≤ 0 voltage fluctuation in the general case and when the synchro-

implies in inductive load and φl ≥ 0 implies in capacitive nization technique is used, respectively. Hence, when the syn-

load). The term kε reaches zero when ε = − (θg + φl ) /2 chronization technique is used, the required capacitance is only

and θg = ±φl , i.e., cos(θg ) = cos(φl ), and when ε = 0 and a fraction δc of the capacitance required in the general case.

θg = −φl . Fig. 2(b) shows the optimum angle ε and the power By using Mode II of the synchronization technique (ε =

angle θg as a function of load power factor. −(θg + φl )/2) and fl /fg = 1, the expression for δc in (34)

Two modes of synchronization for vl can be conceived: in can be written as

Mode I, vl is synchronized with eg with ε constant equal to cos φl − cos θg

δc =

. (35)

ε∗ (ε∗ being the rated value of − (θg + φl ) /2 or simply 0), or cos φl + cos θg

Mode II, vl is synchronized with eg with ε variable equal to

− (θg + φl ) /2 (using measured values of θg and φl ). Mode I is √ Assuming rated conditions (Nl = 1◦pu and Vl = Eg =

the simplest one and Mode II can be used if φl and θg change 2 pu), δc is illustrated in Fig. 3 for ε = 0 , ε = − (θg + φl ) /2,

slowly and the load frequency ωl is allowed to change with a and ε = − (θg + φl + π) /2, as a function of load power factor.

tolerance ∆ωlm ax , i.e., ωl = ωlN ±∆ωlm ax , where ωlN is rated One can see from Fig. 3 that the capacitor can be significantly

load frequency. In Mode II the reduction of ∆vc is maximal. decreased by using the synchronization technique. On other

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276 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

Fig. 3. Relation δc (C 2 /C 1 ) between the capacitance in general case (C 1 )

and that with synchronization technique (C 2 ).

The synchronization is implemented in Modes I and II. In

Mode II, the power factor angle φl and the input power angle θg

TABLE I

CAPACITANCE SIZE REDUCTION AS A FUNCTION OF THE POWER FACTOR ANGLE must be measured. In this paper, these angles were measured by

using a cross-zero detector scheme applied to the reference load

voltage vl∗ and measured load current il to determine φl , and

applied to reference grid voltage vg∗ and measured grid current

ig to determine θg .

hand, when the load power factor is close to zero, no capacitor The synchronization is achieved by using block SYNe.

reduction is achieved. However, this condition is not a usual Modes I and II are selected by the switch ks . The block GENvl

case. is similar to block GENig .

The capacitor size reduction is mainly a function of the max-

imum load power factor angle. In Table I, δc is given for eight VIII. SIMULATION RESULTS

values of load power factor angle. Even if the load power fac- The parameters used in the simulation tests were fs =

tor is small as cos φl = 0.33, the required capacitance for same 10 kHz, C = 1100 µF, Lg = 10 mH, Eg = Vl = 220 V, ωl =

ripple is half of the one in the general case. ωg = 120 πrad/s, and E = 350 V.

The capacitor design presented here was based on the case of Fig. 5(a) and (b) shows the simulated capacitor volt-

ideal capacitor and steady-state, where no dc power is absorbed age (top), grid current (middle) and load current (bottom)

by the capacitor. However, real capacitors appear to have a dc for ε = −(θg + φl )/2 (Mode II) and ε = −(θg + φl + π)/2,

power component term. An additional parameter to incorporate respectively.

this fact on the capacitor model is the equivalent series resistance The case of no synchronization is implemented considering

(ESR). This term has the effect of increasing the total dc-link ε = −(θg + φl + π)/2, which means the worse case of syn-

voltage. Moreover, the dc-link voltage becomes noisier due to chronization, or, in other words, when the rectifier and inverter

the series resistance voltage been submitted to high frequencies operates with different frequencies. In this case, when the syn-

capacitor power. However, the ESR decreases with the increase chronization technique is applied, the reduction in the dc-link

of the capacitor size and frequency. In fact, it is smaller than voltage fluctuation is close to 80%.

0.1 Ω for an electrolytic 1000 µF capacitor. Therefore, the net

effect on the capacitor size caused by the ESR can be neglected.

IX. EXPERIMENTAL RESULTS

The full-bridge converter has been implemented in the lab-

VII. CONTROL SYSTEM oratory. The set-up used in the experimental tests is based

Fig. 4 presents the block diagram of the proposed control on a microcomputer equipped with appropriate plug-in boards

system. The dc-link voltage vc is controlled at a reference value and sensors. In the experimental tests the following parame-

by using controller Rc that provides the amplitude of the ref- ters were used: fs = 10 kHz, C = 1100 µF, Lg = 6 mH, and

erence current Ig∗ . The instantaneous reference current i∗g is ωl = ωg = 120 πrad/s.

synchronized with eg in order to control the power factor. This Fig. 6(a)–(c) shows experimental results for the converter sup-

synchronization is obtained via blocks SYNe and GENig . The plying a RL single-phase load (Pl = 125 W, cos φl = 0.946)

synchronization is implemented by processing eg through a zero with Eg = Vl = 100 V and E = 120 V. The waveforms in these

crossing detector followed by a phase-comparator. The output figures are the capacitor voltage for ε = 0 – Mode I – (top), ε =

angle δg of block SYNe indicates the instantaneous phase of eg . −(θg + φl )/2 – Mode II – (middle) and ε = −(θg + φl + π)/2

The current controller is implemented using a controller indi- (bottom). As expected from the theoretical analysis, the fluctu-

cated by the block Rg . The controller Rl defines Vl∗ , in the case ation reduction in the dc-link voltage is obtained with synchro-

in which an output closed loop is required. nization technique, especially for Mode II, which provides 85%

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DE FREITAS et al.: SINGLE-PHASE TO SINGLE-PHASE FULL-BRIDGE CONVERTER OPERATING 277

Fig. 7. Peak–peak capacitor voltage fluctuation (top) and peak grid current for

several values of load power with and without the proposed algorithm (bottom).

Fig. 5. Simulated (top) capacitor voltage, (middle) grid current, and (bottom)

load current. (a) ε = − (θg + φ l ) /2. (b) ε = − (θg + φ l + π) /2.

Fig. 6. Experimental (top) ac capacitor voltage for ε = 0, (middle) ε = (middle), load voltage and current (bottom) for cos φ l = 0.99. (a) ε =

− (θg + φ l ) /2 and (bottom) ε = − (θg + φ l + π) /2. − (θg + φ l ) /2. (b) ε = − (θg + φ l + π) /2.

of reduction when compared to the worst case. On the other power ranging from 100 to 2000 W and constant power factor

hand, Mode I gives 70% of reduction in the dc-link voltage cos (φl ) = 0.99. The tests were carried out with the Mode II

fluctuation. But besides that, in Mode I, it is not necessary to and without the algorithm when the maximum dc-link voltage

acquire the load power factor. fluctuation might happen considering ε = −(θg + φl + π)/2. It

Fig. 7 shows the experimental value of peak-to-peak capac- can be seen that dc-link capacitor voltage fluctuation increases

itor voltage and input peak current for several values of load with the load power when the algorithm was not used. On the

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278 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

Fig. 9. Experimental capacitor voltage (top), grid voltage and current Fig. 10. Experimental results with distortion in the grid voltage (20% of third

(middle), load voltage and current (bottom) for cos φ l = 0.55. (a) ε = harmonic). (a) ε = − (θg + φ l ) /2. (b) ε = − (θg + φ l + π) /2.

− (θg + φ l ) /2. (b) ε = − (θg + φ l + π) /2.

voltage fluctuation constant, even changing the power load. In

this test and in the next ones, it was used Eg = Vl = 220 V and

E = 350 V.

Figs. 8 and 9 show the capacitor voltage, grid voltage and

current, filtered load voltage, and load current for Pl = 1200 W

with cos φl = 0.99 and cos φl = 0.55 for ε = −(θg + φl )/2

and ε = −(θg + φl + π)/2. Note that the voltage fluctuation

is smaller when the technique is used and it increases, when

decrease the load power factor.

Fig. 10(a) and (b) shows the grid voltage and current, load

voltage and dc-link voltage with and without the synchroniza- Fig. 11. Experimental load transient for a change of load from 2000 to 100 W

tion technique. These results are obtained for the case in which and back to 2000 W.

there is 20% of third harmonic present in the grid voltage. Even

in this case, the control technique permit to reduce the dc-link

voltage fluctuation. X. CONCLUSION

Fig. 11 shows the capacitor voltage, grid current, load current This paper has presented a synchronization technique to re-

for a change of load from 2000 to 100 W and back to 2000 W. duce the ac power and voltage fluctuation in the dc-link of

Note that, even in the case of hard load transient the dc-link single-phase full-bridge converters. It has been considered vi-

voltage is under control. In Fig. 11, a different waveform pre- able for applications where the load frequency is equal to the

sentation was used (obtained from oscilloscope). input frequency. Two modes of synchronization for the converter

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DE FREITAS et al.: SINGLE-PHASE TO SINGLE-PHASE FULL-BRIDGE CONVERTER OPERATING 279

voltages were proposed. In Mode I, the converter load voltage is [19] P. Jain, D. Vincenti, and H. Jin, “An optimized single-phase AC power sup-

synchronized with the grid voltage with a constant phase angle. ply with DC bus synchronization,” in Proc. IEEE APEC, 1996, pp. 905–

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In Mode II the converter load voltage is synchronized with grid [20] C. B. Jacobina, I. S. de Freitas, E. C. dos Santos, Jr., E. R. da Silva, and T.

voltage for a variable phase angle equal to − (θg + φl ) /2. In M. Oliveira, “Dc-link single-phase to single-phase half-bridge converter

Mode II, the reduction of the ac dc-link power is maximal. The operating with reduced capacitor current and ac capacitor power,” in Proc.

IEEE PESC, 2006, pp. 1716–1722.

technique can be directly adapted to be used for three-leg and [21] J. Holtz, “Pulsewidth modulation for electronic power conversion,” Proc.

two-leg ac–ac dc-link converters, in order to reduce the ac dc- IEEE, vol. 82, no. 8, pp. 1194–1214, Aug. 1994.

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PWM technique with minimum switching losses and a variable pulse

sented to demonstrate the effective performance of the method. rate,” IEEE Trans. Ind. Electron., vol. 44, no. 2, pp. 173–181, Apr. 1997.

[23] O. Ojo and P. M. Kshirsagar, “Concise modulation strategies for four-leg

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phase UPQC with minimum VA loading,” IEEE Trans. Power Del., University, College Station, as a Visiting Scholar. He

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M. Hernando, “Simplified voltage-sag filter for line-interactive uninter- July 2008, where he is currently a Professor of electrical engineering. His re-

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1993, pp. 306–311. ina Grande, in 1978, and the Diplôme d’Etudes

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“A general PWM strategy for four-switch three-phase inverters,” IEEE engineering. His research interests include electrical drives, power electronics,

Trans. Power Electron., vol. 21, no. 6, pp. 1618–1627, Nov. 2006. and energy systems.

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limiting the dc-link voltage fluctuation for a doubly fed induction wind born in Picuı́, Paraı́ba, Brazil, in 1979. He received

generator,” IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1205–1213, the B.S., the M.S., and the Ph.D degrees in electrical

May 2008. engineering from the Federal University of Campina

[16] O. Bouhali, B. Francois, E. Berkouk, and C. Saudemont, “Dc link capacitor Grande, Campina Grande, in 2004, 2005, and 2007,

voltage balancing in a three-phase diode clamped inverter controlled by a respectively.

direct space vector of line-to-line voltages,” IEEE Trans. Power Electron., From 2006 to 2007, he was with the Electric Ma-

vol. 22, no. 5, pp. 1205–1213, Sep. 2007. chines & Power Electronics Laboratory, Texas A&M

[17] H. Zhang, S. J. Finney, A. Massoud, and B. W. Williams, “An SVM University, College Station, as a Visiting Scholar.

algorithm to balance the capacitor voltages of the three-level NPC active From August 2006 to March 2009, he was with the

power filter,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2694–2702, Centro Federal de Educação Tecnológica da Paraı́ba,

Nov. 2008. UNED/CZ, Cajazeiras. He has been with the Department of Electrical Engi-

[18] J. Kolar, F. Schafmeister, S. Round, and H. Ertl, “Novel three-phase AC- neering, Federal University of Campina Grande, since March 2009, where he

AC sparse matrix converters,” IEEE Trans. Power Electron., vol. 22, no. 5, is currently a Professor of electrical engineering. His research interests include

pp. 1649–1661, Sep. 2007. power electronics and electrical drives.

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