Paper Title
VHDL Implementation of 128 bit Pipelined Blowfish Algorithm
Authors
Dakey Rahul Khanna, N. Srikanth, Dr. B. Subrahmaneswara Rao
Abstract
Communication through public networks imposes threat to our sensitive data. Information security plays an important role in public networking and wireless communication. In order to achieve the protection of information or private data in networking, Cryptography can be used. It is the automated method in which security goals are accomplished. Cryptographic algorithm is a mathematical function used in Encryption and Decryption process. Blowfish is a keyed symmetric Cryptographic algorithm. It is a very fast and useful scheme for Encryption and Decryption. A key is the strongest point of any algorithm but it can become the weakest point if it is not secured. Our information can be secured if it is encrypted by using multiple keys. Hence implementation of Blowfish algorithm is very much use. Usually blowfish in existing method is 64 bit block cipher and Throughput depends on the size of the blocks applied. In this proposed paper, the blowfish algorithm is designed for 128 bit block size and pipelining operation is carried to improve the speed and reduce the delay accordingly, and so that this architecture improves the throughput of an encoder. The implementation results indicate that the proposed pipelined architecture shows 10% of improvement in Throughput. VHDL Implementation of proposed architecture has done by using XILINX ISE 9.1.
Keywords
Cryptography, blowfish, pipelined architectures.
Citation/Export
MLA
Dakey Rahul Khanna, N. Srikanth, Dr. B. Subrahmaneswara Rao, “VHDL Implementation of 128 bit Pipelined Blowfish Algorithm”, November 17 Volume 3 Issue 11 , International Journal on Future Revolution in Computer Science & Communication Engineering (IJFRSCE), PP: 548 – 552
APA
Dakey Rahul Khanna, N. Srikanth, Dr. B. Subrahmaneswara Rao, November 17 Volume 3 Issue 11, “VHDL Implementation of 128 bit Pipelined Blowfish Algorithm”, International Journal on Future Revolution in Computer Science & Communication Engineering (IJFRSCE), PP: 548 – 552

© All Rights Reserved

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Paper Title
VHDL Implementation of 128 bit Pipelined Blowfish Algorithm
Authors
Dakey Rahul Khanna, N. Srikanth, Dr. B. Subrahmaneswara Rao
Abstract
Communication through public networks imposes threat to our sensitive data. Information security plays an important role in public networking and wireless communication. In order to achieve the protection of information or private data in networking, Cryptography can be used. It is the automated method in which security goals are accomplished. Cryptographic algorithm is a mathematical function used in Encryption and Decryption process. Blowfish is a keyed symmetric Cryptographic algorithm. It is a very fast and useful scheme for Encryption and Decryption. A key is the strongest point of any algorithm but it can become the weakest point if it is not secured. Our information can be secured if it is encrypted by using multiple keys. Hence implementation of Blowfish algorithm is very much use. Usually blowfish in existing method is 64 bit block cipher and Throughput depends on the size of the blocks applied. In this proposed paper, the blowfish algorithm is designed for 128 bit block size and pipelining operation is carried to improve the speed and reduce the delay accordingly, and so that this architecture improves the throughput of an encoder. The implementation results indicate that the proposed pipelined architecture shows 10% of improvement in Throughput. VHDL Implementation of proposed architecture has done by using XILINX ISE 9.1.
Keywords
Cryptography, blowfish, pipelined architectures.
Citation/Export
MLA
Dakey Rahul Khanna, N. Srikanth, Dr. B. Subrahmaneswara Rao, “VHDL Implementation of 128 bit Pipelined Blowfish Algorithm”, November 17 Volume 3 Issue 11 , International Journal on Future Revolution in Computer Science & Communication Engineering (IJFRSCE), PP: 548 – 552
APA
Dakey Rahul Khanna, N. Srikanth, Dr. B. Subrahmaneswara Rao, November 17 Volume 3 Issue 11, “VHDL Implementation of 128 bit Pipelined Blowfish Algorithm”, International Journal on Future Revolution in Computer Science & Communication Engineering (IJFRSCE), PP: 548 – 552

© All Rights Reserved

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_______________________________________________________________________________________________

Student, M.Tech , VLSISD,Dept. of Associate Professor, Dept. of ECE, Professor, Dept. of ECE

ECE, Swarnandhra College of Engg. &Tech. Swarnandhra College of Engg. &Tech.

Swarnandhra College of Engg. &Tech. Narsapur , A.P,India. Narsapur , A.P,India.

Narsapur , A.P,India. e-mail: srikanth648@yahoo.co.in e-mail: boyina_a@yahoo.com

e-mail: rahulkhanna556@gmail.com

Abstract–– Communication through public networks imposes threat to our sensitive data. Information security plays an important role in public

networking and wireless communication. In order to achieve the protection of information or private data in networking, Cryptography can be

used. It is the automated method in which security goals are accomplished. Cryptographic algorithm is a mathematical function used in

Encryption and Decryption process. Blowfish is a keyed symmetric Cryptographic algorithm. It is a very fast and useful scheme for Encryption

and Decryption. A key is the strongest point of any algorithm but it can become the weakest point if it is not secured. Our information can be

secured if it is encrypted by using multiple keys. Hence implementation of Blowfish algorithm is very much use. Usually blowfish in existing

method is 64 bit block cipher and Throughput depends on the size of the blocks applied. In this proposed paper, the blowfish algorithm is

designed for 128 bit block size and pipelining operation is carried to improve the speed and reduce the delay accordingly, and so that this

architecture improves the throughput of an encoder. The implementation results indicate that the proposed pipelined architecture shows 10% of

improvement in Throughput. VHDL Implementation of proposed architecture has done by using XILINX ISE 9.1.

__________________________________________________*****________________________________________________

I. INTRODUCTION

Embedded devices are becoming more popular and that only intended user can use it and other devices are

used in network communications. These devices are now used prevented from using it without proper authentication. In

commonly for storing data and exchange of data through certain applications data security from tampering is mandatory

public networks. Wireless networking imposes threat to the by law. The applications like electronic engine controllers are

sensitive data. To protect sensitive data against threat required to be protected from tampering emission and

embedded devices are designed with inbuilt security features. performance data. Devices used to store medical data and

The sensitive data is encrypted before transmission so that utility meter like taxi, gas, electricity must be tamperproof.

only authorized user can have access to such information. Devices can be secured with passwords, identification

Hardware implementation of encryption algorithm is helpful in numbers, or tokens. The devices can be designed with better

designing secured Embedded System. security using cryptography.

Modern embedded systems need data security more

II. RELATED WORK

than ever before. It is now common to see portable electronic

devices of all sorts, ranging from cellular phones to military It was concluded in [8] that AES is faster and more

radio systems and from inventory tracking systems to medical efficient than other encryption algorithms. When the trans-

record tablets. Devices like PDAs and cell phones store mission of data is considered there is insignificant difference

personal e-mail and contact lists [1]. GPS receivers keep logs in performance of different symmetric key schemes (most of

of our movements and our automobiles record our driving the resources are consumed for data transmission rather than

habits. User-friendly products are in demand which can be computation). Even under the scenario of data transfer it

reprogrammed during normal use and add new features as would be advisable to use AES scheme in case the encrypted

firmware upgrades become available. The user expects that the data is stored at the other end and decrypted multiple times.

system should be protected from unauthorized access. A study in [9] is conducted for different popular

Embedded device manufacturers expect protection of secret key algorithms such as DES, 3DES, AES, and Blowfish.

their systems from unauthorized duplication or reverse They were implemented, and their performance was compared

engineering. Cryptography can be used to secure private data by encrypting input files of varying contents and sizes. The

and keep it private. Encrypted data transmission will protect algorithms were tested on two different hardware platforms, to

contact lists and personal e-mail from unauthorized or compare their performance. They had conducted it on two

unintended persons. Firmware upgrades can be encrypted so different machines: P-II 266 MHz and P-4 2.4 GHz. The

548

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International Journal on Future Revolution in Computer Science & Communication Engineering ISSN: 2454-4248

Volume: 3 Issue: 11 548 – 552

_______________________________________________________________________________________________

results showed that Blowfish had a very good performance IV. PROPOSED DESIGN

compared to other algorithms. Also it showed that AES had a There are software and hardware approaches to

better performance than 3DES and DES. It also shows that implement cryptographic Blowfish algorithm. Hardware

3DES has almost 1/3 throughput of DES, or in other words it implementation provides greater physical security and higher

needs 3 times than DES to process the same amount of data speed as compared to software implementation. Because of the

[10]. increasing requirement to implement cryptographic algorithms

A study in [11] provides evaluation of six of the most in fast rising high-speed network applications combined with

common encryption algorithms namely: AES, DES, 3DES, physical security, hardware implementation becomes essential.

RC2, Blowfish, and RC6. A comparison has been conducted

for those encryption algorithms at different settings for each

algorithm such as different sizes of data blocks, different data

types, battery power consumption, different key size and

finally encryption/decryption speed. Several points can be

concluded from the Experimental results. Firstly; there is no

significant difference when the results are displayed either in

hexadecimal base encoding or in base 64 encoding. Secondly;

in the case of changing packet size, it was concluded that

Blowfish has better performance than other common

encryption algorithms used, followed by RC6. Thirdly; we

find that 3DES still has low performance compared to Figure 1: Blowfish Algorithm Design Blocks

algorithm DES. Fourthly; we find RC2, has disadvantage over The encrypter is required to be designed as integrated

all other algorithms in terms of time consumption. Fifthly; we part of the system in order to attain superior performance.

find AES has better performance than RC2, DES, and 3DES. Embedded system designs are constraint by space, memory

In the case of audio and video files we found the result as the and time. Lookup tables are considered for S box and P array

same as in text and document. Finally, in the case of changing implementations which will generate keys fast and

key size, it can be seen that higher key size leads to clear precomputed values can be retained for encryption and

change in the battery and time consumption. decryption. The symmetric nature of Blowfish helps in

reutilizing hardware for encryption and decryption which

III. ALGORITHM further reduces area requirement or space. Blowfish is feistel

There are two parts to this algorithm; a part that handles the network. This simplifies encryption and decryption realization

expansion of the key and a part that handles the encryption of in hardware.

the data.The first step in the algorithm is to break the original Input plain text is applied to the core Blowfish cipher

key into a set of subkeys. Specifically, a key of no more than block. Input will be processed as block of 64 bits. Each 64 bit

448 bits is separated into 4168 bytes. There is a P-array and data further bifurcated into two 32bit data, in order to apply to

four 32-bit S-boxes. The P-array contains 18 32-bit subkeys, the cipher block. While applying data to the feistel block

while each S-box contains 256 entries. Padding will be done for framing data as multiple of 8 bits. Π

The following steps are used to calculate the subkeys: ROM will give initial key values to S Box. 32bit are divided

into four groups of 8 bit each. It acts as address for selecting

Initialize the P-array and S-boxes precomputed substitution values of S box. Permutation values

XOR P-array with the key bits. For example, P1 XOR are computed using lookup table. Data obtained from four S-

(first 32 bits of key), P2 XOR (second 32 bits of key), boxes further underwent to Arithmetic operations to get 32bit

Use the above method to encrypt the all-zero string random data. The sub key of length 32 bit obtained from P

This new output is now P1 and P2 array elements which are XORed and given to F function.

Encrypt the new P1 and P2 with the modified

subkeys.

This new output is now P3 and P4

Repeat 521 times in order to calculate new subkeys

for the P-array and the four S-boxes

Blowfish has a 64-bit block size and a key length of

anywhere from 32 bits to 448 bits. It is a 16-round Feistel

cipher and uses large key-dependent S-boxes. It is similar in

structure to CAST-128, which uses fixed S-boxes. Here is the

Figure 2: Proposed Memory-based Method

visual representation of this encryption algorithm.

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_______________________________________________________________________________________

International Journal on Future Revolution in Computer Science & Communication Engineering ISSN: 2454-4248

Volume: 3 Issue: 11 548 – 552

_______________________________________________________________________________________________

The architecture of the proposed Blowfish consists of path delay will be of the order of 21.618ns. The building block

a 128-bit block size and 64bit key size, whereby it comprises comprised of logic for performing XOR operation between

two parallel blocks of 64-bit Blowfish algorithm that are key and data and feistel function using S-boxes.

simultaneously executed. This design technique enables the

throughput of the Blowfish algorithm to be maximized. The

parallel blocks share the same S-box that is used for the F

function. As the implementation of the Blowfish design is

targeted to reduce the core size and timing delay, The

implementation for the blow fish using S-boxes can be

replaced with the proposed method uses a read-only memory

(ROM) that contains 1024 × 32-bit input data of addr. The

addr represents the data of four 32-bit S-boxes. The 32-bit

output data are read from the ROM. The proposed method can

Figure 4: Black box of building block of the Design

also lessen the total of slices used by the Blowfish design. A

implementation.

slice contains a set number of look-up tables (LUTs), FFs, and

multiplexers. Thus, less logic resources are used to perform

logic, arithmetic, and ROM functions that can lead to a faster

encryption/decryption process.

This implementation of Hardware block can be

reused two times to perform 128bit operation by means of Figure 5: internal implementation of building block.

selector and de-selector blocks aided to the above design. That

is the proposed implementation of the Blowfish algorithm. The As the single block to perform 64bit operation requires

design can be further modified to a pipelined implementation 21.618ns, to perform 128bit operation by reusing the block

of blowfish algorithm for improved performance as shown in for two times requires 43.236ns. Hence pipelining can be

the figure. introduced by inserting registers between every two building

blocks and make sure that the time lag between two clock ticks

must be at least 43.236ns. Hence the proposed improved

throughput pipelined blowfish Algorithm can work at the

application of maximum clock frequency of 23.128MHz.

64bit fixed block cipher implemented in standard

blowfish hardware architecture by make use of 4 S-boxes

whose entries are calculated from the key and are independent

of both data and key while executing. The RTL (Register

Transfer Level) diagram and Design summary of implemented

Blowfish Algorithm are as shown below. The hardware

description done using VHDL and the synthesis of the design

done for Vertex E FPGA.

Algorithm

Figure 3: Block Diagram of improved throughput pipelined

The black box of improved throughput

blowfish Algorithm

blowfish Algorithm is as shown below. It generates 128bit

If we observe the feistel block implementation, which

is the building block, in hardware using VHDL the critical

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IJFRCSCE | November 2017, Available @ http://www.ijfrcsce.org

_______________________________________________________________________________________

International Journal on Future Revolution in Computer Science & Communication Engineering ISSN: 2454-4248

Volume: 3 Issue: 11 548 – 552

_______________________________________________________________________________________________

cipher output from 64bit design by time sharing using select Here by comparing result obtained from 64bit fixed

input. block size blowfish algorithms implemented using S-box

method and ROM for feistel network, we can conclude that the

ROM based design is optimised to produce less delay and

lesser equivalent gate count. The logic utilization for the both

implementations are almost same.

350000

300000

250000

Figure 7: Black Box of area efficient blowfish Algorithm. 200000

The black box of implemented improved throughput 150000

100000

pipelined blowfish Algorithm is as shown below. Here the 50000

select input makes the 64bit design to operate twice in order 0

produce 128bi output. The clock signal drives the registers Logic Equvalent Delay(ps)

separating the combinational building block of blowfish utilization Gate Count

hardware architecture and triggers with approximate minimum

lapse of 50ns. The select signal trigger once between two S-box Design ROM Design

clock triggers. The clear signal clears all the registers

Figure 9: Comparison between 64bit blowfish algorithms

whenever asserted.

using S-box and ROM

Throughput is defined as the average rate of

successful message delivery over a communication channel.

Throughput is directed toward evaluating each architecture’s

characteristic and performance. Throughput is calculated as

Eq.1.

clock cycles. Latency should be as small as possible to achieve

Figure 8: Black Box of Improved throughput pipelined a power-saving system. Furthermore, a long battery life is

blowfish Algorithm. necessary, particularly for mobile devices.

The cipher result obtained from the plain data applied to the

implemented design for two inputs is as given below, showing Comparisions among 128bit

minimum devotion of 56 of128. implementations

Plaintext:

700000

00000000000000000000000000000000000000000000000000

600000

00000000000000000000000000000000000000000000000000 500000

0000000000000000000000000000 400000

300000

Ciphertext: 200000

00010011110000010111011100110110001001000001011000 100000

00101101010011000100111100000101110111001101100010 0

0100000101100000101101010011 Logic Equivalent Critical Area Delay

Plaintext: utilization Gate Count Delay(ps) Product(ADP)

in um.ps

11111111111111111111111111111111111111111111111111

11111111111111111111111111111111111111111111111111

basic parallel implementation

1111111111111111111111111111

Ciphertext: proposed area efficient implementation

01101111011000001101101001111110001110111011000001 Improved throughput pipelined

00101111111011011011110110000011011010011111100011

1011101100000100101111111011 Figure 10: Comparison among implemented 128bit blowfish

algorithm implementations.

551

IJFRCSCE | November 2017, Available @ http://www.ijfrcsce.org

_______________________________________________________________________________________

International Journal on Future Revolution in Computer Science & Communication Engineering ISSN: 2454-4248

Volume: 3 Issue: 11 548 – 552

_______________________________________________________________________________________________

REFERENCES

Throughput(Normalized) [1] Ravi, Srivaths, et al. "Security in embedded systems: Design

challenges." ACM Transactions on Embedded Computing

140 Systems (TECS) 3.3 (2004): 461-491.

120

[2] Arya, S. "An Implementation of Blowfish Algorithm Using

100

80 FPGA." International Journal of Engineering Research and

60 Technology. Vol. 2. No. 8 (August-2013). IJERT, 2013.

40 [3] Patel C.R., Gohil N.B., Shah V.“FPGA - Hardware Based

20 DES & Blowfish Symmetric Cipher Algorithms For

0 Encryption & Decryption Of Secured Wireless Data

Communication”, Journal of Information, Knowledge and

basic parallel proposed area Improved Research in Electronics and Communication Engineering,

2(2), 739–744. (2013).

implementatio efficient throughput

[4] Dakate, Deepak Kumar, and Pawan Dubey. "Blowfish

implementation pipelined encryption: A comparative analysis using VHDL."

International of Engineering and Advanced Technology

Figure 11: Throughput Comparison among implemented (IJEAT) 1.5 (2012): 177-179.

128bit blowfish algorithms [5] W. Stalling, “Cryptography and Network Security Principles

and Practices”, Prentice Hall, 4th ed., 2005.

From the comparison results shown above, the [6] A. Kahate, “Cryptography and Network Security”, Tata

proposed improved throughput method of implementation McGraw Hill, 2nd ed., 2007.

[7] National Institute of Standards and Technology, Federal

shows off less requirement of LUTs (Look up Tables),

Information Processing Standards Publication 46-3: Data

equivalent gates when compared to parallel implementation

Encryption Standard, 1999.

method. The evaluation delay may be little higher due to [8] S. Hirani, Energy Consumption of Encryption Schemes in

inclusion of selector and de-selector, but overall performance Wireless Devices Thesis, University ofPittsburgh, Apr.

metric ADP is lower for proposed design which is the index 9,2003, Retrieved Oct. 1, 2008.

for improved performance. The proposed design is further [9] A. Nadeem, \A performance comparison of data encryption

modified to get improved throughput pipelined blowfish algorithms," IEEE Information and Communication

architecture, which shows off extremely optimised Technologies, pp. 84-89, 2006.

performance. Results in less logic utilisation, less delay and [10] Results of Comparing Tens of Encryption Algorithms Using

Di®erent Settings- Crypto++ Benchmark,RetrievedOct. 1,

lesser Area Delay Product for superior performance. Still it

2008. (http://www.eskimo.com/ weidai/benchmarks.html)

seems to occupy more equivalent gate count than the proposed

[11] DiaaSalamaAbdElminaam, et,al. “Evaluating The

design due to inclusion of Registers. Performance of SymmetricEncryption Algorithms”

The performance metric throughput is seems to be International Journal of Network Security, Vol.10, No.3,

doubled for proposed implementation, due to parallel PP.213{219, May 2010.

implementation of hardware, whereas for pipelined

architecture throughput is n times, where n is the number of

pipeline stages. Overall performance of the proposed

improved throughput pipelined architecture is better compared

to others.

VI. CONCLUSION

Implemented 64bit fixed block size blowfish algorithm using

VHDL. Simulated for satisfactory result in MODELSIM and

synthesized in XILINX ISE simulator, also implemented

feistel network of blowfish algorithm with ROM and observed

the performance improvement. The implementation of 128bit

blowfish algorithm using proposed improved throughput

method, proposed area efficient method and proposed

improved throughput pipelined method is done and obtained

results shows that the proposed improved throughput pipelined

method poses superior performance. The implementation

results indicate that the proposed pipelined architecture shows

10% of improvement in Throughput.

552

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_______________________________________________________________________________________

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