R.V.

COLLEGE OF ENGINEERING,
BANGALORE 560059

DEPARTMENT OF TELECOMMUNICATION ENGINEERING




LABORATORY MANUAL

V SEMESTER TELECOMMUNICATION

TC DIGITAL COMMUNICATION LABORATORY





DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 2
2

DO'S AND DON'TS IN THE LABORATORY


Come in proper dress code as prescribed by the college

Come well equipped to the lab. (Datasheets, Practical record book, Graph
sheets, calculator etc).

Read the theory of the experiment to be performed well in advance and
understand the working principle clearly before conducting the experiment.

Come prepared for viva - voce.

Follow the given procedure in the same sequence.

USE only 5V power supply for all ÌC.

Handle the equipment with care.

Materials present in the vicinity of the experiment should be absorbing
ones. Remove reflecting objects from the work table.

After the completion of the experiment get the datasheets signed by the
staff-in-charge.

Make sure to return all the components and equipments to the stores after
the completion of the experiment.


Note: Lab manual should be treated as a guideline only.
















DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 3
3
CONTENTS

Cycle of experiments
Equipment specifications
1. Verification of sampling theorem using flat top samples.
2. ASK generation and detection (binary).
3. TDM and recovery of two band limited signals.
4. FSK generation and detection (binary).
5. PCM generation and detection using CODEC chip.
6. BPSK generation and detection (binary).
7. DPSK encoder and decoder.
8. QPSK modulator.
9. Delta modulator and demodulator.
10. Adaptive delta modulator and demodulator.
11. Generation of 3bit pseudo noise binary sequence using JK flip
flops.
12. Realization of direct sequence spread spectrum.
13. Realization of frequency hopping spread spectrum.



Data sheets.

Viva questions.

Sample question bank.














DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 4
4



TC DIGITAL COMMUNICATION LAB

Hours/ week: 3 IA marks: 25
Exam Hours: 3 Exam marks: 50

LAB ORIENTATION

Study of all the components of Microwave bench
Usage of digital oscilloscope / Spectrum Analyzer

CYCLE - I

1. Verification of sampling theorem using flat top samples.
2. ASK generation and detection (binary).
3. PCM generation and detection using CODEC chip.
4. TDM and recovery of two band limited signals.

CYCLE - II

1. FSK generation and detection (binary).
2. PSK generation and detection (binary).
3. DPSK encoder and decoder.
4. QPSK modulator and demodulator.

CYCLE - III

1. Delta modulator and Demodulator.
2. Adaptive delta modulator and demodulator.
3. Generation of Pseudo Random Noise binary sequence using shift register.
4. Generation of WALSH code and BARKER code.
5. Generation of DSSS and FHSS.




Prof. and Head



DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 5
5
Expt. No. 1 SAMPLING THEOREM

AIM: -
(a) To verify sampling theorem using flat top sampling.
(b) To observe the effect of under and over sampling.

APPARATUS REQUIRED:
Op-Amp (µA 741), CD4016 ÌC, resistors, capacitors, signal generators, CRO,
power supply, cables and accessories.

PRINCIPLE
Sampling of a signal is a fundamental operation in digital communication. A
continuous time signal is first converted to discrete time signal by sampling
process. The sufficient numbers of samples have to be taken so that the original
signal can be recovered from sampled values.

Statement:
Let m(t) is a message signal band-limited to W Hz. Ìf this signal is sampled at a
rate of fs < 2W, then we can reconstruct the information from the sampled values
with less distortion.
i.e. fs < 2W where W = max. Message signal frequency.
fs = Sampling frequency.

PROCEDURE: -

a) For flat-top sampling :-

1. Rig up the circuit as shown in fig (a).
2. A sinusoidal signal is given as input message (fm) (5V and 3.4 kHz).
3. A square wave of amplitude 5V, frequency fs is given at the control input
of the analog switch. fs = 2fm ÷ Nyquist sampling
1. fs > 2fm ÷ Over sampling
2. fs < 2fm ÷ Under sampling
4. The sampled output is held at the output terminal using capacitor 'C'.
5. The output is observed on the CRO for different sampling frequencies.

-) For reconstruction of message signal :-

1. Rig up the circuit as shown in fig (b).
2. The flat-top sampled signal from the sample & hold circuit is given as the
input to the filter.
3. The cut-off frequency of the filter is chosen to be slightly greater than the
message frequency ( say 5 kHz for a message frequency of 3.4 kHz).
4. The recovered message signal at the output of the filter is displayed on
the CRO & is compared with the input message signal for different
sampling frequency fs.
5. Plot the outputs obtained on a graph sheet with suitable scale.
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 6
6
OBSERVATIONS: -
Part (a): -
Amplitude of message signal = Volts
Frequency of message signal = Hz
Amplitude of sampling signal = Volts
Frequency of sampling signal = Hz

Part (b): -
Amplitude of recovered signal = Volts
Frequency of recovered signal = Hz

DESIGN: -

1. fs : sampling frequency
fm : message frequency

fs < 2fm

fs = 2fm ÷ Nyquist rate of frequency
fs < 2fm ÷ Under sampling
fs > 2fm ÷ Over sampling

Ex: Ìf the message signal frequency = 3.4 kHz, then for proper
reconstruction Fs > (2×3.4) kHz

2. Design of reconstruction filter

(i) Gain A
0
=1 + (R
F
/R
1
) [Hint: 2
nd
order Butter worth polynomial is
S
2
+1.414S+1]

For 2
nd
order Butterworth filter, A
0
=1.586

.
´
. 1 + (R
F
/R
1
) = 1.586

Let R1

= 10 KD, RF

= 5.86 KD

(ii) Cut-off frequency fc = 1


Let R
2
=R
3
=R
C
2
=C
3
=C
Then fc = 1 / (2ĉRC)

Choose fc = Hz
and C = F

R = 1 / (2ĉfcC) = D

2ĉ\R
2
C
2
R
3
C
3

DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 7
7

R


R

CD 4016:

Ìt is a CMOS quad analog switch

V
DD
= +15V V
SS
= GND
S
1
S
2
S
3
S
4

Ìnput
1 4 8 11
Output 2 3 9 10
Enable
(control)
13 5 6 12

CIRCUIT DIAGRAM: -

















SampIe and hoId circuit :
















Reconstruction FiIter


V
DD

E
0

E
3

Y
3

Z
3

Z
2

Y
2


2
3
4
5
6
7

4
3
2


9
8


C
D
4
0
1
6

PIN diagram
:
6
2


_

3A741
¹15V

-15V
7
4
6
2


_

3A741
¹15V

-15V
7
4 Message
Input
(3.4 kHz)
1
(i/p)

13
14
V
CC

2
(o/p)

7
GND
5V
0

Sampling Signal

C 0.13F

S/H
Output
CD4016
Fig. (a)
6

Output
2


_

3A741
¹15V

-15V
7
4

R
F


S/H
SignaI

R
1



C


C

Fig. (b)
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 8
8
ResuIts:
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 9
9
Expt. No. 2 AMPLITUDE SHIFT KEYING (ASK)

AIM: -To design and study the working of binary ASK system. To demodulate the
above signal with the help of suitable circuit.

APPARATUS REQUIRED:
Op-Amp (µA 741), Transistor, Diode, resistors, capacitors, signal generators,
CRO, power supply, cables and accessories.

PRINCIPLE
Ìn an ASK system , the binary symbol 1 is represented by transmitting a
sinusoidal carrier wave of fixed amplitude and fixed frequency f for a bit
duration T seconds, where as the binary symbol 0 is represented by switching off
the carrier k for T seconds

A cos(2Rf t) symbol 1
S(t) =
0 symbol 0


To generate ASK wave, we have to apply the incoming binary data in unipolar
format to a product modulator. The detection of an ASK wave is done using a
coherent detector with an appropriate threshold level or using an envelope
detector.

PROCEDURE: -

a) odulation:-

1. Rig up the circuit as shown in fig(a).
2. The message signal (square wave of frequency 200Hz) is applied to the
base of the transistor.
3. The carrier signal (sine wave of frequency 1-2kHz) is fed to the collector
circuit of the transistor.
4. The output ASK signal is taken across the emitter resistor R
E
.
5. Observe the waveforms on the CRO and plot it.

b) emodulation:-

1. Rig up the circuit as shown in fig (b).
2. The ASK signal generated is fed at the input of envelope detector which
gives distorted square wave.
3. The output of the envelope detector is compared with V
ref
using a
comparator to get proper square wave.
4. The output of the comparator is the recovered message which is
compared with the input message.

DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 10
10
OBSERVATIONS: -

Amplitude of message signal = Volts
Frequency of message signal = Hz
Amplitude of carrier signal = Volts
Frequency of carrier signal = Hz
Modulated signal amplitude = Volts
Demodulated signal amplitude = Volts
Demodulated signal frequency = Hz

DESIGN: -

a) odulator

Ì
C(sat)
= 2 mA V
CE(sat)
= 0.2V
hfe
(min)
= 30
V
be(sat)
= 0.7V

R
E
= VE

= VC - V
CEsat
= 8 ÷ 0.2 = 3.9kC Choose R
E
= 3.3kC






R
b
= V
m
- V
be(sat)
= 10 ÷ 0.7 = 139.5kC Choose R
b
= 140kC










-) emodulator

Cut-off freq fc = 1 / (2ĉRC)

Let message freq = 200 Hz

Choose fc = 800 Hz (passing upto 4
th
harmonics)
Let C = 0.13F

R = 1 / (2ĉfcC) = 2kD (use pot)

V
ref
= A
c
T
b
/ 4
A
c
= 8V T
b
= 1/(2x2x10
-3
)
V
ref
= Volts



Ì
C
2x10
-3
Ì
E

[2x10
-
3
/30]

CE(sat)
/hfe
(min)
]
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 11
11
CIRCUIT DIAGRAM: -



i) odulator













ii) emodulator























R
E

$100

Carrier
c(t)

6V

A$
outpu
t

R
b

m(t)

message
V)

Fig. (a)
OA79

C

R
ASK i/p
demoduIated
message SignaI
6
2


_

¹15V
74

-15V
7
4
m(t)
V
reI


Fig. (b)
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 12
12







DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 13
13
Expt. No. 3 TIME DIVISION MULTIPLEXING (TDM)

AIM: - To study the working of time division multiplexing circuit for Pulse
Amplitude Modulated (PAM) signals.

APPARATUS REQUIRED:


PRINCIPLE
Ìn Pulse Amplitude Modulated (PAM) systems, the sampled carrier pulses
occupy only a portion of the time interval between samples. Thus, with TDM
technique the time interval between samples is used by other independent
massage sources on a time-sharing basis.
The multiplexer unit multiplexes the different message signals, converts the
different message signals into a set of pulses on a time division basis. At the
receiving end a de-multiplexer is used to separate the sampled pulses of different
messages and low pass filters do the reconstruction of the different messages.
CD4051 an ÌC can be used as multiplexer or de-multiplexer and up to eight
signals can be multiplexed.

PROCEDURE: -

c) %:-

1. Set up the circuit as shown in Fig a. CD4051 is used for multiplexing two
signals.
2. One signal is applied at Ì
0
and the other signal at Ì
1
input of the multiplexer
ÌC (pins 13 and 14).
3. V
CC
is connected to +5V. V
EE
is grounded or connected to ÷5V. V
SS
is
grounded. The inhibit input (ÌNH ÷ pin 6) is also grounded.
4. The output is taken at pin 3. Selection lines B & C (pins 9 & 10) are
grounded. The control signal is applied to A (pin 11) with a frequency
greater than twice the maximum frequency of the input signals.
5. Design the demodulation (reconstruction) circuits and rig ÷ up as shown
above.
6. Observe the reconstructed output and compare with input signals.
Note:- To generate PAM waves follow the procedure given below.

d) !:-
PrincipIe:- Pulse amplitude modulation, the simplest form of pulse modulation, is
illustrated in the figure. PAM is a pulse modulation system in which the signal is
sampled at regular intervals, and each sample is made proportional to the
amplitude of the signal at the instant of sampling. The pulses are then sent by
either wire or cable, or else used to modulate a carrier. There are two types of
PAM, double-polarity PAM and single-polarity PAM. Ìn single-polarity PAM a
fixed DC level is added to the signal, to ensure that the pulses are always
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 14
14
positive. PAM is used infrequently because it does not utilize constant amplitude
pulses, and when it is used, the pulses frequency-modulate the carrier.
odulation:
1. To generate PAM signal, rip up the circuit as shown in fig(c).
2. Apply sinusoidal message signal at the base of the transistor(say
frequency 1kHz).
3. Square wave sample pulses are applied at the collector of the transistor
(frequency is higher than message signal frequency say 10kHz)
4. PAM output is observed across emitter resistor R
E
.

emodulation:
1. Apply PAM signal to envelope detector as shown in fig(d).
2. Design RC filter to pass only message signal.
3. The filter will eliminate the higher frequency components and demodulated
message is obtained at the output.
4. Compare demodulated message with actual message.
5. Observe the waveforms on CRO and plot it.

BIock Diagram: -










Pin Diagram of CD4051: -










Function TabIe of CD4051: -

INPUT GATES ON
CHANNEL INHIBIT C B A
0 0 0 0 I
0

0 0 0 1 I
1

0 0 1 0 I
2


MUX

DEMUX
LPF
LPF
X
1
(t)
X
2
(t)
X
1R
(t)
X
2R
(t)
TDM
Control
Signal
V
DD
Ì
2

Ì
1
Ìnputs
Ì
0
Ì
3

A
B Selection Lines
C


Ì
4
Ì/O Ì
6
OUTPUT
Ì
7
Ì/O Ì
5

ÌNHÌBÌT
V
EE
V
SS

1 16
2 C 15
3 D 14
4 4 13
5 0 12
6 5 11
7 1 10
8 9
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 15
15
0 0 1 1 I
3

0 1 0 0 I
4

0 1 0 1 I
5

0 1 1 0 I
6

0 1 1 1 I
7

1 X X X NONE

CIRCUIT DIAGRAM: -




Low Pass FiIter (LPF): -








ResuIts:


TDM Signal
GND
A B C A B C
V
CC

Control Signal
13 6 7
14 16

C
D 3
4
0
5
1 8


11 10 9
6 7 13
16 14

C
D
3 4
0
5
8 1


11 10 9
V
CC

GND
V
EE
V
EE
ÌNH ÌNH
LPF
LPF
X
1R
(t)
X
1
(t) Ì
o

X
2
(t) Ì
1

X
2R
(t)
#
1
6 2

R
C 0.1µF Ì/P O/P
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 16
16
Expt. No. 4 FREQUENCY SHIFT KEYING (FSK)

AIM: -To design and demonstrate the working of FSK and demodulate the
signal with the help of a suitable circuit.

APPARATUS REQUIRED:
NE/SE 565 PLL ÌC, 555 ÌC, Op-Amp (µA 741), Transistor, resistors, capacitors,
signal generators, CRO, power supply, cables and accessories.

PRINCIPLE
Ìn an FSK system, two sinusoidal waves of the same amplitude , but different
frequencies f1 and f2 are used to represent the binary symbols1and 0.

cos2R f
1
t) symbol 1
S(t) =
cos(2R f
2
t ) symbol 0


To generate FSK wave, we may apply the incoming binary data
represented in the polar format to a frequency modulator. As the modulator input
changes from one voltage level to another, the transmitted frequency changes in
a corresponding fashion.

PROCEDURE: -

a. odulation:-
) Rig up the circuit as shown in the Iigure.
2) Switch on the supply and apply a LOW to the transistor so that it is OFF.
3) Vary the pot R
A
to get an output Irequency I

.
4) Apply a HIGH to the transistor so that it is ON.
5) Vary the pot R
C
to get an output Irequency I

.
6) Apply a square wave oI given Irequency and observe the FSK o/p.

-) emodulation:-
) Rig up the circuit as shown in the Iigure.
2) Apply the FSK signal to the i/p and observe the demodulated o/p.

DESIGN: -
a. odulator:-
I

÷ 27 Hz
I
2
÷ 7 Hz
Choose R
B
÷ 47k
C ÷ .F

For astable mode I

÷ .44 / R
A
¹R
B
)C
R
A
÷ 4k
Use 47k pot ¹ k resistance
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 17
17
For monostable mode I

÷ .44 / ¦R
A
|R
C
)¹2R
B
}C
Let R
B
÷ 4k
C ÷ .F
R
A
|R
C
÷ 2k
Choose R
A
÷ R
C
÷ 4k

Use 47k pot + 10k resistance for both R
A
and R
C


-. emodulator:-
I ÷ 27Hz I2 ÷ 7Hz
Iout ÷ I¹I2)/2 ÷ 7Hz
Iout ÷ .2 /4R

C

Let C

÷ .F
R

÷ 25k
V ÷ 5--5) ÷ Volts
I
LOCK
÷ 8Iout/V ÷ 936Hz
I
H
÷ /2ĉR`C` R`÷k C`÷.2F

CIRCUIT DIAGRAM: -
MODUATOR:

DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 18
18

R1 10k

ii) emodulator

































Results:
6
2


_

¹15V

-15V
7
74
4
10 7
4



1
2
3
4
5
6
7

14 NC
13 NC
12 NC
11 NC
10 V
+

9 Ext Cap for VCO
8 Ext R for VCO


V
-

i/p
i/p
VCO o/p
Phase comparator VCO i/p
Ref o/p
Demod o/p

N
E
5
6
5


C2


0.02µF

0.02µF

0.02µF

0.15µF

0.01µF

10k

10k

10k

680C

680C

27k

0.1µF

0.047µF


C1

R2


R3


-5V
FSK
i/p
5
6
8
1 9 3
2
NE/SE 565 PLL

o/p
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 19
19
Expt. No. 5 PHASE SHIFT KEYING (PSK)

AIM: -
a) To design and demonstrate the working of BPSK modulated signal.
b) To demodulate the BPSK signal to recover digital data.

APPARATUS REQUIRED:
Op-Amp (µA 741), Transistor, Diode, resistors, capacitors, signal generators,
CRO, power supply, cables and accessories (Balanced Modulator).

PRINCIPLE
Ìn a PSK system, a sinusoidal carrier wave of fixed amplitude and fixed
frequency f is used to represent both symbols 0 and 1, except that the carrier
phase for each symbol differs by 180 degrees. The PSK may be represented as
follows.


cos2R f t) symbol 1
S(t) =
cos(2R f t + R) symbol 0

To generate PSK wave we can apply the signal in polar format to a product
modulator. The detection of the PSK wave can be done using a coherent
detector by choosing an appropriate threshold level.


PROCEDURE: -

a) odulation:-
) Rig up the circuit as shown in fig(b).
2) Apply the message signal m(t), a square wave of frequency 500 Hz, at the
base of each transistor.
3) A carrier signal (sine wave) of frequency 2kHz is applied as shown in the
figure.
4) During the positive half cycle of the message m(t), the transistor T1 will
conduct and the output of the op-amp is in phase with the carrier, as the
input is given to the non-inverting terminal.
5) During the negative half cycle of the message m(t), the transistor T2 will
conduct and the output of the op-amp is 180
o
out of phase with the carrier,
as the input is given to the inverting terminal.
6) The output of the op-amp is the BPSK signal.
7) Adjust the 10k pot to get equal gain for both the cycles.
8) Observe the waveform on the CRO.




DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 20
20

R

-) emodulation:-
) Rig up the circuit as shown in fig(d).
2) Apply BPSK signal and reference carrier at the input of the adder as
shown in fig(d).
3) The output of the adder gives the ASK signal.
4) The ASK signal is applied to the envelope detector to get the demodulated
output.
5) The waveform may be distorted. To get a smooth output, apply the
demodulated signal to a comparator with proper V
ref
.
6) The output of the comparator gives a perfect square wave message.


DESIGN: -

odulator:-

RC >> T
Choose RC = 10T
Let f = 500Hz T=1/f
Choose C = 1µF
Find R

CIRCUIT DIAGRAM: -

i) Using IC1496 alanced odulator)






















6
2


_

¹15V

3 ¹

- 15V
7
4

BM-Ì
1496
Fig. (a)

Message
SignaI
i/p

BM-ÌÌ
1496

C


0.01µF

BPSK

BPSK
741
Demod
Message
o/p
Carrier
signaI

Modulator

Buffer

Demodulator
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 21
21
i) odulator
ii) Circuit iagram


















AIternate circuit for BPSK ModuIation :


























Fig. (b) BPSK
ModuIator
6
2
3 +
_

3A741
+15V

-15V
7
4

10k


k
pot


10k


10k

1k

c(t)
carrier
signal


m(t) digital
data


!$
signal



SK100


SL100

T1



T2

Message
m(t)
BPSK
output
OA79
Carrier
SignaI c(t)

Fig. (c)
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 22
22


DemoduIator :

















Output WAVEFORMS:






















Results:



OA79

C

R
O
O/p
6
2

3 +
_

¹15V

-15V
7
4
V
reI

Fig. (d)
6
2

3 +
_

+15V

-15V
7
4
ADDER
1k

k
ENVELOPE
DETECTOR
COMPARATOR
BPSK
signa
I
Reference
Carrier

k
1 0 1 1 0

Binary Data

Polar
Representation

Carrier c(t)
BPSK
signal
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 23
23
Expt. No. 6 DIFFERENTIAL PHASE SHIFT KEYING (DPSK)

AIM: - To demonstrate the working of DPSK encoder and decoder with the help
of a suitable circuit.

APPARATUS REQUIRED:

DPSK Encoder and Decoder kits, Signal Generator, CRO and accessories.

PRINCIPLE

As for PSK, it cannot be detected non-coherently because the envelope of a PSK
wave is the same for both the symbols 1 and 0 and a single carrier frequency is
used for the modulation process. To eliminate the need for phase
synchronization of the receiver with PSK, we may incorporate differential
encoding. Ìn differential encoding, we encode the digital information content of a
binary data in terms of transitions. A signaling technique that combines
differential encoding with phase shift keying is known as differential phase shift
keying (DPSK). The DPSK wave can be detected by multiplying the signal with a
delayed version of itself and then applying it to an integrator followed by a
decision device with an appropriate value of threshold. Thus the need for phase
and timing synchronization is eliminated.

PROCEDURE: -

a) %ransmitter:-

1. Connect the power cord to the power supply as
Red : +5V
Black : GND
Green : +12V
Blue : -12V
2. Select the input bit stream by the combination of DÌP switches.
3. From this switch, 8-bit data is available.
4. Select proper transmission rate, either 300bps or 600bps, by connecting
jumpers.
5. By connecting jumper select NRZ(L) data at the output of the data
generator.
6. By using EX-OR gate and 1 bit delay ckt, we can generate encoded bit
stream.
c
k
= b
k
c
k-1

7. The DPSK data changes the phase of the carrier whenever the selected
data bit is '0' and remains in the same phase when the data bit is '1' (For
bit '1' it will select sine function whereas for bit '0' it will select inverted sine
function).
8. The DPSK waveform is displayed on the CRO.
9. The experiment is repeated for different data patterns.
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 24
24

-) Receiver:-

. The interIace card is connected between transmitter and receiver.
2. DPSK modulated signal is given to the adder ckt with or without noise.
3. This signal is passed through BPF to minimize noise eIIect.
4. The output oI the BPF is applied at the input oI the multiplier with reIerence
carrier.
5. The output oI the multiplier is passed through a Iilter to eliminate high Irequency
components.
6. The Iilter output is connected to the comparator with proper V
reI
to get perIect
digital data.
7. This data is decoded using EX-OR and -bit delay ckt.
8. The decoded data at EX-OR is latched at the output and observed on the CRO.


OBSERVATIONS: -

a) ModuIator


Input bit stream ¦b
k
}
Encoded bit stream ¦c
k
}
DPSK phase H H H H H

b) DemoduIator


Modulated DPSK
signal phase
R
X
signal)
H H H H H
Comparator output
bit stream

Decoded output
bit stream












DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 25
25
BLOCK DIAGRAM: -

DPSK Transmitter :





















D!$ Receiver :


















DÌVÌDE
BY 8

DATA
GENERATOR
NRZ(L)


Select

Ext
Data
Parallel 8-bit
Data
From DÌP

MUX
2:1

ÌNVERTER

1 BÌT
DELAY
DPSK MODULATED
OUTPUT


SÌNE WAVE
GENERATOR
(10kHz)
600bps
300bps
NRZ(L)

Selection
Logic

300bps
600bps

CLOCK
GENERATÌ
ON

CLOCK
DÌVÌDER
Encoded
Data

EX-OR

MULTÌPLÌER

LPF

Reference Sine
1 BÌT
DELAY

EX-OR

LPF

ADDE
R

Noise Ìn

DPSK signal
(from T
X
)

LEVEL
CONVERTER


LATCH


Decoded
Data


V
ref

DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 26
26
Expt. No. 7 PCM using CODEC chip

AIM: - To study the generation of PCM wave and reconstruction of anaIog
signaI from PCM using CODEC chip.

!rinciple:

PCM produces a series oI numbers or digits usually in binary code representing the
approximately amplitude in oI the signal sample at that instant. In PCM, the total
amplitude range, which the signal may occupy is divided into the number oI standard
levels are represented by the binary code, the actual number oI levels is the power 2. the
essential operation oI a PCM transmitter are sampling, quantization and encoding.
Quantization reIers to the use oI Iinite set oI amplitude levels and selection oI a levels
nearest to a particulars sample value oI the message signals as represented Ior it. The
quantization and coding process are perIormed in the same circuit known as A-D
converter . the essentials oI the receivers are regeneration, decoding and demodulation oI
the train pulses, which are perIormed in the same circuit called as D-A converter.the
quantization process introduces some distortion known as quantization noise.
Advantage oI PCM:
. PCM has much better noise immunity.
2. PCM doesnot suIIer Irom gradual deterioration and degradation as in the case oI
analog signals.

Disadvantages:
. PCM requires very complex encoding and quantizing circuitary.
2. PCM requires a large bandwidth compared to analog systems.

Application:

24 channel telephony t systems), space communication, broadband network etc.

a) Clock divider circuit:



Fig-



DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 27
27

CODEC chip circuit diagram:


!rocedure:

. Rigup the clock circuit to generate 8 kHz synchronous clock and test the
o/p.
2. Rigup the CODEC circuit as shown in the Iigure.
3. Apply the clock 2 kHz) and synchronous 8 kHz) signals.
4. Apply the input analog signals) oI Irequency less than 3.4 kHz with in the
voice band).
5. Observe the PCM o/p at pin 5 and note down the o/p.
6. Measure the Irame duration 25microsec).
7. Connect the PCM O/P to the PCM I/P and observe the reconstructed
signals.
8. Compare the analog I/P and reconstructed input.

Observation:

DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 28
28
Expt. No. 8 QUADRATURE PHASE SHIFT KEYING (QPSK)

AIM: - To generate QPSK signal by using suitable circuit and also to demodulate
QPSK signal.

APPARATUS REQUIRED:

QPSK Encoder and Decoder kits, Signal Generator, CRO and accessories.

PRINCIPLE

Ìn binary data transmission, we send only one of two possible signals during
each bit of interval T
b
. On the other hand, in an M-ary data transmission system
we send any one of the M possible signals, during each signaling interval T. For
almost all applications, the number of possible signals M=2 to the power of n. Ìt is
apparent that a binary data transmission system is a special case of M-ary data
transmission system. Each of the M signals is called a symbol. The rate at which
these symbols are transmitted through the communication channel is expressed
in units of bauds. A baud stands for one symbol per second; for M-ary data
transmission, it equals log
2
M bits per second.

Ìn this section we consider quadriphase-shift keying(QPSK), which is an example
of M-ary data transmission with M=4. Ìn QPSK, one of the four possible signals is
transmitted during each signaling interval, with each signal uniquely related to a
dibit (pairs of bits are termed dibits).


PROCEDURE: -

a) %ransmitter:-

. Select proper clock speed either 3bps or 6bps.
2. Connect the power cord to the power supply as
Red : ¹5V
Black : GND
Green : ¹2V
Blue : -2V
3. Select the input bit stream by the combination oI DIP switches.
4. Connect NRZL) line to the data select line.
5. Check the working oI individual MUX, each MUX has to work as a PSK
modulator.
6. Output oI each MUX is combined using the adder circuit. The output oI the adder
ckt gives QPSK signal which is observed on the CRO.


-) Receiver:-
. The interIace card is connected between the transmitter and receiver.
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 29
29
2. The reIerence sine & cosine carrier signals are applied to the two multipliers
along with the received QPSK signal.
3. The
st
multiplier acts as in-phase detector and the 2
nd
multiplier acts as
quadrature detector.
4. The odd and even sequences are demodulated separately.
5. The output at the level converter is obtained by adiusting the pot connected to the
reIerence voltage.
6. The recovered bit stream is observed on the CRO and compared with the inout bit
stream.
OBSERVATIONS: -
Input bit stream bt)
Odd bit stream b
o
t)

-)

-)

¹)

¹)
Even bit stream b
e
t)

-)

¹)

-)

¹)
Phase oI modulated
output
H/4 3H/4 -3H/4 -H/4
BLOCK DIAGRAM: -
QPSK Transmitter :

























WORD
PULSE
GENERATOR

DATA
GENERATOR
BÌT
SPLÌTTER
NRZ(L)

Select
Data

Ext Data

DÌP SWÌTCH
DATA PATTERN
Parallel
8-bit Data

MUX
2:1

ÌNVERTER

MUX
2:1

ÌNVERTER

Ext Data
Odd Bit Stream

Ext Data
Even Bit Stream sin

÷÷
sin
cos

÷÷
cos

ADDER

QPSK

O/P

CARRÌER
GENERATOR


(10kHz)

90
O
PHASE
SHÌFTER
600bps
300bps
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 30
30

Q!$ Receiver :




















Observation:




















ResuIts:




MULTÌPLÌER

LEVEL
CONVERTER

LPF

Ref
Sine
V
reI


MULTÌPLÌER

LEVEL
CONVERTER

LPF

Ref
Cos
V
reI


BPF

QPSK
input

BÌT
COMB-
ÌNER

LATCH

O/P

(Parallel
To Serial)
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 31
31
Expt No: 9
Aim: To reaIize deIta moduIation and demoduIation using
suitabIe circuit.
Components and equipments required:
SI.No Components. VaIue and quantity.
1. OperationaI AmpIifier UA741 (3).
2. Transistors. Q2N3904 (1).
3. Resisters 1k(3), 50k(1), 10k(3),
39k(1),100k(1).
4. Capacitors. 0.22u(1), 0.2n(1).
5. Power suppIy. 0-30V.
6. SignaI generators 0-2MHz(2).

Theory: Delta modulation DM or A-modulation) is an analog-to-digital and digital-
to-analog signal conversion technique used Ior transmission oI voice inIormation where
quality is not oI primary importance. DM is the simplest Iorm oI diIIerential pulse-code
modulation DPCM) where the diIIerence between successive samples is encoded into n-
bit data streams. In delta modulation, the transmitted data is reduced to a -bit data
stream.
!rinciple of operation:
O The analog signal is approximated with a series oI segments
O Each segment oI the approximated signal is compared to the original analog wave
to determine the increase or decrease in relative amplitude
O The decision process Ior establishing the state oI successive bits is determined by
this comparison
O Only the change oI inIormation is sent, that is, only an increase or decrease oI the
signal amplitude Irom the previous sample is sent whereas a no-change condition
causes the modulated signal to remain at the same or state oI the previous
sample.
O Rather than quantizing the absolute value oI the input analog waveIorm, delta
modulation quantizes the diIIerence between the current and the previous step, as
shown in the block diagram in Fig. .


DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 32
32
Fig. - Block diagram oI a A-modulator/demodulator
O The modulator is made by a quantizer which converts the diIIerence between the
input signal and the average oI the previous steps. In its simplest Iorm, the
quantizer can be realized with a comparator reIerenced to two levels quantizer),
whose output is or iI the input signal is positive or negative. The demodulator
is simply an integrator like the one in the Ieedback loop) whose output rises or
Ialls with each or received. T
Circuit diagram:
V5
TD =
TF = 100n
PW = 20u
PER = 0.1m
V1 = 0
TR = 100n
V2 = 5
U1
uA741
+
3
-
2
V
+
7
V
-
4
OUT
6
OS1
1
OS2
5
U2
uA741
+
3
-
2
V
+
7
V
-
4
OUT
6
OS1
1
OS2
5
U3
uA741
+
3
-
2
V
+
7
V
-
4
OUT
6
OS1
1
OS2
5
R1
50k
R2
1k
R3
1k
R4
7k
R5
39k
R6
100k
C1
0.22u
0
V2
FREQ = 500
VAMPL = 100m
VOFF = 0
Q1
Q2N3904
U4
uA741
+
3
-
2
V
+
7
V
-
4
OUT
6
OS1
1
OS2
5
neg
VCC
V3
15Vdc
V4
15Vdc
r
0
R7
10k
R8
10k
VCC
C2
.2n
neg
neg
VCC
neg
r
VCC
tout
r
neg
VCC
0
tout
&%
4000Hz
1000hz 1dB
50dB
0
V

Procedure:
Part -A: DeIta moduIation:
. Rigup the circuit as shown in the Iigure above.
2. Apply the voltage oI the pulse to 5V and Irequency to kHzIrom the signal generators
to summer circuit.
3. Apply voltage oI the message signal to 5v and Irequency to 5Hz Irom signals
generators to summer circuit as shown in Iigure above.
4. Apply the above resulting signal to quantizer and step delay circuit.
6. Observe the output waveIorm as shown below.
7. Note down the duration oI the delta signal and plot the graphs.
!art-: Delta demodulation:
. Rig up the circuit Ior recovery oI the message signal Irom modulation.
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 33
33
2. Apply the modulated output to the input oI the integrator Iallowed by low pass Iilter.
3. Observe the waveIorm Ior message signal Irom the demodulation circuit.

Expected waveforms:


ResuIts:



























DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 34
34
Expt 10: eneration of pseudo noise binary sequence using 1-
flip flop.

Components required:
Sl.No Components. Value and quantity.
1. J-K flip flop. (3)
2. 2 input XOR gate (1)

Theory: Generation oI PN sequence:



Fig : Maximum-length sequence generator Ior n÷3
A Ieedback shiIt register is said to be Linear when the Ieed back logic consists oI entirely
mod-2-address Ex-or gates). In such a case, the zero state is not permitted. The period
oI a PN sequence produced by a linear Ieedback shiIt register with n` Ilip Ilops cannot
exceed 2n-. When the period is exactly 2n-, the PN sequence is called a maximum
length sequence` or m-sequence`.

!rinciple of operation: Consider the linear Ieed back shiIt register as shown in Iig .
involve three Ilip-Ilops. The input so is equal to the mod-2 sum oI S and S3. II the initial
state oI the shiIt register is . Then the succession oI states will be as Iollows.

,,,,,,, . . . . . .

The output sequence output S3) is thereIore. . . . . .

Which repeats itselI with period 23 ÷ 7 n÷3)

Maximal length codes are commonly used PN codes
In binary shiIt register, the maximum length sequence is N ÷ 2m-1 chips, where m is the
number oI stages oI Ilip-Ilops in the shiIt register.

Observation:
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 35
35



































DATA SHEET:

a) CD4016:
1 0 0
1 1 0
0 1 1
0 1 1
1 0 1
0 1 0
0 0 1
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 36
36


b). HD44233P:
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 37
37


DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 38
38

DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 39
39

DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 40
40


c) UA741 OPAMP:

DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 41
41


DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 42
42
d) CD4051B:

DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 43
43

DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 44
44


DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 45
45

e)


VIVA QUESTIONS

A. DigitaI Communication
1. State and explain sampling theorem.
2. What is Nyquist rate of sampling?
3. What is aliasing? How is it minimized practically?
4. What should be the minimum sampling rate for a voice signal in the range
300 ÷ 3400 Hz?
5. Explain FDM & TDM
6. What are the advantages of digital communication?
7. What are the disadvantages of digital communication?
8. How can an analog voice signal be digitized?
9. What is quantization? How is this error minimized?
10. Explain sampling theorem for a band pass signal?
11. A message signal is band limited to a frequency range of 10 ÷ 12 kHz, find
the minimum sampling frequency?
12. How messages signal is reconstructed from the sampled values?
13. How is bandwidth measure in the case of AM, DSBSC, SSB and Digital
Modulation?
14. For a given sinusoidal input signal write PAM, PWM and PPM signals.
15. What are the advantages of PPM signals?
16. Explain different types of digital modulation techniques.
17. For the binary data 101101 draw ASK, FSK and PSK modulated
waveforms.
18. Comment on the bandwidth requirement of the various digital modulation
techniques.
19. Explain the need for CODECS.
20. What is PCM draw the block diagram of a typical PCM system?
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 46
46
21. For an 8 ÷ bit PCM system if the voice signal is sampled at the rate of 8k
samples /sec, find the rate of transmission and bandwidth requirement.
22. What is delta modulation (DM)?
23. Explain the different types of errors in DM,
24. Compare the different types of DM techniques.
25. What are the advantages of optical communication?
26. Explain few optical sources and detectors.
27. How is the maximum bit rate supported measured in a digital link?
28. Represent the following binary data in 1.Polar, 2. Bipolar, 3. Unipolar, 4.
Manchester coded and 5. Differential coded forms.
29. Explain the need for M- ary modulation.
30. What is QPSK modulation?
31. What is signal space representation?
32. Write the signal space representation for the following signals a) ASK, b)
FSK and c) PSK.
33. Differentiate between matched filter and correlative filter.
34. What is bit error rate and probability of error in digital modulation?
35. Compare PER of ASK, FSK & PSK modulation techniques.
36. Explain non-coherent ASK & FSK demodulation.
37. What is QAM?
38. Explain a DPSK modulator and demodulator.
39. Differentiate between coherent & non-coherent demodulation techniques.
40. Ìn a PCM system the minimum SNR required is 40dB, how many bits of
quantization is required.

DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 47
47
TC DIGITAL COMMUNICATION LAB

SAMPLE QUESTION BANK

b. DigitaI Communication
1. For a _____ Hz message signal, design and demonstrate the working of a
flat top sampling circuit. Demonstrate the effect of a) Under sampling, b)
over sampling & c) right sampling, on the demodulated signal with the help
of suitable reconstruction filter.
2. Design and demonstrate the working of TDM for PAM signals with ______
& ____ Hz message signals. With the help of suitable circuits demultiplex
the above message signals.
3. Design and demonstrate an ASK system to transmit ____bps digital date
using a suitable carrier. Demodulate the above signal with the help of a
suitable circuit and determine the minimum carrier frequency for proper
detection.
4. Design and demonstrate the working of FSK system with a suitable circuit
for ___ & ____ Hz carri9er signals. Determine the frequency deviation and
modulation index. Demodulate the above signal with the help of a suitable
circuit.
5. Design and demonstrate the working a BPSK modulation for a carrier
signal of ___Hz to transmit a digital data of ____Hz. Demodulate the
BPSK signal to recover the digital data.
6. With the help of a suitable circuit demonstrate the working of a DPSK
encoder and decoder for a given input stream and carrier frequency.
7. Rig up a DPSK system to avoid error propagation. For a suitable binary
input demonstrate the output with and without error propagation.
8. With the help of suitable circuit modules demonstrate the working of a
QPSK modulator and demodulator.
9. Measure the maximum bit rate a digital link can support by setting up a
digital fiber optic link.
DEPARTMENT OF TELECOMMUNÌCATÌON, R V C E 48
48
10. Conduct a suitable experiment using a fiber optic trainer kit to determine
a) Launching angle, b) attenuation loss c) bending loss, of the given
optical fiber


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