# EE/COSC 2390 Homework Set 5 Solutions 4-1(a,b) For the combinational circuit given. . .

Spring 2004

(a) Derive the Boolean expressions for T1 through T4 . Evaluate the outputs F1 and F2 as a function of the four inputs. T1 T2 T3 T4 F1 F2 BC AB A + T1 = A + B C D ⊕ T2 = D ⊕ A B = A BD + D(A + B ) = A BD + AD + B D T3 + T4 = A + B C + A BD + AD + B D = A + BD + B D + B C D + T2 = D + A B

= = = = = =

Note: to get to the ﬁnal form of F1 shown above, I applied a K-map. (b) List the truth table with 16 binary combinations of the four input variables. Then list the binary values for T1 through T4 and outputs F1 through F2 in the table. A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 T1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 T2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 T3 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 T4 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 F1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 F2 0 1 0 1 1 1 1 1 0 1 0 1 0 1 0 1

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The output is 0 otherwise. 1. To speak in Boolean function terms.EE/COSC 2390 Homework Set 5 Solutions Spring 2004 4-2 Obtain the simpliﬁed Boolean expressions for output F and G in terms of the input variables in the circuit given. in SOP canonical form. A and B and C. A INV AND2 B INV OR2 H C INV AND2 4-28 Design a circuit using a 3-to-8 decoder and external gates to provide the following Boolean functions: F1 = x y z + xz F2 = xy z + x y F3 = x y z + xy 2 . A schematic for this circuit is shown below. B. 2) . You can use a K-map to ﬁnd that this reduces to H(A. B. So. we have the following: F = = = = = and G = = = = (A + BC)((A D) ) (A + BC)(A + D ) A A + A D + ABC + BCD A D + ABC (A (A D) ) (A + BC) (A + A D)(A + BC) AA + ABC + A A D + A BCD ABC + A D + A BCD ABC + A D where the last simpliﬁcation step in both F and G might be aided via a K-map. C) = A B + A C = A (B + C ) . 4-4 Design a combinational circuit with three inputs and one output. I will call the desired function H and the inputs. we want to design a circuit such that H(A. From the circuit diagram in the text. from most signiﬁcant bit to least signiﬁcant bit. C) = (0. The output is 1 when the binary value of the inputs is less than 3.

For our given functions. F1 (x. z) as a basis for the minterm numbering. D3_8E z y x A0 A1 A2 D0 D1 D2 OR3 D3 D4 D5 VCC D6 E D7 OR3 F1 F2 F3 OR3 The particular decoder I used in the schematic happens to be in the Xilinx symbol set for the xc95108. 4) (1. Because this one has an enable. 5. 7) So. we have. z) = x y z + xz = F2 (x. . z) = xy z + x y = F3 (x. I had to tie it to an “always enabled” condition. 3 . we want to know the canonical SOP (list of minterms). 3. we’re just left to “hook up the external gates” after correctly attaching the inputs to the select lines of the decoder.EE/COSC 2390 Homework Set 5 Solutions Spring 2004 First note that for a decoder design. 7) (2. y. 6. y. using the order F1 (x. Your mileage may vary depending upon the mux you use. A schematic is shown below. . y. y. z) = x y z + xy = (0.

then the ﬁnal 2 × 1 mux selects the appropriate byte. In order to describe the design scheme. The scheme is to use the two 8 × 1 muxes to select data from within the upper and lower “bytes” of D(15:0).EE/COSC 2390 Homework Set 5 Solutions Spring 2004 4-31 Construct a 16 × 1 multiplexer with two 8 × 1 and one 2 × 1 multiplexers. with the most signiﬁcant bit Sel(3) controlling the ﬁnal mux. Use block diagrams. Note in particular the wiring of the select lines. I’ll assume that we have 16 data inputs in the bus D(15:0) and four select lines Sel(3:0). The schematic shown below summarizes this connection. D(15:0) D(0) Sel(3:0) D(1) D(2) D(3) D(4) D(5) D(6) D(7) Sel(0) Sel(1) Sel(2) VCC M8_1E D0 D1 D2 D3 O D4 D5 D6 D7 S0 S1 S2 E M2_1 D0 O D1 S0 M Sel(3) D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15) Sel(0) Sel(1) Sel(2) VCC M8_1E D0 D1 D2 D3 O D4 D5 D6 D7 S0 S1 S2 E 4 .

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