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Digital Logic Families

Introduction

A logic family is a group of compatible devices

with the same logic levels and supply voltage.

Classification:

According to components used in the logic family,

digital logic families are classified as,

1. Bipolar

a. Saturated

i. RTL: Resistor Transistor logic

ii. DTL: Diode Transistor logic

iii. DCTL: Direct coupled logic

iv. I 2 L: Integrated Injection logic

v. HTL: High threshold logic

vi. TTL: Transistor -Transistor logic

b. Unsaturated

i. Schottkey TTL

ii. ECL: Emitter Coupled Logic

2. Unipolar

1. PMOS( P-channel MOSFET)

2. NMOS(P-channel MOSFET MOSFET)

3. CMOS(Complementary MOSFET)

Saturated and Unsaturated Logic Circuits

The logic circuits in which transistors are driven

into saturation are called saturated logic circuits or


simply saturated logic. TTL is the example of a

saturated logic.

The disadvantages of saturated logic is the delay

that occurs when the transistors is brought out of saturation.

When a transistor is saturated, its base is flooded with

carriers. Even when base voltage is switched off, the

base remains flooded for some time till all carriers

leave.

The time required by the carriers to leave the

base is called saturated delay time (ts). Saturated logic

circuits have low switching speeds

Those circuits, which avoid saturation of their

transistors, are called non -saturated logic. ECL is the

example of a non-saturated logic. Non saturated logic

circuits have faster switching speeds.

Characteristics of Logic Families

1. Power and Ground

2. Logic Level Voltage Ranges

3. Current and voltage parameters

4. Noise immunity and Noise margin

5. Power dissipation

6. Propagation delay

7. Speed power Product

8. Fan-in and Fan-out

9. Current sourcing and Sinking


Power and Ground

The most important connection required to operate

an IC is power and ground. Both TTL and CMOS logic ICs

have the appropriate pins.

V cc represents the power supply pin for TTL logic

and V DD for CMOS. If CMOS is compatible with TTL then

power supply pin can be labeled as V cc .

The standard value of the DC supply voltage for

TTL is +5V and V DD for CMOS device can range from +3V

to + 1 8 V.

But +5V is most often used. For simplicity, the dc

supply voltage is usually omitted from the logic circuits.

It is connected to the V CC or V DD pin of an IC package

and the ground is connected to the GND pin of an IC

package.

Logic Level Voltage Ranges

For the standard TTL, the input voltage range for

Logic 0 (LOW) is 0 to 0.8V and for Logic 1 (HIGH) is 2 to

5V. The voltage that is not in either range are said to

be indeterminate and should not be used as inputs to

any TTL devices.

For the standard CMOS, the input voltage range for

Logic 0(LOW) is 0 to 1.5V and for Logic 1 (HIGH) is 3.5 to

5V. The voltage that is not in either range are said to


be indeterminate and should not be used as inputs to

any CMOS devices. The voltage ranges are listed in the

table

Table : Logic Level

TTL Input Range in V TTL Output Range in V


Low
High Low High
Indeterminate Indetermina
Logic Logic Logic Logic
State te State
0 1 0 1

0 to
2 to 0 to > .4 and < 2.4
>0.8 and <2
0.8 5 0.4 2.4 to 5

CMOS Input Range in V CMOS Output Range in V

Low Low
Indetermin High Indetermi High
Logic Logic
ate State Logic 1 nate State Logic 1
0 0
>1.5 and
0 to >0.8 and <2 0 to 3.5 to
2 to 5
0.8 1.5 <3.5 5

The fig (a) & (b) show the input logic voltage range

for TTL and CMOS digital ICs.

Figure (a) TTL Voltage Range


Figure (b) CMOS Voltage Range

Current and voltage parameters

V IH ( min ) – High Level Input Voltage: The minimum

voltage level required for logic 1 at an input.

V IL (max) – Low Level Input Voltage: The maximum

voltage level required for logic 0 at an input.

V OH (min) – High Level Output Voltage: The minimum

voltage level at the logic circuit output in the

logic 1 state under defined load conditions.

V OL (max) – Low Level Output Voltage: The maximum

voltage level at the logic circuit output in the

logic 0 state under defined load conditions.

IH – High Level Input Current: The current that flows

into an input when a specified high -level

voltage is applied to that input.

IL – Low Level Input Current: The current that flows

into an input when a specified low - level

voltage is applied to that input.


Noise immunity and Noise margin

- The unwanted, false signals are called noise -

The causes for the noise voltage are stray electric

and magnetic fields on the connecting wires

between logic circuits.

- The noise voltage causes the voltage at the i/p to

a logic circuit to drop below V IH (min) or rise above

V IL (max).

- This could produce unpredictable operation in a

logic circuit.

- The noise immunity of a logic circuit is the

circuit’s ability to tolerate noise without causing a

false change in its o/p voltage.

- A Quantitative measure of a circuit’s noise

immunity is called noise margin. It is expressed

in volts.

a. The high level noise margin (VNH)

V NH = V OH – V IH (min)

b. The low level noise margin )VNL)

V NL = V IL (max) – V OL (min)

Power Dissipation

Each gate is connected to a power supply VCC (VDD in

the case of CMOS). It draws a certain amount of current

during its operation. Since each gate can be in a High,


Transition or Low state, there are three different

currents drawn from power supply.

- I CCH : Current drawn during HIGH state.

- I CCT : Current drawn during HIGH to LOW, LOW to HIGH

transition.

- I CCL : Current drawn during LOW state

For TTL, I CCT the transition current is negligible, in

comparison to I CCH and I CCL . If we assume that I CCH and

I CCL are equal then,

Icc(avg ) = (ICCH + ICCL)/2

Average Power Dissipation PD(avg) = Vcc X Icc(avg)

Propagation Delay

When a signal passes through a logic circuit, it

always experiences a finite time delay. The change

in o/p level occurs after a short time, later than the

change in i/p level that caused it. There are two

propagation delay times specified for logic gates:

1. t PL H : It is the time interval between a

designated point on the i/p pulse and the

corresponding point on the o/p pulse when the o/p

is changing from LOW to HIGH.

2. t PHL : It is the time interval between a

designated point on the i/p pulse and the

corresponding point on the o/p pulse when the o/p

is changing from HIGH to LOW.


Figure Propagation delay

The propagation delay time of a logic gate limits

its maximum operating frequency. The greater the

propagation delay time of a logic gate, the lower is its

maximum operating frequency. This means a high speed

logic gate is a one that has a small propagation delay

time.

Speed power product

It provides a basis for comparison of logic circuit s

when the propagation delay and power dissipation are

important considerations in the selection of the type of

logic family to be used in certain applications. The

speed power product is expressed in Pico joule (pJ). It

is obtained by multiplying the gate propagation delay

by the gate power dissipation. Typically the CMOS

family has much lower value of speed power product as

compared to TTL family.


Fan in and Fan Out

Fan-in is the number of inputs a gate has, for example two

input AND gate has fan-in of two, a three input NAND gate

as a fan-in of three. So a NOT gate always has a fan -in of

one

When the output of any logic gate is connected to

one or more inputs of other logic gates, a load on the

driving gate is created.

In any logic circuit, there is al ways a limit to the

number of load gate inputs that a given logic gate can

drive. This limit is called as Fan-out. Logic families

can also be described as how the current flows between

the output of one logic circuit and the input of another.

Current sourcing and sinking

A device output is said to source current when the

current flows from the power supply, out of the device

output and through the load to ground

Figure Current Sourcing

A device output is said to sink current when the

current flows from the power supply, through the device

output and load to ground

Figure current sinking


TTL (Transistor-Transistor Logic) circuit

There are many versions or families of TTL.

1. Standard TTL.

2. High Speed TTL

3 Low Power TTL.

3. Schhottky TTL.

TTL families have three configurations for outputs.

Totem - Pole output.

Open Collector Output.

Tri state Output

Basic TTL NAND gate.

Figure TTL NAND gate Truth Table

A B Q

0 0 1

0 1 1

1 0 1

1 1 0
Construction

- It consists of multi emitter NPN transistor TR1

- No of emitter represents the no of input. Here

two inputs A & B

- TR1 is the output transistor configured as an

inverter with its emitter grounded and its collector

tied to V cc with a pull-up resistor

- The output is taken from collector terminal of

TR2.

Operation:

1. If both inputs A and B are HIGH (logic 1)

emitter base junction of TR1 is reverse biased so

that it has no emitter current. Hence Q1 is OFF.

But collector base junction is forward biased

supplying base current to TR2 from V CC through R1.

So Q2 is turned ON. Hence output is logic 0.

2. When either or both inputs are at logic 0 (0V),

emitter base junction becomes forward biased.

The value of R1 is selected to ensure that TR1 is

turned ON. Voltage at base current for TR2 is

reduced to zero. Hence Q2 is OFF. Hence output

is logic 1.

Totem Pole Output

Figure shows a basic 2-input TTL NAND gate with a

totem-pole output
Construction

- The circuit is called totem pole because the

three components T3, D, T4 are stacked one on

top of the other in the manner of a totem pole.

- It consists of multi emitter NPN transistor T1

- No of emitter represents the no of input. Here

two inputs Vi1 and Vi2

- Totem pole output circuit, which replaces the

pull-up resistor with a V cc -side transistor sitting on

top of the GND-side output transistor.

- The emitter of the V cc -side transistor (whose

collector is tied to V cc ) is connected to the

collector of the GND-side transistor (whose

emitter is grounded) by a diode.

- The output is taken from the collector of the

GND-side transistor.

Figure: TTL with Totem pole output Truth Table

Input Output

A B Vo

0 0 1

0 1 1

1 0 1

1 1 0
Circuit Operation –High input state

- Two input terminals have positive voltage (logic 1).

The emitter base junction gets reverse biased

because of which there is no emitter current.

- T1 is OFF. Since collector base junction of T1 is

forward biased, so base current of T2 starts flowing

from VCC via R1.

- So T2 gets turned ON, as a result potential at point

N where base of T3 connects to collector of T2

drops so much that T2 is turned ON.

- Simultaneously the current from the T2 emitter

turns ON T4. When T4 is ON, its collector potential

is nearly that of its emitter. Hence output is LOW.

Circuit Operation - Low Input State

- If any of the two inputs or both are LOW T1 is

turned ON and potential of the collector

terminal drops.

- Hence T2 is turned OFF, grounding its emitter and

the base of T4, so T4 is turned OFF.

- Since point where base of T3 connects to collector

of T2 is at VCC, T3 is turned ON.

- Potential of point at which output is taken is VCC

minus drop in R4, T3 and D. so output is at high

state logic 1.

- The function of diode D is to prevent both T3 and

T4 from being turned ON simultaneously.


- If both transistors were ON at the same time,

they would offer low impedance to the supply,

which will draw excessive current and produce

large noise in the output.

Advantage of totem pole circuit occurs in the output

HIGH state.

- T3 is acting as an emitter follower with its

associated low output impedance.

- The impedance provides a short time constant for

charging up any capacitive load on the output.

- This provides very fast rise time waveforms at

TTL outputs.

Disadvantage occurs during the transition from LOW to

HIGH state.

- T4 is turned OFF slowly than T3 turns ON, and so

there is a period of few nanoseconds during which

both transistors are conducting and relatively

large current will be drawn from the supply.

TTL circuit with open collector output

Construction

Construction for the TTL circuit with open collector

output is similar to the basic TTL circuit. The only

difference is the upper transistor is removed.

Circuit Operation

The output will be LOW when T3 is ON and the

output will float when T3 is OFF (can sink current,


cannot source current). To get a HIGH output, an

external resistor must be used. When T3 is ON, the

output is LOW. The optimum value of the pull -up resistor

depends on the value of load current required at the

output.

Figure TTL with open Collector Output

TTL NOR gate

- TTL NOR gate does not use a multiple emitter

transistor; instead each input is applied to the

emitter of separate transistors.

- On the output side, NOR uses a totem pole output

arrangement as NAND circuit.

- NAND and AND gates use multiple emitter

transistors as inputs while NOR and OR gates use

separate input transistors.


Figure: TTL NOR Gate

- In both cases the input will be the cathode of

a PN junction,

- so that HIGH input voltage will turn OFF the

junction and only a small leakage current will

flow.

- LOW input voltage will turn ON the junction and

a relatively large current will flow back to the

signal source.

Comparison of Totem pole and Open collector Outputs

Totem Pole Open Collector

Output state consists of pull Output stage consists of

up transistor, diode resistor and only pull down transistor

pull down transistor.

No need for external pull For proper operation of

up resistor gate external pull up

resistor is needed
Outputs of two gates cannot be Outputs of two gates can

tied together be tied together

High operating speed Low operating speed

Characteristics of TTL family

Advantages

1. High speed operation

2. Moderate power dissipation

3. Available in commercial and military versions

4. Available for wide range of functions

5. Low cost

6. Moderate packaging density


ECL (Emitter coupled logic) circuit

- Bipolar logic family that prevents transistor saturation,

thereby increasing overall switching speed is called

as emitter coupled logic (ECL).

- It operates on the principle of current switching

whereby a fixed bias current less than IC (sat) is

switched from one transistor’s collector to another.

Because of this current mode operation, this logic is

also called as current mode logic ( CML).

- The transistors will never operate in the fully

saturated or cut-off, so it is called as non-saturated

logic.

- Another feature of ECL is that it provid es two outputs,

which are always complementing of each other.

Basic ECL Circuit Operation

The basic circuit will be a differential amplifier

configuration. The V EE supply produces an essentially

fixed current I E , 3mA. This current is allowed to flow

through either Q1 or Q2, depending on the voltage

level at V IN .

The two input logic levels for ECL circuit is – 1.7 V

for logic 0 and – 0.8 V for logic 1


Figure: Basic ECL

Two important points to be noted are:

1) VC1 and VC2 are the complements of each other

and

2) The output voltage levels are not the same as

the input logic levels.

The emitter follower performs two functions

1. They subtract 0.8V from Vc1 and Vc2 to shift the

output levels

2. Provide very low output impedance for large fan -

out and fast charging of load capacitance

3. This circuit produces two complementary outputs

V OU T1 = V IN , and V OU T2 = V IN

ECL OR-NOR gate

The gate consists of a differential amplifier logic

stage with a current source and an emitter follower

driver stage with separate current source. VCC is ground.

Current going into the terminal is positive and coming


out of the terminal is negative. The OR -NOR gate has a

reference threshold voltage VBB in differential

amplifier stage, so the architecture is called as one -

level series gating.

Figure: ECL OR/ NOR

- Differential amplifier stage consists of an input

transistor (Q1 or Q2) and a reference transistor Q3

that acts as a signal switch. The base of Q3 is

connected to a reference voltage V BB1 that has a

value between V CC and V EE .

- Emitter follower driver stage consists of transistors Q4

and Q5 and current sources I2 and I3. For each

logical output there is always one emitter follower

transistor and one current source.


- Applying HIGH input to the base of the transistor

(either Q1 or Q2) turn ON the transistor. If any

input is HIGH corresponding transistor is active and

they will conduct through I1 thereby turning OFF Q3.

- As the current path through the differential switch

changes, base voltages of Q4 and Q5 change, thus

changing the output states So, OUT C is HIGH

meanwhile OUTC is LOW

- Voltage compensation is achieved by providing the

differential amplifier stage with a true current

source that is controlled by generated from a bias

network.

AND–NAND gate

The AND-NAND gate uses macro cell, which is two

level series gating. The differential switch has two

threshold transistors with different base voltages VBB1

and VBB2. The difference between the threshold

voltages is equal to the base emitter voltage of the

input emitter follower, which allows both inputs to use

the same voltages.


Figure ECL AND NAND Logic

Characteristics of ECL
Advantages

1. It has fastest switching speed

2. Storage delay time is eliminated since transistors

are not allowed to go into complete saturation

3. Large fan out

Disadvantages

1. Low noise immunity

2. High power dissipation

MOS

Digital circuits which use MOSFETs are divided in to

three categories:

1) PMOS - uses only P channel MOSFETs

2) NMOS - used only N channel MOSFETs

3) CMOS - uses both P and N channel MOSFETs

Since FET requires small area, it is possible to

fabricate a large number of MOS circuits on a single

small chip.

Advantages of MOS ICs over bipolar:

1. The MOS IC is relatively simple and

inexpensive to fabricate.

2. MOS device size is small and consumes less

power. Because of the small size, the MOS ICs

can accommodate a much larger number of circuit

elements on a single chip.

3. MOS digital ICs normally do not use IC resistor

elements that take up so much of the chip area.


Disadvantage:

1. MOS devices are susceptible to static electricity

damage.

NMOS NAND Logic

The circuit consists of two switching MOSFETs Q2 and

Q3 acting as logic elements and Q1 as load resistor. For

positive logic, 0 V will be logic 0 and positive voltage

(+V DD ) will be logic 1.

If either both or any of the inputs A or B is logic

0, the corresponding MOSFETs are OFF and driving the

output to Logic 1. If both inputs A and B are logic 1, then

both MOSFETs start to conduct and drive the output to

logic 0.

Figure NMOS NAND gate


NMOS NAND Operation Table

Inputs
Q2 Q3 Output
A B

0 0 OFF OFF 1 ( HIGH)

0 1 OFF ON 1 ( HIGH)

1 0 ON OFF 1 ( HIGH)

1 1 ON ON 0 ( LOW)

NMOS NOR Logic Figure NMOS NOR

The circuit consists of two switching MOSFETs Q2 and Q3

acting as logic elements and Q1 as load resistor.

- For positive logic, 0V will be logic 0 and positive

voltage (+VDD) will be logic 1.

NMOS NOR Operation Table

Inputs
Q2 Q3 Output
A B

0 0 OFF OFF 1 ( HIGH)

0 1 OFF ON 0 ( LOW)

1 0 ON OFF 0 ( LOW)

1 1 ON ON 0 ( LOW)
- If any of the inputs A or B is logic 1, the

corresponding MOSFET will conduct causing the

output to go LOW i.e Logic 0.

- If both inputs A and B are logic 0, then both

MOSFETs will be OFF driving the output to logic 1.

NMOS Inverter Logic

Figure NMOS Inverter Logic

NMOS Inverter Operation Table

Input Q2 Output

0 OFF 1 (HIGH)

1 ON 0 (LOW)

CMOS Inverter Logic

- CMOS uses both P (Q1) and N (Q2) channel MOSFETs

in the same circuit to realize the advantages of both

PMOS and NMOS.

- CMOS circuits are faster and even consume less power

than other MOS circuits.


- It has two MOSFETs in series in such a way that

the P channel device’s source is connected to +V DD

and the N channel device’s source is connected to

ground.

- The drains of the two devices are connected

together as the common output.

- When V IN = +V D D , gate of Q1 is at 0V relative to

the source of Q1. So Q1 will be OFF. The gate of Q2

will be at +V DD with respect to its source. Thus Q2

will be ON.

When VIN = 0V, Q1 will have negative potential

with respect to source while Q2=0V, thus Q1 will be

ON and Q2 will be OFF.

Figure CMOS Inverter


Figure CMOS NAND & NOR

CMOS NOR

- CMOS NOR gate is formed by adding a series PMOS

and a parallel NMOS to the inverter.

- This circuit can be analyzed by realizing that a

LOW at any input turns ON its corresponding PMOS and

turns OFF its corresponding NMOS and vice versa.

CMOS NAND

Adding a parallel P Channel MOSFET and a series

N channel MOSFET to the inverter forms NAND gate.

When 0V is given as input it turns ON PMOS and NMOS

gets turned OFF and vice versa. Thus LOW output will

occur only when both inputs are in HIGH state.


Loading and Fan-out in CMOS family

Loading in CMOS logic family differs from that of

TTL. Because the FET used in CMOS logic family is

capacitive load to the driving gate.

The limitations are the charging and the

discharging times associated with the output resistance of

the driving gate and the input capacitance of the load

gates.

When the output of the driving gate is HIGH, the

input capacitance of the load gate is charging through

the output resistance of the driving gate. When the

output of the driving gate is LOW, the capacitance is

discharging.

When large number of load gate inputs is added to

the driving gate output, the total capacitance increases

because the input capacitances effectively appear in

parallel. This increases the charging and discharging

times. As a result, the maximu m operating frequency

increases.

Each CMOS load increases the driving circuit ’ s

propagation delay. CMOS outputs are limited to a fan out


of 50 for low frequency operation. For high frequency

operation the fan out will be less.

Characteristics of CMOS family

Advantages of CMOS family

- Less power consumption

- Can be operated at high voltage

- Fan out is more

- Better Noise margin

disadvantages of CMOS family

Susceptible to static charge

Switching speed low


Dynamic CMOS

A dynamic logic gate uses clocking and charge storage

properties of MOSFETs to implement logic operations.

The clock defines two

Distinct modes of operation.

- Precharge: charge the capacitance

- Evaluate: discharge the capacitance depending on

condition of logic inputs

The clock provides a synchronized data flow, which

makes the technique useful in designing sequential

networks.

Mostly NMOS circuit is pre charged high by a PMOS

device, and a mostly PMOS circuit is pre charged low by

an NMOS device.

PMOS gate uses PMOS transistors to evaluate the

logic, and conditionally charge the o /p high when the

PMOS evaluation transistor is enabled.

Pre charge logic gives a very fast circuit. Pre

charged, NMOS gates couldn’t drive similar gates due to

the fact that their o/ p are pre charged high, and

become i/p to driven gates, causing them to evaluate


during the pre charge cycles. This is avoided in domino

logic by buffering each gate with an o /p inverter.

Figure Dynamic CMOS Logic circuit

The clock Φ drives the pair of the transistors Mn

and Mp. This clock provides synchronization. The output

voltage Vout is taken across the output capacitor Cout.

When Φ =0, the circuit is in Precharge with Mp ON

and Mn OFF. So there is path between Vout and output

allowing Cout to charge to a voltage Vout = V DD . Mp is

called as pre-charge FET.

When Φ =1, drives the circuit to evaluation mode,

where Mp is OFF and Mn is ON. The inputs are valid

and control the switching in the nFET logic array. Mn is

called evaluate transistor.

If the logic block acts as the closed switch the

Cout can discharge through logic array and Mn. This gives

final result of Vout = 0V corresponding to the logic f=0.


If the inputs cause the block to behave like an

open switch from bottom, the charge on Cout is held and

Vout = V DD logically this is an output of 1.

Clocked pre-charged high, 2 input NMOS NAND gate

Clock Mode Vout

0 Pre Capacitor acts as a load. Capacitor

charge becomes charges. The output is high

irrespective of the inputs

1 Evaluate If A & B = 1, output is 0

If either A or B is 0 then the

output is 1
Gated pre-charged low, 2 input PMOS NOR gate

Clock Mode Vout

0 Pre The output is low irrespective of the

charge inputs

1 Evaluate If A & B = 0, output is 1

If either A or B is 1 then the output

is 0

Clocked pre-charged high, 2 input NMOS NOR gate


Clock Mode Vout

0 Pre The output is high irrespective of

charge the inputs

1 Evaluate If A & B = 0, output is 1

If either A or B is 1 then the

output is 0

Gated pre-charged low, 2 input PMOS NAND gate

Clock Mode Vout

0 Pre The output is low irrespective of the

charge inputs

1 Evaluate If A & B = 1, output is 0

If either A or B is 0 then the output

is 1
Advantages over static logic:

1. Avoids duplicating logic twice as both N -tree and

P-tree, as in standard CMOS.

2. Used in very high performance applications

3. Very simple sequential memory circuits

4. High density achievable

5. Consumes less power ( in some cases)

Disadvantages compared to static logic:

- Problems with clock synchronization and timing

Design is more difficult

- Greater propagation delay