You are on page 1of 82

# Digital Logic Families

Introduction

Classification:

1. Bipolar

a. Saturated

b. Unsaturated

i. Schottkey TTL

2. Unipolar

## 2. NMOS(P-channel MOSFET MOSFET)

3. CMOS(Complementary MOSFET)

## into saturation are called saturated logic circuits or

simply saturated logic. TTL is the example of a

saturated logic.

leave.

## 4. Noise immunity and Noise margin

5. Power dissipation

6. Propagation delay

Power and Ground

## The standard value of the DC supply voltage for

TTL is +5V and V DD for CMOS device can range from +3V

to + 1 8 V.

package.

## 5V. The voltage that is not in either range are said to

be indeterminate and should not be used as inputs to

table

## TTL Input Range in V TTL Output Range in V

Low
High Low High
Indeterminate Indetermina
Logic Logic Logic Logic
State te State
0 1 0 1

0 to
2 to 0 to > .4 and < 2.4
>0.8 and <2
0.8 5 0.4 2.4 to 5

## CMOS Input Range in V CMOS Output Range in V

Low Low
Indetermin High Indetermi High
Logic Logic
ate State Logic 1 nate State Logic 1
0 0
>1.5 and
0 to >0.8 and <2 0 to 3.5 to
2 to 5
0.8 1.5 <3.5 5

The fig (a) & (b) show the input logic voltage range

## Figure (a) TTL Voltage Range

Figure (b) CMOS Voltage Range

## voltage is applied to that input.

Noise immunity and Noise margin

V IL (max).

logic circuit.

in volts.

## a. The high level noise margin (VNH)

V NH = V OH – V IH (min)

## b. The low level noise margin )VNL)

V NL = V IL (max) – V OL (min)

Power Dissipation

## during its operation. Since each gate can be in a High,

Transition or Low state, there are three different

transition.

## Average Power Dissipation PD(avg) = Vcc X Icc(avg)

Propagation Delay

## is changing from HIGH to LOW.

Figure Propagation delay

time.

## compared to TTL family.

Fan in and Fan Out

## Fan-in is the number of inputs a gate has, for example two

input AND gate has fan-in of two, a three input NAND gate

one

## Figure current sinking

TTL (Transistor-Transistor Logic) circuit

1. Standard TTL.

## 3 Low Power TTL.

3. Schhottky TTL.

A B Q

0 0 1

0 1 1

1 0 1

1 1 0
Construction

TR2.

Operation:

is logic 1.

## Figure shows a basic 2-input TTL NAND gate with a

totem-pole output
Construction

## - The output is taken from the collector of the

GND-side transistor.

## Figure: TTL with Totem pole output Truth Table

Input Output

A B Vo

0 0 1

0 1 1

1 0 1

1 1 0
Circuit Operation –High input state

terminal drops.

state logic 1.

## T4 from being turned ON simultaneously.

- If both transistors were ON at the same time,

HIGH state.

TTL outputs.

HIGH state.

Construction

## difference is the upper transistor is removed.

Circuit Operation

## output will float when T3 is OFF (can sink current,

cannot source current). To get a HIGH output, an

output.

## separate input transistors.

Figure: TTL NOR Gate

a PN junction,

flow.

signal source.

## up resistor gate external pull up

resistor is needed
Outputs of two gates cannot be Outputs of two gates can

5. Low cost

## 6. Moderate packaging density

ECL (Emitter coupled logic) circuit

logic.

level at V IN .

## for logic 0 and – 0.8 V for logic 1

Figure: Basic ECL

and

output levels

## 3. This circuit produces two complementary outputs

V OU T1 = V IN , and V OU T2 = V IN

## Current going into the terminal is positive and coming

out of the terminal is negative. The OR -NOR gate has a

## transistor and one current source.

- Applying HIGH input to the base of the transistor

network.

AND–NAND gate

## the same voltages.

Figure ECL AND NAND Logic

Characteristics of ECL

MOS

## Digital circuits which use MOSFETs are divided in to

three categories:

small chip.

## 1. The MOS IC is relatively simple and

inexpensive to fabricate.

damage.

logic 0.

## Figure NMOS NAND gate

NMOS NAND Operation Table

Inputs
Q2 Q3 Output
A B

## 0 0 OFF OFF 1 ( HIGH)

0 1 OFF ON 1 ( HIGH)

1 0 ON OFF 1 ( HIGH)

1 1 ON ON 0 ( LOW)

Inputs
Q2 Q3 Output
A B

## 0 0 OFF OFF 1 ( HIGH)

0 1 OFF ON 0 ( LOW)

1 0 ON OFF 0 ( LOW)

1 1 ON ON 0 ( LOW)
- If any of the inputs A or B is logic 1, the

Input Q2 Output

0 OFF 1 (HIGH)

1 ON 0 (LOW)

## than other MOS circuits.

- It has two MOSFETs in series in such a way that

ground.

will be ON.

## Figure CMOS Inverter

Figure CMOS NAND & NOR

CMOS NOR

CMOS NAND

## When 0V is given as input it turns ON PMOS and NMOS

gets turned OFF and vice versa. Thus LOW output will

gates.

discharging.

increases.

## propagation delay. CMOS outputs are limited to a fan out

of 50 for low frequency operation. For high frequency

Dynamic CMOS

networks.

an NMOS device.

## become i/p to driven gates, causing them to evaluate

during the pre charge cycles. This is avoided in domino

## If the logic block acts as the closed switch the

Cout can discharge through logic array and Mn. This gives

## final result of Vout = 0V corresponding to the logic f=0.

If the inputs cause the block to behave like an

## If either A or B is 0 then the

output is 1
Gated pre-charged low, 2 input PMOS NOR gate

charge inputs

is 0

Clock Mode Vout

output is 0

charge inputs

## If either A or B is 0 then the output

is 1
Advantages over static logic: