Digital Logic Circuits Notes

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Digital Logic Circuits Notes

© All Rights Reserved

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Introduction

Classification:

1. Bipolar

a. Saturated

b. Unsaturated

i. Schottkey TTL

2. Unipolar

3. CMOS(Complementary MOSFET)

simply saturated logic. TTL is the example of a

saturated logic.

leave.

5. Power dissipation

6. Propagation delay

Power and Ground

TTL is +5V and V DD for CMOS device can range from +3V

to + 1 8 V.

package.

be indeterminate and should not be used as inputs to

table

Low

High Low High

Indeterminate Indetermina

Logic Logic Logic Logic

State te State

0 1 0 1

0 to

2 to 0 to > .4 and < 2.4

>0.8 and <2

0.8 5 0.4 2.4 to 5

Low Low

Indetermin High Indetermi High

Logic Logic

ate State Logic 1 nate State Logic 1

0 0

>1.5 and

0 to >0.8 and <2 0 to 3.5 to

2 to 5

0.8 1.5 <3.5 5

The fig (a) & (b) show the input logic voltage range

Figure (b) CMOS Voltage Range

Noise immunity and Noise margin

V IL (max).

logic circuit.

in volts.

V NH = V OH – V IH (min)

V NL = V IL (max) – V OL (min)

Power Dissipation

Transition or Low state, there are three different

transition.

Propagation Delay

Figure Propagation delay

time.

Fan in and Fan Out

input AND gate has fan-in of two, a three input NAND gate

one

TTL (Transistor-Transistor Logic) circuit

1. Standard TTL.

3. Schhottky TTL.

A B Q

0 0 1

0 1 1

1 0 1

1 1 0

Construction

TR2.

Operation:

is logic 1.

totem-pole output

Construction

GND-side transistor.

Input Output

A B Vo

0 0 1

0 1 1

1 0 1

1 1 0

Circuit Operation –High input state

terminal drops.

state logic 1.

- If both transistors were ON at the same time,

HIGH state.

TTL outputs.

HIGH state.

Construction

Circuit Operation

cannot source current). To get a HIGH output, an

output.

Figure: TTL NOR Gate

a PN junction,

flow.

signal source.

resistor is needed

Outputs of two gates cannot be Outputs of two gates can

Advantages

5. Low cost

ECL (Emitter coupled logic) circuit

logic.

level at V IN .

Figure: Basic ECL

and

output levels

V OU T1 = V IN , and V OU T2 = V IN

out of the terminal is negative. The OR -NOR gate has a

- Applying HIGH input to the base of the transistor

network.

AND–NAND gate

Figure ECL AND NAND Logic

Characteristics of ECL

Advantages

Disadvantages

MOS

three categories:

small chip.

inexpensive to fabricate.

Disadvantage:

damage.

logic 0.

NMOS NAND Operation Table

Inputs

Q2 Q3 Output

A B

0 1 OFF ON 1 ( HIGH)

1 0 ON OFF 1 ( HIGH)

1 1 ON ON 0 ( LOW)

Inputs

Q2 Q3 Output

A B

0 1 OFF ON 0 ( LOW)

1 0 ON OFF 0 ( LOW)

1 1 ON ON 0 ( LOW)

- If any of the inputs A or B is logic 1, the

Input Q2 Output

0 OFF 1 (HIGH)

1 ON 0 (LOW)

- It has two MOSFETs in series in such a way that

ground.

will be ON.

Figure CMOS NAND & NOR

CMOS NOR

CMOS NAND

gets turned OFF and vice versa. Thus LOW output will

Loading and Fan-out in CMOS family

gates.

discharging.

increases.

of 50 for low frequency operation. For high frequency

Dynamic CMOS

networks.

an NMOS device.

during the pre charge cycles. This is avoided in domino

Cout can discharge through logic array and Mn. This gives

If the inputs cause the block to behave like an

output is 1

Gated pre-charged low, 2 input PMOS NOR gate

charge inputs

is 0

Clock Mode Vout

output is 0

charge inputs

is 1

Advantages over static logic:

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