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Adamson University College of Engineering Computer Engineering Department Microelectronics Laboratory Experiment No.3 CMOS NOR and NAND

Adamson University

College of Engineering Computer Engineering Department

Adamson University College of Engineering Computer Engineering Department Microelectronics Laboratory Experiment No.3 CMOS NOR and NAND

Microelectronics Laboratory

Experiment No.3

CMOS NOR and NAND Gate

Adamson University College of Engineering Computer Engineering Department Microelectronics Laboratory Experiment No.3 CMOS NOR and NAND

Score

 

Exceeds

Meets

Needs

 

CRITERIA

Expectations

Expectations

Improvement

Unsatisfactory

Completeness

 
  • 20 10

  • 15 5

 

Accuracy of

 
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  • 15 5

 

Results

Observation /

 
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  • 15 5

 

Conclusion

Spelling and

 
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  • 15 5

 

Grammar

Presentation and

       

Format

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  • 15 5

Submitted by Lopez, Dylan Josh, D. 10:30 1:30 / Wed / CL15

Submitted to

Engr. Yolly D. Austria, Meng-CpE

Instructor

Date Performed

February 22, 2017

Date Submitted

February 27, 2017

  • I. DATA AND RESULTS

W N

W P

τ PHL

τ PLH

0.80µm

3.20µm

0.71ns

0.45ns

0.80µm

1.60µm

0.65ns

0.82ns

0.80µm

0.80µm

0.62ns

1.75ns

Table 1. Voltage parameters of CMOS NOR

W N

W P

τ PHL

τ PLH

1.60µm

3.20µm

0.46ns

0.33ns

1.60µm

1.60µm

0.40ns

0.55ns

1.60µm

0.80µm

0.37ns

1.07ns

Table 2. Voltage parameters of CMOS NAND

MICROELECTRONICS LABORATORY | ADAMSON UNIVERSITY

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Figure 1 NOR Internal Schematic Figure 2 NOR IC Block Diagram MICROELECTRONICS LABORATORY | ADAMSON UNIVERSITY

Figure 1 NOR Internal Schematic

Figure 1 NOR Internal Schematic Figure 2 NOR IC Block Diagram MICROELECTRONICS LABORATORY | ADAMSON UNIVERSITY

Figure 2 NOR IC Block Diagram

MICROELECTRONICS LABORATORY | ADAMSON UNIVERSITY

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Figure 3 NOR Dynamic Characteristic Analysis Schematic Figure 4 NOR Output Graph when Wp = 3.2microns

Figure 3 NOR Dynamic Characteristic Analysis Schematic

Figure 3 NOR Dynamic Characteristic Analysis Schematic Figure 4 NOR Output Graph when Wp = 3.2microns

Figure 4 NOR Output Graph when Wp = 3.2microns

MICROELECTRONICS LABORATORY | ADAMSON UNIVERSITY

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Figure 5 NOR Output Graph when Wp - 1.6microns Figure 6 NOR Output Graph when Wp

Figure 5 NOR Output Graph when Wp - 1.6microns

Figure 5 NOR Output Graph when Wp - 1.6microns Figure 6 NOR Output Graph when Wp

Figure 6 NOR Output Graph when Wp = 0.8microns

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Figure 7 NAND Internal Schematic Figure 8 NAND IC Block Diagram MICROELECTRONICS LABORATORY | ADAMSON UNIVERSITY

Figure 7 NAND Internal Schematic

Figure 7 NAND Internal Schematic Figure 8 NAND IC Block Diagram MICROELECTRONICS LABORATORY | ADAMSON UNIVERSITY

Figure 8 NAND IC Block Diagram

MICROELECTRONICS LABORATORY | ADAMSON UNIVERSITY

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Figure 9 NAND Dynamic Characteristic Schematic Figure 10 NAND Output Graph when Wp = 3.2microns MICROELECTRONICS

Figure 9 NAND Dynamic Characteristic Schematic

Figure 9 NAND Dynamic Characteristic Schematic Figure 10 NAND Output Graph when Wp = 3.2microns MICROELECTRONICS

Figure 10 NAND Output Graph when Wp = 3.2microns

MICROELECTRONICS LABORATORY | ADAMSON UNIVERSITY

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Figure 11 NAND Output Graph when Wp = 1.6microns Figure 12 NAND Output Graph when Wp

Figure 11 NAND Output Graph when Wp = 1.6microns

Figure 11 NAND Output Graph when Wp = 1.6microns Figure 12 NAND Output Graph when Wp

Figure 12 NAND Output Graph when Wp = 0.8microns

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II.

ANALYSIS / OBSERVATION

In the first table it can be seen that as the width of the PMOS decreases τ PHL also decreases but τ PLH increases. As the behavior of the τ PHL and τ PLH are the same for the second table. In the second table as the width of the NMOS decreased there is a decrease in both τ PHL and τ PLH . Comparing with the dynamic characteristics of the CMOS inverter the τ PHL and τ PLH of NAND and NOR gates are faster.

III.

CONCLUSION

It can be concluded that the Width of the PMOS is directly proportional to the High to Low delay

but inversely proportional to the Low to High Delay; and the Width of the NMOS has an inverse relation with the transient characteristics of the device. Furthermore, the NOT gate has greater delay than NOR and NAND gates.

MICROELECTRONICS LABORATORY | ADAMSON UNIVERSITY

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