Skilled navigation in mobile robotics usually requires solving two problems pertaining to the knowledge of the position of the robot, and to a motion control strategy. When no prior knowledge of the environment is available, the problem becomes even more challenging, since the robot has to build a map of its surroundings as it moves. These three tasks ought to be solved in conjunction due to their interdependency. The present manuscript proposes a novel mobile robot navigation technique using a customized RFID reader with two receiving antennas mounted on the robot and a number of standard RFID tags attached in the robot’s environment to define its path. In here, we show that using the RF signal from the RFID tags as an analog feedback signals can be a promising strategy to navigate a mobile robot within an unknown or uncertain indoor environment. This method is computationally simpler and more cost-effective than many of its counterparts in the state of the art. It is also modular and easy to implement since it is independent of the robot’s architecture and its workspace. A set of numerical computer simulations are provided to illustrate the effectiveness of the proposed scheme

Fig 1.1 Diagram Of Transmitter And Receiver Radio Frequency Identification (RFID) is evolving as a major technology enabler for identifying and tracking goods and assets around the world. It can help hospitals locate expensive equipment more quickly to improve patient care, pharmaceutical companies to


reduce counterfeiting and logistics providers to improve the management of moveable assets. It also promises to enable new efficiencies in the supply chain by tracking goods from the point of manufacture through to the retail point of sale (POS). RFID is used for reading the physical tags on single products, cases, pallets, or reusable containers which emit radio signals to be picked up by reader devices. The complete RFID picture combines the technology of the tags and readers with access to global standardized databases. Tags contain a unique identification number called an Electronic Product Code (EPC), and potentially additional information of interest to manufacturers, healthcare organizations, military organizations or others that need to track the physical location of goods or equipment. RFID can be read at a small distance with no overt physical action required to scan the tag. This project is developed to build a security system for a home/office to prevent unauthorized persons to enter into the important room/chamber by controlling radio frequency identification by checking a suitable RFID card. The RFID tag gives the unique ID whenever it reads the card information. This ID information is send to the micro controller to check the correct card to take a security action. If the card ID matches with the original information, it allows entering into the gate, if not gives the buzzer as an indication of unauthorized person tried to enter into the gate





The RFID reader which is present in the block diagram always try to read data to shaft of DC motor. the motor and microcontroller is generated then the power through the IC will be on then it can detect the number present on the RFID tag and send it to the reader and the reader detects the number and send to microcontroller using MAX232. DC motors contains drivers through which is it accessed. if the card belongs to the authorized person (if it is a valid one) then it will allow for further operations i.. and is send through a microcontroller by using a voltage level translator that is MAX232. • Whenever we want to perform a task the authorized person keeps the RFID Tag on the RFID Reader it reads the and checks whether it is a VALID or INVALID card. We connect a power supply to acess motor. • • • The voltage levels are different from RFID to AVR controller. it will send the information to the controller and controller will reads the data.2 . so for the conversion Now for ROBOT and RFID there is a L293D IC because we can’t directly access In RFID there is one coil and one chip present. present on the RFID tag.e. 4 . • • • The data is received from particular reader.WORKING PRINCIPLE • • • • In this project will see how the robot is used in day-to-day life. by inducing the magnetic flux. emf of levels we use MAX232 as LEVEL TRANSLATOR. controller and LCD. Microcontroller is attached to robot which is having 2 wheels . compared with pre-stored values.wheels are connected Robot contains minimum of 2 motors compulsory so as to provide direction . based on the technology used and is For observing the number on the RFID tag we use a LCD display in our project.

and Lock Bits through the JTAG Interface 5 .1 ATMEGA32 MICROCONTROLLER ARCHITECTURE • High-performance. MICROCONTROLLER The microcontroller here we are using is AVR (ADVANCED VIRTUAL RISC ARCHIECTURE). 3. Fuses.000 Write/Erase Cycles Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – – – 1024 Bytes EEPROM 2K Byte Internal SRAM Programming Lock for Software Security Endurance: 100.3. Low-power AVR 8-bit Microcontroller • Advanced RISC Architecture – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier • Non-volatile Program and Data Memories – – – – – 32K Bytes of In-System Self-Programmable Flash Endurance: 10. 1149.The features of this microcontroller are discussed in detail.000 Write/Erase Cycles • JTAG (IEEE std. EEPROM.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash.

• Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler.5 .1 mA 6 . 10-bit ADC 8 Single-ended Channels 7 Differential Channels in TQFP Package Only 2 Differential Channels with Programmable Gain at 1x.5. or 200x – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Programmable Watchdog Timer with Separate On-chip Oscillator • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle. Power-down. ADC Noise Reduction. Standby and Extended Standby • I/O and Packages – 32 Programmable I/O Lines – 40-pin PDIP. 44-lead TQFP. Power-save.8 MHz for ATmega32L – 0 . and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel. 3V. Compare Mode. 10x. and 44-pad QFN/MLF • Operating Voltages – 4. 25°C for ATmega32L – Active: 1.16 MHz for ATmega32 • Power Consumption at 1 MHz.5V for ATmega32 • Speed Grades – 0 .

2 PIN CONFIGURATION: FIG: 3.2 PIN DIAGRAM ATMEGA32 7 .35 mA 3.– Idle Mode: 0.

2 Block Diagram FIG 3.1 Block Diagram of ATMEGA32 8 .2.BLOCK DIAGRAM Fig 3.

an SPI serial port. the Asynchronous Timer continues to run. Timer/Counters. The Power-down mode saves the register contents but freezes the Oscillator. Internal and External Interrupts. allowing two independent registers to be accessed in one single instruction executed in one clock cycle. and interrupt system to continue functioning. SPI port. Two-wire interface.OVERVIEW: The ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. an 8channel. In 9 . a programmable Watchdog Timer with Internal Oscillator. 2K byte SRAM. SRAM. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. A/D Converter. a byte oriented Two-wire Serial Interface. In Power-save mode. By executing powerful instructions in a single clock cycle. The ATmega32 provides the following features: 32K bytes of In-System Programmable Flash Program memory with Read-While-Write capabilities. 10-bit ADC with optional differential input stage with programmable gain (TQFP package only). All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU). The Idle mode stops the CPU while allowing the USART. allowing the user to maintain a timer base while the rest of the device is sleeping. On-chip Debugging support and programming. 1024 bytes EEPROM. The AVR core combines a rich instruction set with 32 general purpose working registers. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC. three flexible Timer/Counters with compare modes. 32 general purpose I/O lines. to minimize switching noise during ADC conversions. 32 general purpose working registers. and six software selectable power saving modes. disabling all other chip functions until the next External Interrupt or Hardware Reset. the ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. a JTAG interface for Boundary-scan. a serial programmable USART.

by a conventional nonvolatile memory programmer. The device is manufactured using Atmel’s high density nonvolatile memory technology. In Extended Standby mode. PIN DESCRIPTIONS VCC GND Digital supply voltage. providing true Read-While-Write operation. if the A/D Converter is not used. even if the clock is not running. or by an On-chip Boot program running on the AVR core. the crystal/resonator Oscillator is running while the rest of the device is sleeping. The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. The PortA pins are tri-stated when a reset condition becomes active. The boot program can use any interface to download the application program in the Application Flash memory. Port A Port A (PA7-PA0) also serves as an 8-bit bi-directional I/O port. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip. The Port B output buffers have symmetrical drive characteristics 10 . Port B (PB7-PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).Standby mode. Port pins can provide internal pull-up resistors (selected for each bit). the Atmel ATmega32 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. Ground. Software in the Boot Flash section will continue to run while the Application Flash section is updated. When pins PA0 to PA7 are used as inputs and are externally pulled low. they will source current if the internal pull-up resistors are activated. The On-chip ISP Flash allows the program memory to be reprogrammed insystem through an SPI serial interface. This allows very fast start-up combined with low-power consumption. both the main Oscillator and the Asynchronous Timer continue to run. Port A serves as the analog inputs to the A/D Converter.

Port C pins that are externally pulled low will source current if the pull-up resistors are activated. even if the clock is not running. As inputs. Either a quartz crystal or a ceramic resonator may be used. As inputs. respectively. The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. Input to the inverting Oscillator amplifier and input to the internal Reset Input. Port D pins that are externally pulled low will source current if the pull-up resistors are activated. RESET pulse length will generate a reset. even if the clock is not running. even if the clock is not running Port D also serves the functions of various special features of the ATmega32. XTAL2 Crystal Oscillator XTAL1 and XTAL2 are input and output. Port C also serves the functions of the JTAG interface and other special features of the ATmega32 Port D (PD7-PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).with both high sink and source capability. The Port D pins are tri-stated when a reset condition becomes active. Port C (PC7-PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. The CKOPT Fuse selects between two Output from the inverting Oscillator amplifier. as shown in Figure 12. The Port C pins are tri-stated when a reset condition becomes active. of an inverting amplifier which can be configured for use as an On-chip Oscillator. Port B pins that are externally pulled low will source current if the pull-up resistors are activated. As inputs. XTAL1 clock operating circuit. A low level on this pin for longer than the minimum 11 .

the amount of stray capacitance.2 Crystal Oscillator Connections The Oscillator can operate in three different modes.different Oscillator amplifier modes. the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed. When CKOPT is unprogrammed. The operating mode is selected by the fuses CKSEL3. For resonators.. each optimized for a specific frequency range. It should be externally connected to VCC. Fig: 3. and the electromagnetic noise of the environment. even if the ADC is not 12 . C1 and C2 should always be equal for both crystals and resonators. For ceramic resonators. When CKOPT is programmed. the Oscillator output will oscillate will a full rail-to-rail swing on the output. This reduces power consumption considerably.1 AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. The optimal value of the capacitors depends on the crystal or resonator in use. Table: 3. This mode has a wide frequency range. the Oscillator has a smaller output swing. the capacitor values given by the manufacturer should be used. This mode is suitable when operating in a very noisy environment or when the output from XTAL2 drives a second clock buffer. This mode has a limited frequency range and it cannot be used to drive other clock buffers.2.1 as shown in table below. Some initial guidelines for choosing capacitors for use with crystals are given in Table below.

control peripherals. and handle interrupts. perform calculations. The CPU must therefore be able to access memories.used. The main function of the CPU core is to ensure correct program execution. AREF AREF is the analog reference pin for the A/D Converter. 3. it should be connected to VCC through a low-pass filter.3 AVR CPU CORE: Introduction This section discusses the AVR core architecture in general. 13 . If the ADC is used.

the AVR uses a Harvard architecture – with separate memories and buses for program and data.Fig: 3.3 Block Diagram of THE AVR MCU Architecture Architectural Overview In order to maximize performance and parallelism. This concept 14 . Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed. the next instruction is pre-fetched from the program memory.

the Boot program section and the Application Program section. described later in this section. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. In a typical ALU operation. Program flow is provided by conditional and unconditional jump and call instructions. two operands are output from the Register File. These added function registers are the 16-bit X-. Most AVR instructions have a single 16-bit word format. and Z-register. This allows single-cycle Arithmetic Logic Unit (ALU) operation. Y-. The program memory is InSystem Reprogrammable Flash memory. the Status Register is updated to reflect information about the result of the operation. Both sections have dedicated Lock bits for write and read/write protection. able to directly address the whole address space. Single register operations can also be executed in the ALU. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Program Flash memory space is divided in two sections. and the result is stored back in the Register File – in one clock cycle. 15 . After an arithmetic operation. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. Every program memory address contains a 16. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. the operation is executed. One of the address pointers can also be used as an address pointer for look up tables in Flash Program memory.or 32-bit instruction.enables instructions to be executed in every clock cycle.

This information can be used for altering program flow in 16 . Within a single clock cycle. or as the Data Space locations following those of the Register File. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers. The lower the interrupt vector address. ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. The Stack Pointer SP is read/write accessible in the I/O space. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. arithmetic operations between general purpose registers or between a register and an immediate are executed. The interrupts have priority in accordance with their interrupt vector position. The Stack is effectively allocated in the general data SRAM. logical. The memory spaces in the AVR architecture are all linear and regular memory maps.During interrupts and subroutine calls. The I/O Memory can be accessed directly. All interrupts have a separate interrupt vector in the interrupt vector table. and other I/O functions. See the “Instruction Set” section for a detailed description. and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. the higher the priority. The ALU operations are divided into three main categories – arithmetic. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. the return address Program Counter (PC) is stored on the Stack. SPI. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. and bitfunctions. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed).

. Half Carry is useful in BCD arithmetic. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a half carry in some arithmetic operations. The I bit can also be set and cleared by the application with the SEI and CLI instructions. This must be handled by software. The AVR Status Register – SREG – is defined as: • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. none of the interrupts are enabled independent of the individual interrupt enable settings. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. S = N ⊕ V 17 . • Bit 4 – S: Sign Bit. as described in the instruction set reference. Note that the Status Register is updated after all ALU operations.order to perform conditional operations. and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. The individual interrupt enable control is then performed in separate control registers. See the “Instruction Set Description” for detailed information. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This will in many cases remove the need for using the dedicated compare instructions. resulting in faster and more compact code. as specified in the Instruction Set Reference. If the Global Interrupt Enable Register is cleared. A bit from a register in the Register File can be copied into T by the BST instruction.

See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input 18 . General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetic’s.The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. In order to achieve the required performance and flexibility. See the “Instruction Set Description” for detailed information. See the “Instruction Set Description” for detailed information. See the “Instruction Set Description” for detailed information. See the “Instruction Set Description” for detailed information.

These registers are 16-bit address pointers for indirect addressing of the Data Space. Although not being physically implemented as SRAM locations. The X-register. Y.2 X-. Y-. As shown in Figure. Z.R31 have some added functions to their general purpose usage.Registers 19 .. Fig: 3.Fig: 3. each register is also assigned a data memory address. and Z are defined as described in Figure below. as the X-.3. The three indirect address registers X. Y-register and Z-register The registers R26.1 AVR CPU General Purpose Working Registers . this memory organization provides great flexibility in access of the registers. mapping them directly into the first 32 locations of the user Data Space. Y-.3. and Z-pointer Registers can be set to index any register in the file.

Stack Pointer The Stack is mainly used for storing temporary data. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction. Instruction Execution Timing 20 . for storing local variables and for storing return addresses after interrupts and subroutine calls. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. This implies that a Stack PUSH command decreases the Stack Pointer. the SPH Register will not be present. In this case. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The number of bits actually used is implementation dependent. and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer must be set to point above $60. Note that the Stack is implemented as growing from higher memory locations to lower memory locations.

Fig: 3.This section describes the general access timing concepts for instruction execution. Figure shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost. directly generated from the selected clock source for the chip. and the result is stored back to the destination register. 21 . The AVR CPU is driven by the CPU clock clk CPU.3 parallel instruction fetches and instruction executions enabled by the Harvard architecture Below figure shows the internal timing concept for the Register File.3. In a single clock cycle an ALU operation using two register operands is executed. functions per clocks. No internal clock division is used. and functions per power-unit.

the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is set. the interrupt will not be triggered 22 . The user software can write logic one to the I-bit to enable nested interrupts. If the interrupt condition disappears before the interrupt is enabled. These interrupts do not necessarily have Interrupt Flags. For these interrupts. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. See the section “Memory Programming” on page 254 for details.Fig: 3. This feature improves software security. the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The first type is triggered by an event that sets the Interrupt Flag. the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The second type of interrupts will trigger as long as the interrupt condition is present. There are basically two types of interrupts. the Interrupt Flag will be set and remembered until the interrupt is enabled. if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared. Similarly. and hardware clears the corresponding Interrupt Flag.4 Internal Timing Concepts for the Register File Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. Depending on the Program Counter value. and will then be executed by order of priority. or the flag is cleared by software.3. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared. When an interrupt occurs.

This increase comes in addition to the start-up time from the selected sleep mode. If an interrupt occurs when the MCU is in sleep mode. During this four clock cycle period. the Program Counter (two bytes) is popped back from the Stack. this instruction is completed before the interrupt is served. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. During these four clock cycles. No interrupt will be executed after the CLI instruction. The pin driver is strong enough to 23 . A return from an interrupt handling routine takes four clock cycles. The vector is normally a jump to the interrupt routine. it will always return to the main program and execute one more instruction before any pending interrupt is served. When using the CLI instruction to disable interrupts. After four clock cycles the program vector address for the actual interrupt handling routine is executed. the interrupt execution response time is increased by four clock cycles. even if it occurs simultaneously with the CLI instruction.4 I/O PORTS Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.When the AVR exits from an interrupt. the interrupts will be immediately disabled. nor restored when returning from an interrupt routine. Each output buffer has symmetrical drive characteristics with both high sink and source capability. If an interrupt occurs during execution of a multi-cycle instruction. Note that the Status Register is not automatically stored when entering an interrupt routine. the Stack Pointer is incremented by two. This must be handled by software. the Program Counter is pushed onto the Stack. 3. and the I-bit in SREG is set. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. and this jump takes three clock cycles.

i.e. The Port Input Pins I/O location is read only..drive LED displays directly. while the Data Register and the Data Direction Register are read/write. PORTB3 for bit no. However. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure: 3. and a lower case “n” represents the bit number. A lower case “x” represents the numbering letter for the port. Data Direction Register – DDRx. when using the register or bit defines in a program. Figure shows a functional description of one I/O-port pin. 3 in Port B. here documented generally as PORTxn. 24 . All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. the precise form must be used. the Pull-up Disable – PUD bit in SFIOR disables the pull-up function for all pins in all ports when set. All I/O pins have protection diodes to both VCC and Ground. here generically called Pxn. one each for the Data Register – PORTx. and the Port Input Pins – PINx.4 I/O Pin Equivalent Schematic All registers and bit references in this section are written in general form. Three I/O memory address locations are allocated for each port. In addition.

PORTxn. PORTxn} = 0b01) or output low ({DDxn. as a high-impudent environment will not notice the difference between a strong high driver and a pull-up. PORTxn} = 0b10) must occur. PORTxn} = 0b11).1 General Digital I/O Configuring the Pin Each port pin consists of three register bits: DDxn. and PINxn. PORTxn} = 0b00) and output high ({DDxn. When switching between tri-state ({DDxn. As shown in “Register Description for I/O Ports” .Figure: 3. the pull-up enabled state is fully acceptable. and the PINxn bits at the PINx I/O address. If PORTxn is written logic one when the pin is configured as an input pin. To switch the pull-up resistor off. even if no clocks are running. Normally.4. If this is not the case. Digital Input Enable and Sleep Modes 25 . the PORTxn bits at the PORTx I/O address. PORTxn has to be written logic zero or the pin has to be configured as an output pin. an intermediate state with either pull-up enabled ({DDxn. the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. the DDxn bits are accessed at the DDRx I/O address. the pullup resistor is activated. The port pins are tri-stated when a reset condition becomes active.

Active mode and Idle mode). floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset. but the figure serves as a generic description applicable 26 . The signal denoted SLEEP in the figure. SLEEP is also Over ridden by various other alternate functions as described in “Alternate Port Functions” If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as “Interrupt on Rising Edge. is to enable the internal pullup. Standby mode.10. since this may cause excessive currents if the pin is accidentally configured as an output. the digital input signal can be clamped to ground at the input of the Schmitt-trigger. and Extended Standby mode to avoid high power consumption if some input signals are left floating. Alternate Port Functions Most port pins have alternate functions in addition to being General Digital I/Os. Power-save mode. If the External Interrupt Request is not enabled. Figure 26 shows how the port pin control signals from the simplified Figure 23 can be overridden by alternate functions. Unconnected pins If some pins are unused. or have an analog signal level close to VCC/2.As shown in Figure 3. The overriding signals may not be present in all port pins. The simplest method to ensure a defined level of an unused pin. Connecting unused pins directly to VCC or GND is not recommended. is set by the MCU Sleep Controller in Power-down mode. it is recommended to ensure that these pins have a defined level. Falling Edge. as the clamping in these sleep modes produces the requested logic change. the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes. SLEEP is active also for these pins. SLEEP is overridden for port pins enabled as External Interrupt pins. or Any Logic Change on Pin” while the External Interrupt is not enabled. Even though most of the digital inputs are disabled in the deep sleep modes as described above.

it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. Special Function I/O Register – SFIOR • Bit 2 – PUD: Pull-up disable When this bit is written to one. Table: 3.4 Port A Pins Alternate Function Alternate Functions of Port B 27 . See “Configuring the Pin” Alternate Functions Of Port A Port A has an alternate function as analog input for the ADC as shown in Table 22. Refer to the alternate function description for further details. PORTxn} = 0b01).The following subsections shortly describe the alternate functions for each port. If some Port A pins are configured as outputs. the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn. and relate the overriding signals to the alternate function.

the data direction of this pin is controlled by DDB6. Bit 7 SCK: Master Clock output. When the SPI is enabled as a Slave. When the SPI is enabled as a Master. • MOSI – Port B. the data direction of this pin is controlled by DDB7. As a Slave.5 Port B Pins Alternate Functions • SCK – Port B. Slave Data input for SPI. this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master. Slave Data output pin for SPI. • SS – Port B. When the SPI is enabled as a Slave. Bit 5 MOSI: SPI Master Data output. the pull-up can still be controlled by the PORTB7 bit. When the SPI is enabled as a Slave. Bit 4 SS: Slave Select input. this pin is configured as an input regardless of the setting of DDB7. this pin is configured as an input regardless of the setting of DDB4.Table: 3. this pin is configured as an input regardless of the setting of DDB6. When the pin is forced by the SPI to be an input. Slave Clock input pin for SPI. Bit 6 MISO: Master Data input. the pull-up can still be controlled by the PORTB5 bit. When the SPI is enabled as a Slave. the data direction of this pin is controlled by DDB5. the SPI is activated when this pin is 28 . • MISO – Port B. When the pin is forced by the SPI to be an input. When the SPI is enabled as a Master.

INT2. • AIN0/INT2 – Port B. Bit 3 AIN1. Output Compare Match output: The PB3 pin can serve as an external output for the Timer/Counter0 Compare Match. The OC0 pin is also the output pin for the PWM mode timer function. Analog Comparator Positive input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. If the JTAG interface is enabled. • T1 – Port B.9. Bit 2 AIN0. Bit 1 T1. Bit 0 T0. USART External Clock. The XCK pin is active only when the USART operates in Synchronous mode. When the SPI is enabled as a Master.driven low. • AIN1/OC0 – Port B. When the pin is forced by the SPI to be an input. XCK. 29 . PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. the pull-up can still be controlled by the PORTB4 bit. the pull-up resistors on pins PC5(TDI). Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. The Data Direction Register (DDB0) controls whether the clock is output (DDB0 set) or input (DDB0 cleared). External Interrupt Source 2: The PB2 pin can serve as an external interrupt source to the MCU. Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 3. • T0/XCK – Port B. Timer/Counter0 Counter Source. the data direction of this pin is controlled by DDB4. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. OC0. Analog Comparator Negative Input. Timer/Counter1 Counter Source.

and becomes the inverting output of the Oscillator amplifier. When the JTAG interface is enabled. Bit 4 30 . a Crystal Oscillator is connected to this pin. and the pin cannot be used as an I/O pin • TDI – Port C. this pin cannot be used as an I/O pin. and becomes the input of the inverting Oscillator amplifier. and the pin cannot be used as an I/O pin. JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). • TOSC1 – Port C. Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2. Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2. pin PC6 is disconnected from the port. Bit 7 TOSC2.Table: 3. pin PC7 is disconnected from the port. • TDO – Port C. In this mode. Bit 6 TOSC1. In this mode.6 Port C Pins Alternate Functions • TOSC2 – Port C. Bit 5 TDI. a Crystal Oscillator is connected to this pin.

In this mode. • TCK – Port C. the pull-up can still be controlled by the PORTC1 bit. When this pin is used by the Twowire Serial Interface. When this pin is used by the Two-wire Serial Interface. • TMS – Port C. there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal. this pin cannot be used as an I/O pin.12. Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface.TDO. JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. JTAG Test Data Out: Serial output data from Instruction Register or Data Register. pin PC0 is disconnected from the port and becomes the Serial Clock I/O pin for the Two-wire Serial Interface. this pin cannot be used as an I/O pin. When enabled. this pin cannot be used as an I/O pin. In this mode. When the JTAG interface is enabled. In addition. 31 . Bit 0 SCL. The TD0 pin is tri-stated unless TAP states that shifts out data are entered. JTAG Test Clock: JTAG operation is synchronous to TCK. This is not shown in the figure. and the pin is driven by an open drain driver with slew-rate limitation. Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 3. Bit 3 TMS. Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface. Bit 2 TCK. the Two-wire Serial Interface enables slew-rate controls on the output pins PC0 and PC1. spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal. pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the Two-wire Serial Interface. Note: 1. the pull-up can still be controlled by the PORTC0 bit. and the pin is driven by an open drain driver with slew-rate limitation. • SCL – Port C. When the JTAG interface is enabled. When the JTAG interface is enabled. Bit 1 SDA. • SDA – Port C.

• OC1A – Port D. The OC2 pin is also the output pin for the PWM mode timer function. The pin has to be configured as an output (DDD7 set (one)) to serve this function.Table: 3. Bit 7 OC2. The OC1A pin is also the output pin for the PWM mode timer function. Bit 5 OC1A. Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A.7 Port D Pins Alternate Functions The alternate pin configuration is as follows: • OC2 – Port D. • OC1B – Port D. Bit 6 ICP1 – Input Capture Pin: The PD6 pin can act as an Input Capture pin for Timer/Counter1. • ICP1 – Port D. Bit 4 32 . Timer/Counter2 Output Compare Match output: The PD7 pin can serve as an external output for the Timer/Counter2 Output Compare.

this pin is configured as an output regardless of the value of DDD1. Bit 3 INT1. • INT1 – Port D. Bit 0 RXD. When the USART Transmitter is enabled. • RXD – Port D. The pin has to be configured as an output to serve this function. Bit 1 TXD. 8. Transmit Data (Data output pin for the USART). When the USART Receiver is enabled this pin is configured as an input regardless of the value of DDD0.OC1B. Bit 2 INT0. or 9 Data Bits and 1 or 2 Stop Bits 33 . The main features are: • • • • • Full Duplex Operation (Independent Serial Receive and Transmit Registers) Asynchronous or Synchronous Operation Master or Slave Clocked Synchronous Operation High Resolution Baud Rate Generator Supports Serial Frames with 5. • INT0 – Port D. External Interrupt Source 0: The PD2 pin can serve as an external interrupt source. 3. • TXD – Port D. 6. External Interrupt Source 1: The PD3 pin can serve as an external interrupt source. When the USART forces this pin to be an input. Output Compare Match B output: The PD4 pin can serve as an external output for the Timer/Counter1 Output Compare B. 7. the pull-up can still be controlled by the PORTD0 bit. Receive Data (Data input pin for the USART).5 USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.

Overview A simplified block diagram of the USART transmitter is shown in CPU accessible I/O . Transmitter and Receiver. Control Registers are shared by all units. The clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation. and the baud rate generator. 34 . TX Data Register Empty. and RX Complete Multi-processor Communication Mode Double Speed Asynchronous Communication Mode.The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator.• • • • • • • Odd or Even Parity Generation and Parity Check Supported by Hardware Data OverRun Detection Framing Error Detection Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter Three Separate Interrupts on TX Complete.

The receiver supports the same frame formats as the transmitter.Fig 3. The write buffer allows a continuous transfer of data without any delay between frames. 35 . a Shift Register and a two level receive buffer (UDR). control logic. The Transmitter consists of a single write buffer. the receiver includes a parity checker. a serial Shift Register. The XCK (Transfer Clock) pin is only used by Synchronous Transfer mode. and can detect frame error. data overrun and parity errors. The recovery units are used for asynchronous data reception. The Receiver is the most complex part of the USART module due to its clock and data recovery units. In addition to the recovery units.5 Block Diagram Of Usart . parity generator and control logic for handling different serial frame formats.

The USART is therefore more resistant to Data OverRun (DOR) error conditions. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • • • • • Bit locations inside all USART Registers Baud Rate Generation Transmitter Operation Transmit Buffer Functionality Receiver Operation However. the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer. This is done by allowing the received data to remain in the serial Shift Register (see Figure 69) if the Buffer Registers are full. Otherwise the error status will be lost since the buffer state is lost. The following control bits have changed name. Therefore the status bits must always be read before the UDR Register is read.AVR USART vs. The USART supports four modes of clock operation: Normal Asynchronous. Double Speed Asynchronous. • The receiver Shift Register can now act as a third buffer level. 36 . Master Synchronous and Slave Synchronous mode. but have same functionality and register location: • CHR9 is changed to UCSZ2 • OR is changed to DOR Clock Generation The clock generation logic generates the base clock for the Transmitter and Receiver. until a new start bit is detected. Therefore the UDR must only be read once for each incoming data! More important is the fact that the Error Flags (FE and DOR) and the 9th data bit (RXB8) are buffered with the data in the receive buffer.

37 . The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Note however that the receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery. the XCK pin will be used as either clock input (Slave) or clock output (Master). there are no downsides. and therefore a more accurate baud rate setting and system clock are required when this mode is used. This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation: Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1). The dependency between the clock edges and data sampling or data change is the same. effectively doubling the transfer rate for asynchronous communication. The description in this section refers to for details. External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. the data will be changed at falling XCK edge and sampled at rising XCK edge.Double Speed Operation (U2X) The transfer rate can be doubled by setting the U2X bit in UCSRA. As Figure 71 shows. Set this bit to zero when using synchronous operation. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and receiver. Setting this bit only has effect for the asynchronous operation. If UCPOL is set. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8. The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. External Clock External clocking is used by the synchronous slave modes of operation. For the Transmitter.

Be careful when using bit test instructions (SBIC and SBIS). The receive buffer consists of a two level FIFO. does not contain any unread data). Data written to UDR when the UDRE Flag is not set.. When data is written to the transmit buffer. and the Transmitter is enabled. Then the data will be serially transmitted on the TxD pin. since these also will change the state of the FIFO. do not use read modify write instructions (SBI and CBI) on this location.e. Reading the UDR Register location will return the contents of the Receive Data Buffer Register (RXB). The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR Register location. Due to this behavior of the receive buffer. The FIFO will change its state whenever the receive buffer is accessed. the Transmitter will load the data into the transmit Shift Register when the Shift Register is empty. the receive buffer will be flushed and consequently the RXC bit will become 38 . will be ignored by the USART Transmitter.USART REGISTER DESCRIPTION USART I/O Data Register – UDR The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. USART Control and Status Register A – UCSRA • Bit 7 – RXC: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i. If the receiver is disabled.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. • Bit 5 – UDRE: USART Data Register Empty The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. • Bit 3 – DOR: Data OverRun This bit is set if a Data OverRun condition is detected. UDRE is set after a reset to indicate that the transmitter is ready. and therefore ready to be written. 39 . This bit is valid until the receive buffer (UDR) is read. Write this bit to zero when using synchronous operation. The RXC Flag can be used to generate a Receive Complete interrupt (see description of the RXCIE bit). • Bit 6 – TXC: USART Transmit Complete This flag bit is set when the entire frame in the transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDR). the buffer is empty. If UDRE is one. The UDRE Flag can generate a Data Register empty Interrupt (see description of the UDRIE bit). or it can be cleared by writing a one to its bit location. Always set this bit to zero when writing to UCSRA • Bit 1 – U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. it is a new character waiting in the receive Shift Register. This bit is valid until the receive buffer (UDR) is read. • Bit 2 – PE: Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1).e. Always set this bit to zero when writing to UCSRA.. The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed. i. Always set this bit to zero when writing to UCSRA. A Data OverRun occurs when the receive buffer is full (two characters). The FE bit is zero when the stop bit of received data is one. This bit is valid until the receive buffer (UDR) is read. and a new start bit is detected. • Bit 4 – FE: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. when the first stop bit of the next character in the receive buffer is zero.zero.

40 . • Bit 6 – TXCIE: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC Flag. the Global Interrupt Flag in SREG is written to one and the RXC bit in UCSRA is set. and PE Flags. The transmitter is unaffected by the MPCM setting. USART Control and Status Register B – UCSRB • Bit 7 – RXCIE: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC Flag. For more detailed information. A USART Transmit Complete Interrupt will be generated only if the TXCIE bit is written to one. the Global Interrupt Flag in SREG is written to one and the TXC bit in UCSRA is set. Disabling the Receiver will flush the receive buffer invalidating the FE. the Global Interrupt Flag in SREG is written to one and the UDRE bit in UCSRA is set. When the MPCM bit is written to one. • Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDRE Flag. The Receiver will override normal port operation for the RxD pin when enabled. all the incoming frames received by the USART receiver that do not contain address information will be ignored. • Bit 4 – RXEN: Receiver Enable Writing this bit to one enables the USART Receiver. A USART Receive Complete Interrupt will be generated only if the RXCIE bit is written to one. A Data Register Empty Interrupt will be generated only if the UDRIE bit is written to one.• Bit 0 – MPCM: Multi-processor Communication Mode This bit enables the Multi-processor Communication mode. DOR.

• Bit 3 – TXEN: Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD pin when enabled. when the transmit Shift Register and transmit Buffer Register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port. • Bit 2 – UCSZ2: Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Character Size) in a frame the receiver and transmitter use. • Bit 1 – RXB8: Receive Data Bit 8 RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR. • Bit 0 – TXB8: Transmit Data Bit 8 TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR. USART Control and Status Register C – UCSRC

• Bit 7 – URSEL: Register Select This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when reading UCSRC. The URSEL must be one when writing the UCSRC. • Bit 6 – UMSEL: USART Mode Select This bit selects between Asynchronous and Synchronous mode of operation.

• Bit 5:4 – UPM1:0: Parity Mode


These bits enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE Flag in UCSRA will be set.

• Bit 3 – USBS: Stop Bit Select This bit selects the number of Stop Bits to be inserted by the Transmitter. The Receiver ignores this setting.

• Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use. • Bit 0 – UCPOL: Clock Polarity This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).


 Radio Frequency Identification (RFID) is a silicon chip-based transponder that communicates via radio waves. Radio Frequency Identification is a technology which uses tags as a component in an integrated supply chain solution set that will evolve over the next several years. RFID tags contain a chip which holds an electronic product code (EPC) number that points to additional data detailing the contents of the package.  Applications are evolving to comply with shipping products to automatically processing transactions based on RFID technology.

4.1 Operating principles of RFID systems
There is a huge variety of different operating principles for RFID systems. The picture below provides a short survey of known operation principles (The numbers refer to the relating chapters in the book). The most important principles - ‘inductive coupling’ and ‘backscatter coupling’ are described more detailed below. Inductive Coupling (3.2.1) An inductively coupled transponder comprises of an electronic data carrying device, usually a single microchip and a large area coil that functions as an antenna. Inductively coupled transponders are almost always operated passively. This means that all the energy needed for the operation of the microchip has to be provided by the reader. For this purpose, the reader's antenna coil generates a strong, high frequency electro-magnetic field, which penetrates the cross -section of the coil area and the area around the coil. Because the wavelength of the frequency range used (< 135 kHz: 2400 m, 13.56 MHz: 22.1


with a resonant frequency that corresponds with the transmission frequency of the reader. The voltage U at the transponder coil reaches a maximum due to resonance step-up in the parallel resonant circuit. which can be used to generate the required field strengths for the operation of the remote transponder. By induction. A small part of the emitted field penetrates the antenna coil of the transponder.m) is several times greater than the distance between the reader's antenna and the transponder. the electro-magnetic field may be treated as a simple magnetic alternating field with regard to the distance between transponder and antenna . inductively coupled systems are based upon a transformer-type coupling between the primary coil in the reader and the secondary coil in the 44 . which is some distance away from the coil of the reader. The antenna coil of the transponder and the capacitor C1 to form a resonant circuit tuned to the transmission frequency of the reader. a voltage Ui is generated in the transponder's antenna coil. the capacitance of which is selected such that it combines with the coil inductance of the antenna coil to form a parallel resonant circuit. A capacitor C1 is connected in parallel with the reader's antenna coil. Fig. Very high currents are generated in the antenna coil of the reader by resonance step-up in the parallel resonant circuit. This voltage is rectified and serves as the power supply for the data carrying device (microchip). 4.1 Block digram of RFID interfacing As described above.

transponder. If a resonant transponder (i. To reclaim the data in the reader. This additional power consumption can be measured as voltage drop at the internal resistance in the reader antennae through the supply current to the reader's antenna. If the switching on and off of the load resistor is controlled by data. then this draws energy from the magnetic field. the self-resonant frequency of the transponder corresponds with the transmission frequency of the reader) is placed within the magnetic alternating field of the reader's antenna. This type of data transfer is called load modulation.2 sample circuit of the power supply and load modulator in a transponder Picture above: If the additional load resistor in the transponder is switched on and off at a very high elementary frequency fH. This represents the demodulation of an amplitude modulated signal. so that the transponder is located in the near field of the transmitter antenna .16 . This is true when the distance between the coils does not exceed 0. then two spectral lines are created at a distance 45 . the voltage measured at the reader's antenna is rectified. Fig4.e. The switching on and off of a load resistance at the transponder's antenna therefore effects voltage changes at the reader's antenna and thus has the effect of an amplitude modulation of the antenna voltage by the remote transponder. then this data can be transferred from the transponder to the reader. An example circuit is shown in the chapter "Reader – Low Cost Layout".

as is the case for antenna at the appropriate frequency for example. The voltage obtained may also be sufficient to serve as a power supply for short ranges. Fig 4. and these can be easily detected (however fH must be less than fREADER). which have a particularly low threshold voltage.3 Operation principle of a backscatter transüonder Power P1 is emitted from the reader's antenna. Data transfer is by the ASK. FSK or PSK modulation of the subcarrier in time with the data flow.of  f H around the transmission frequency of the reader.2) We know from the field of RADAR technology that electromagnetic waves are reflected by objects with dimensions greater than around half the wavelength of the wave. The power P1' is supplied to the antenna connections as HF voltage and after rectification by the diodes D1 and D2 this can be used as turn on voltage for the deactivation or activation of the power saving "power-down" mode. Backscatter Coupling (3. In the terminology of radio technology the new elementary frequency is called a subcarrier.Objects that are in resonance with the wave front that hits them.2. a small proportion of which (free space attenuation) reaches the transponder's antenna. 46 . The efficiency with which an object reflects electromagnetic waves is described by its reflection cross-section. The diodes used here are low barrier Schottky diodes. This represents an amplitude modulation of the subcarrier. have a particularly large reflection cross-section.

47 . For this reason. It is particularly important to ensure that RFID systems do not interfere with nearby radio and television. The need to exercise care with regard to other radio services significantly restricts the range of suitable operating frequencies available to an RFID system. a load resistor RL connected in parallel with the antenna is switched on and off in time with the data stream to be transmitted. In order to transmit data from the transponder to the reader. and they can also be used for RFID applications.A proportion of the incoming power P1' is reflected by the antenna and returned as power P2. it is usually only possible to use frequency ranges that have been reserved specifically for industrial. marine and aeronautical radio services and mobile telephones. Frequency Ranges Because RFID systems generate and radiate electromagnetic waves. which is stronger by powers of ten. The amplitude of the power P2 reflected from the transponder can thus be modulated The power P2 reflected from the transponder is radiated into free space. is to a large degree suppressed by the directional coupler. The reflection characteristics of the antenna can be influenced by altering the load connected to the antenna. scientific or medical applications or for short range devices. The "forward" signal of the transmitter. industry). These are the frequencies classified worldwide as ISM frequency ranges (Industrial-Scientific-Medical) or SRD frequency ranges. The reflected signal therefore travels into the antenna connection of the reader in the "backwards direction" and can be decoupled using a directional coupler and transferred to the receiver input of a reader. mobile radio services (police. they are justifiably classified as radio systems. The function of other radio services must under no circumstances be disrupted or impaired by the operation of RFID systems. security services. A small proportion of this) is picked up by the reader's antenna.

smartlabels (ISO 15693.SERIAL COMMUNICATION INTRODUCTION: 48 .400 MHz 6.. wide spread usage for contactless smartcards (ISO 14443.800 MHz article surveilance) only 13.957 .... backscatter coupling. used for EAS (electronic transmission power 72 dBµA/m max 13.6 MHz RFID UHF (RFID only). rarely used for 865 .795 MHz 7. Listen before talk 10 . I-Code. ISM).frequency range < 135 kHz 3. frequency ranges for RFID-Systems comment allowed fieldstrength / low frequency. 100 mW 100 mW ERP Europe only 2W ERP (=3.283 item management (ISO 18000-3).553 .1 Frequency ranges used for RFID-systems (August 2006) 5 . Tag-It. .567 MHz coupling...56 MHz. inductive coupling medium frequency.5 dBµA/m 42 dBµA/m 9 dBµA/m 60(!) dBµA/m 8.6 . medium frequency (13. LEGIC.155 . .) and 26. inductive coupling EAS medium frequency (ISM). 868 MHz 865... 6. special applications only 42 dBµA/m MHz 433 MHz UHF (ISM). 27. Listen before talk UHF (RFID only).. 3.. MIFARE..8W EIRP) Europe only Table: 4.765 . 867...400 .). medium frequency (ISM). inductive coupling. inductive 13.

On the software side of things. The pulse length however was cut down to 3/16th of a RS232 bit length to conserve power considering these devices are mainly used on diaries. Serial Cables can be longer than Parallel cables. IrDA-1 (The first infra red specifications) was capable of 115. Only two pins are commonly used. 3. laptops and palmtops. You don't need as many wires as parallel transmission. 2. The serial port transmits a '1' as -3 to -25 volts and a '0' as +3 to +25 volts where as a parallel port transmits a '0' as 0v and a '1' as 5v. However could you imagine transmitting 8 bits of data at the one time across the room and being able to (from the devices point of view) decipher which bits are which? Therefore serial transmission is used where one bit is sent at a time.2k baud and was interfaced into a UART. Microcontroller's have also proven to be quite popular recently. In most cases. there are many more registers that you have to attend to than on a Standard Parallel Port. Serial Communication reduces the pin count of these MPU's. If your device needs to be mounted a far distance away from the computer then 3 core cable (Null Modem Configuration) is going to be a lot cheaper that running 19 or 25 core cable. any device you connect to the serial port will need the serial transmission converted back to parallel so that it can be used. 4. Therefore the serial port can have a maximum swing of 50V compared to the parallel port which has a maximum swing of 5 Volts. Therefore cable loss is not going to be as much of a problem for serial cables as they are for parallel. You may have seen many electronic diaries and palmtop computers which have infra red capabilities build in. However you must take into account the cost of the interfacing at each end.The Serial Port is harder to interface than the Parallel Port. This can be done using a UART. Infra Red devices have proven quite popular recently. Many of these have in built SCI (Serial Communications Interfaces) which can be used to talk to the outside world. (SPP) So what are the advantages of using serial data transfer rather than parallel? 1. Transmit Data (TXD) and Receive Data (RXD) compared with at least 8 pins if you use an 8 bit Parallel method (You may also require a Strobe) 49 .

RS-232 is now widely used for direct connections between data acquisition devices and computer systems. RS-232 STANDARDS One of the advantages of a serial system is that it lends itself to transmission over telephone lines. As in the definition of RS-232. parallel communications require at least as many lines as there are bits in a word being transmitted (for an 8-bit word. a minimum of 8 lines are needed). RS-232 is defined as the “Interface between data terminal equipment and data communications equipment using serial binary data exchange. In contrast. and have jumpers to provide “handshaking” for those devices that require it. 5 50 . the 9-pin cables do not include many of the uncommonly used connections. A modem cable has pin-to-pin connections. placed onto a standard voice-grade telephone line. the computer is data transmission equipment (DTE). while serial is often used between computers and other peripherals.2.Information being transferred between data processing equipment and peripherals is in the form of digital data which is transmitted in either a serial or parallel mode.” This definition defines data terminal equipment (DTE) as the computer.to-pin connections of modem cables. 5. 9 or 25-pin wiring. Null modem cables are designed for this situation. However. The 25-pin cable connects every pin. Serial transmission involves the sending of data one bit at a time. many interface products are not data communications equipment (DCE). RS-232 cables are commonly available with 4. Serial transmission is beneficial for long distance communications. and is designed to connect a DTE device to a DCE device. The serial digital data can be converted by modem. These jumpers connect pins 4. In addition to communications between computer equipment over telephone lines. whereas parallel is designed for short distances or when very high transmission rates are required. over a single communications line. and converted back to serial digital data at the receiving end of the line by another modem. null modem cables have different internal wiring to allow DTE devices to communicate with one another. Parallel communications are used mainly for connections between test instruments or computers and printers. while data communications equipment (DCE) is the modem. 4-pin cables provide the bare minimum connections. rather than having the pin. Officially.1.

it is recommended that the user obtain the two devices to be connected. To connect this port to a standard 25. are you connecting two DTE devices (null modem cable) or a DTE device to a DCE device (modem cable)? Second. 5. Selecting a Cable The major consideration in choosing an RS-232 cable is what devices are to be connected? First. this computer and many new expansion boards for PC’s feature a 9-pin serial port. It is interesting to note however. TA adapter. and then determine which cable is required. 4. The advent of the IBM PC AT has created a new wrinkle in RS-232 communications. A "Mark" (Logic 1) will be between -3 and -25 Volts.000 BPS!. 3.and 8. A "Space" (logic 0) will be between +3 and +25 Volts. a 9-to-25-pin adaptor cable can be utilized. RS-232D has been recently released. An open circuit voltage should never exceed 25 volts.3.pin port. or the user can create his own cable specifically for that purpose. 51 . The electrical specifications of the serial port are contained in the EIA (Electronics Industry Association) RS232C standard.) Data Communications Equipment are devices such as your modem. 5. The driver should be able to handle this without damage. that the RS232C standard specifies a maximum baud rate of 20. male or female. Rather than having the standard 25-pin connector.1. It states many parameters such as 1. (In Reference to GND) A short circuit current should not exceed 500mA. which is rather slow by today's standards. and also pins 6 and 20. Line Capacitance. For more information please consult the EIA RS232-C standard. what connectors are required on each end. (Take note of this one!) Above is no where near a complete list of the EIA standard. These are DCE (Data Communications Equipment) and DTE (Data Terminal Equipment. plotter etc while Data Terminal Equipment is your Computer or Terminal. The region between +3 and -3 volts is undefined. 2. 25-pin or 9-pin (AT style)? Usually. A new standard. HARDWARE PROPERTIES Devices which use serial cables for their communication are split into two categories. Maximum Baud Rates etc are also included.

Pin 3 Pin 2 Pin 7 Pin 8 Pin 6 Pin 5 Pin 1 Pin 4 TD RD RTS CTS DSR SG CD DTR Transmit Data Receive Data Request To Send Clear Send Data Ready Signal Ground Carrier Detect Data Terminal Ready Ring Indicator To Set Abbreviation Full Name Pin 9 RI 52 . Serial Pin outs (D9Connector Table 5.Serial Ports come in two "sizes". thus you will require a female connector on your device. there are the D-Type 25 pin connector and the DType 9 pin connector both of which are male on the back of the PC.1 DB9 Pin Connectors D-Type9 Pin No. Below is a table of pin connections for the 9 pin and 25 pin D-Type connectors.

Fig 5.1: DB9 PIN &DB 25 PIN configurations Abbreviation TD Full Name Transmit Data 53 Function Serial Data Output (TXD) .

This is the opposite to DSR. This line informs the Modem that the UART is ready to exchange data. A typical activity that might use a synchronous protocol would be a transmission of files from one point to another. this Line becomes active. When the modem detects a "Carrier" from the modem at the other end of the phone line.1 :DB9 pin functionality 5. synchronous communication requires that each end of an exchange of communication respond in turn without initiating a new communication.1. a response is returned indicating success or the need to resend.RD CTS Receive Data Clear to Send Serial Data Input (RXD) This line indicates that the Modem is ready to exchange data.4 DATA TRANSFER SYNCHRONOUS DATA TRANSFER In program-to-program communication. As each transmission is received.1. This tells the Modem that the UART is ready to link. This tells the UART that the modem is ready to establish a link. 54 . Goes active when modem detects a ringing signal DCD Data Carrier Detect DSR Data Set Ready DTR Data Terminal Ready Request To Send RTS RI Ring Indicator Table 5.

each party would be required to wait a specified interval before speaking.28/V. particularly applications where ±12V is not available. For this reason. The difficulty with asynchronous communications is that the receiver must have a way to distinguish between valid data and noise. MAX233. 55 . For example. since their low-power shutdown mode reduces power dissipation to less than 5μW. 5.24 communications interfaces. a telephone conversation is asynchronous because both parties can talk whenever they like. The MAX225. MAX235. asynchronous communication is sometimes called start-stop transmission. These parts are especially useful in battery-powered systems. In computer communications. If the communication were synchronous. this is usually accomplished through a special start bit and stop bit at the beginning and end of each piece of data.2 LINE DRIVER The MAX220–MAX249 family of line drivers/receivers is intended for all EIA/TIA-232E and V. and MAX245/MAX246/MAX247 use no external components and are recommended for applications where printed circuit board space is critical.ASYNCHRONOUS DATA TRANSFER The term asynchronous is usually used to describe communications in which data can be transmitted intermittently rather than in a steady stream.

RS-232 receivers. A small amount of power may be drawn from the +10V (V+) and -10V (V-) outputs to power external circuitry except on the MAX225 and MAX245–MAX247.are not regulated. Do not load V+ and V. RS-232 drivers. Dual Charge-Pump Voltage Converter The MAX220–MAX249 has two internal charge-pumps that convert +5V to ±10V (unloaded) for RS-232 driver operation. and receiver and transmitter enable control inputs. where these pins are not available. The second converter uses capacitor C2 to invert +10V to -10V on C4 at the V. The first converter uses capacitor C1 to double the +5V input to +10V on C3 at the V+ output.2: Internal Diagram of MAX232 The MAX220–MAX249 contain four sections: dual charge-pump DC-DC voltage converters.output.to a point that violates the minimum ±5V EIA/TIA-232E driver output voltage when sourcing current 56 .Fig 5. V+ and V. so the output voltage drops with increasing load current.

5V). and V+ falls to +5V. the C1 capacitor must not be installed and the SHDN pin must be tied to VCC. V. Table 2 shows the effects of the shutdown control and receiver three state controls on the receiver outputs. Outputs can be driven to ±15V. These include a minimum 3kΩ load.to external circuitry. MAX236.232E and V. The internal input pull-up resistors typically source 12μA. in three-state mode. MAX241. MAX230. Driver outputs turn off and enter a highimpedance state—where leakage current is typically Microamperes (maximum 25μA) when in shutdown mode. and maximum operating temperature. When using the shutdown feature in the MAX222. MAX235. or when device power is removed. Output swing is guaranteed to meet the EIA/TIA. This is because V+ is internally connected to VCC in shutdown mode. avoid using V+ and Vto power external circuitry. The inputs of unused drivers can be left unconnected since 400kΩ input pull-up resistors to VCC are built in (except for the MAX220).5V. MAX240. MAX225. Input thresholds are both TTL and CMOS compatible. and the MAX223.from V+ and V. which calls for ±5V minimum driver output levels under worst-case conditions. The MAX220 does not have pull-up resistors to force the outputs of the unused drivers low. and MAX241 have both a receiver three-state control line and a low-power shutdown control. MAX235. The MAX239 has a receiver three-state control line.28 specification. When these parts are shut down.+0. RS-232 DRIVERS: The typical driver output voltage swing is ±8V when loaded with a nominal 5kΩ RS-232 receiver and VCC = +5V. VCC = +4.falls to 0V.3V) to (V. and MAX245–MAX249. For applications where a +10V external supply is applied to the V+ pin (instead of using the internal charge pump to generate +10V). The power supply current typically drops to 8μA in shutdown mode. except in shutdown mode where the pull-ups are disabled. 57 . MAX240. MAX225. Connect unused inputs to GND or VCC. Unloaded driver output voltage ranges from (V+ -1. The pull-up resistors force the outputs of unused drivers low because all drivers invert. MAX236.

The device enters shutdown mode and transmitters go into a three-state mode with logic high on both ENTA and ENTB. The control states. A logic high at the A-side control input (ENA) causes the four A-side receivers and drivers to go into a three-state mode. The ENRA and ENRB receiver enable inputs each control four receiver outputs. The ENRA and ENRB receiver enable inputs each control five receiver outputs. In shutdown mode. active receivers operate in a low-power receive mode at data rates up to 20kbits/sec. The MAX246 has ten receivers and eight drivers with two control pins.Receiver and Transmitter Enable Control Inputs The MAX225 and MAX245–MAX249 feature transmitter and receiver enable controls. Enabled receivers function in the lowpower receive mode when in shutdown. the B-side control input (ENB) causes the four B-side drivers and receivers to go into a three-state mode. The receiver enables inputs control the full-speed receive and three-state modes. The MAX247 provides nine receivers and eight drivers with four control pins. one aside and one B-side receiver (RA5 and RB5) remain active at all times. APPLICATIONS: • • • • • Portable Computers Low-Power Modems Interface Translation Battery-Powered RS-232 Systems Multi drop RS-232 Networks 6.The MAX249 provides ten receivers and six drivers with four control pins. The receivers have three modes of operation: full-speed receive (normal active) ‚ three-state (disabled) ‚ and low power receive (enabled receivers continue to function at lower data rates). As in the MAX245. LCDMODULE 58 . The MAX244 has no control pins and is not included in these tables. Similarly. The device enters shutdown mode when all transmitters are disabled. each controlling one side of the device. The transmitter enable inputs also control the shutdown mode.

However. watches. There are two major types of LCDs which are: Dynamic-scattering LCDs and Field-effect LCDs Field-effect LCDs are normally used in such applications where source of energy is a prime factor (e.). It’s like a cheap “monitor” that you can hook in all of your gadgets. The details of the pins are: Table: 6.A liquid crystal is a material (normally organic for LCDs) that will flow like a liquid but whose molecular structure has some properties normally associated with solids.g. It is limited to a temperature range of about 0C to 60C and lifetime is an area of concern. The response time of LCDs is in the range of 100 to 300ms. because LCDs can chemically degrade. The Liquid Crystal Display (LCD) is a low power device. and their height is limited to 2 inches.The lifetime of LCDs is steadily increasing beyond 10. These can be easily interfaced to microcontrollers The modules have 16 PIN’S for interfacing. However.1 59 . Since the color generated by LCD units is dependent on the source of illumination. an LCD requires an external or internal light source.. The most popular one can display 2 lines of 16 characters. portable instrumentation etc. On the other hand. They come in various types. light-scattering units are available up to 8 inches in height. LCD Modules can present textual information to user.000+hours limit.They absorb considerably less power than the light-scattering type. the cost for field-effect units is typically higher. The power requirement is typically in the order of microwatts for the LCD. there is a wide range of color choice. Field-effect LCD is used in the project for displaying the appropriate information The turn-on and turn-off time is an important consideration in all displays.

So that LCD can recognize the operation to be performed based on the bit status.1 16 x 2 Char LCD RS (Command / Data): This bit is to specify whether received byte is command or data. RS RS = 0 = 1 => => Command Data RW (Read / Write): A 60 K D 7 .NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Hardware Diagram: NAME VSS (GND supply) VCC (+5V supply) VEE (contrast adjust) RS R/W E DBO DB1 DB2 DB3 DB4 DB5 DB6 DB7 LED (+) LED (-) Fig: 6.

The READ operation here is just ACK bit to know whether LCD is free or not.RW bit is to specify whether controller wants READ from LCD or WRITE to LCD. RW RW = 0 = 1 => => Write Read EN (Enable LCD): EN bit is to ENABLE or DISABLE the LCD.bridge driver circuit is required for driving the motor which amplifies the current up to 1A. EN EN = 0 => => High Impedance = 1 Low Impedance ACK (LCD Ready): ACK bit is to acknowledge the MCU that LCD is free so that it can send new command or data to be stored in its internal Ram locations ACK = 1 => => Not ACK ACK ACK = 0 7. So in L293D driver IC internally four Hbridge drivers are provided for four channels. MOTORS Microcontroller provides 10 milli amps current from each port. This current is not sufficient to drive the motors so an H. Each channel provides max 1A current so it 61 . Whenever controller wants to write something into LCD or READ acknowledgment from LCD it needs to enable the LCD.

The L293 and L298 H-Bridges are configured in this way. The lower the number. The higher the value. When the value is 1 to 255. When the value is a negative number from -1 to -128. L293D MOTOR DRIVER Description: A DC Motor Object is a Hardware Object that uses three digital I/O lines to control the direction. For bidirectional controlling of dc motors forward and backward two channels are connected to one motor and other two channels to another motor. the motor turns backwards at the speed indicated by the value. the faster the motor turns in reverse. The DC Motor Object is capable of driving a DC Motor at 255 different speeds. the motor turns in a direction specified by a direction value at the rate specified by the speed value. the motor turns forward at the speed indicated by the value. active braking. The H-Bridge that the DC Motor Object is designed to work with has 2 drive inputs and a PWM input. When the speed value is configured with a range of -128 to +127. the faster the motor turns. the faster the motor turns. The higher the value. the motor is at free-spinning rest. When the value is a positive number from 1 to 127. This L293D driver IC is interfaced with port 1 of microcontroller. the motor turns forward at the speed indicated by the value. and braking of a DC Motor by communicating with an H-Bridge circuit which handles the voltage and current requirements of the DC Motor it is connected to. the motor is at free-spinning rest. When this value is 0. and friction braking modes. the speed value is then also used to specify the direction that the motor turns. A brake value 62 . The physical direction that the motor will turn can be set to: forward turns clockwise and reverse turns counterclockwise or forward turns counter-clockwise and reverse turns clockwise. The speed at which the motor spins is specified by a single value which can be configured to have a range of 0 to 255 or -128 to +127.can drive four dc motors in one direction. in forward or reverse plus free spinning. speed. When this value is 0. By changing the polarities of dc motor it can move in forward and backward. When the speed value is configured with a range of 0 to 255.

a Pulse-Width-Modulated (PWM) clock cycle is outputted on the I/O line specified by the IOLineP property.1 Circuit Diagram Of H-Bridge Circuit Operation: The DC Motor Object monitors the Value and the Brake properties. and braking of a DC Motor by outputting control signals to a H-Bridge motor driver circuit such as the L293D. speed. and based on their numeric values controls the direction.is used to apply brakes and when this value is set to 1. The method used to stop the motor is active braking. 63 . The maximum number of DC Motor Objects that can be dimensioned in a single application program is 2. the speed value is ignored and the motor will quickly stop. To control the speed of the motor. limited only be the number of PWM channels are available. H BRIDGE CIRCUIT Fig 7.

the faster the motor will turn in reverse. both of the control lines specified by the IOLine1 and IOLine2 properties are set to the value specified by the InvertOutB property and the PWM output is set to the value specified by the Mode property. If the motor is being driven by an L293D H-Bridge. In this case. The L293D H-Bridge monitors the state of all three of these control lines and controls the DC motor accordingly. then the Pulse-Width of the PWM output is set to correspond to the Value property. The required state of the PWM while braking is on depends on the control circuit that is used. the I/O line specified by the IOLine1 property is set to 5 Volts and the I/O line specified by the IOLine2 property is set to 0 Volts. effectively driving the motor back the other way which causes the motor to come to an abrupt stop. If the Unsigned property is set to 1. the Mode property need to be 1 which will set the PWM line to 5 Volts so that the motor will remain on to allow the braking power to be applied.The direction that the motor spins is controlled by setting one of the control lines specified by IOLine1 and IOLine2 properties to 1 while setting the other to 0. the Direction property is set to 0. a 0 in the Value property will cause the PWM line to output 0 Volts. and the control lines specified by the IOLine1 and IOLine2 properties are set according to the value that the Direction property was set to. the application program is expected to set the value of the Direction property. This will cause the DC Motor to go backwards at a speed specified by the Value property. then the operation is modified so that the Value property is always expected to be a positive value. The actual direction that the DC Motor spins when going in the "forward" direction can be reversed by setting the Invert Out property to 1. The lower the number (down to negative 128). If the Value property is greater than 0. Whether or not the brakes are applied is controlled by outputting the same value to both of the control lines specified by IOLine1 and IOLine2 properties. In this case. In normal operation. When the Brake property is set to 1. then setting both the control lines to the same value will cause the Motor to generate power back into itself. 64 . causing the motor to be at a full stop.

giving frequencies of 5-Mhz. A full PWM clock cycle has been reached when the Period-Duration Counter reaches the value specified by the period property. because any value above 10 will never be reached by the Period-Duration Counter. The period property can be set to any value from 1 to 255. The combination of the period and the pre scale properties specify the PWM clock cycle's frequency.However. Likewise. then the value property's effective range is 0 . This scaled down 5-Mhz clock is used to increment a Period-Duration Counter.5-Khz. The L293D H- 65 . The L293D H-Bridge is a dual H-Bridge and each one of its H-Bridges is a set of 2 push-pull drivers that use a total of 3 I/O lines. IOLine1 and IOLine2 can be any 2 I/O lines of the OOPic's 31 I/O lines. 1. if the period property is set to 10. or 16. 4. If the period property Is set to 255 then the value property's range is 0 .25-Mhz. This results in 765 possible frequencies. and 312. then the Mode property needs to be 0 which will set the PWM line to 0 Volts so that the Motor will shut off when the mechanical brake is applied. IOLineP can be I/O line 17 or 18.255. The pre scale property can be set to divide the 5Mhz clock by 1. The period property also dictates the resolution of the PWM pulse. The pre scale property specifies how many times a 5-Mhz clock is divided.10. if the Brake line is connected to a mechanical braking system.

POWERSUPPLY BLOCK DIAGRAM 66 . Fig 7.2 Block diagram of L-293D & DC Motor 8.Bridge requires a power supply that is capable of handling enough current to dive the attached DC motor.

In our circuit the transformer of 230v/15-0-15v is used to perform the step down operation where a 230V AC appears as 15V AC across the secondary winding. it gives isolation between the power source and power supply circuitries. Diode has the property that will let the electron flow easily in one direction at proper 67 . The current rating of the transformer used in our project is 2A.1 Block Diagram of Power Supply INDIVIDUAL UNIT DESCRIPTION: STEP DOWN TRANSFORMER: When AC is applied to the primary winding of the power transformer it can either be stepped down or up depending on the value of DC needed. Apart from stepping down AC voltages. rectification is normally achieved using a solid state diode. The next alteration will temporarily cause the reverse.Fig 8. One alteration of input causes the top of the transformer to be positive and the bottom negative. RECTIFIER UNIT: In the power supply unit.

The DC voltage appearing across the output terminals of the bridge rectifier will be somewhat less than 90% of the applied rms value.8v pulsating DC. A commonly used circuit for supplying large amounts of DC power is the bridge rectifier. Since each altercation produces a resulting output pulse. A load resistor R1 is connected so that a reference to the ground is maintained. At the same time one of the other two diodes conducts for the negative voltage that is applied from the bottom winding due to the forward bias for that diode. Opposite ends of the transformer will therefore always be 180 deg out of phase with each other. The DC output has a ripple frequency of 100Hz. In this circuit due to positive half cycleD1 & D2 will conduct to give 10. The primary purpose of a regulator is to aid the rectifier and filter circuit in providing a constant 68 . As AC is applied to the diode.biasing condition. For a positive cycle. This capacitor is also called as a decoupling capacitor or a bypassing capacitor. The output obtained is not a pure DC and therefore filtration has to be done. Reversing the polarity of voltage will not permit electron flow. A bridge rectifier of four diodes (4*IN4007) are used to achieve full wave rectification. Normally one alteration of the input voltage will reverse the polarities. VOLTAGE REGULATORS: The voltage regulators play an important role in any power supply unit. C1R1 is for bypassing ripples. frequency = 2*50 Hz. Two diodes will conduct during the negative cycle and the other two will conduct during the positive half cycle. electrons only flow when the anode and cathode is negative. two diodes are connected to the positive voltage at the top winding and only one diode conducts. FILTERING UNIT Filter circuits which are usually capacitors acting as a surge arrester always follow the rectifier unit. is used not only to ‘short’ the ripple with frequency of 120Hz to ground but also to leave the frequency of the DC to appear at the output.

IC7812 and 7912 is used in this project for providing +12v and –12v DC supply. also called a variable bench power supply. With a regulator connected to the DC output. Fig 8.2 Common Terminal with mounting base A variable regulated power supply. CIRCUIT DIAGRAM 69 . is one where you can continuously adjust the output voltage to your requirements. Power supplies without regulators have an inherent problem of changing DC voltage values due to variations in the load or due to fluctuations in the AC liner voltage. the voltage can be maintained within a close tolerant region of the desired output.DC voltage to the device. Varying the output of the power supply is the recommended way to test a project after having double checked parts placement against circuit drawings and the parts placement guide.

to ground. at high frequencies this capacitor is not very efficient. This IC contains all the circuitry needed to accept any input voltage from 8 to 18 volts and produce a steady +5 volt output. the . The 1000µf capacitor serves as a "reservoir" which maintains a reasonable input voltage to the 7805 throughout the entire cycle of the ac line voltage. and the capacitor is quite capable of sustaining any reasonable load in between charging pulses. 70 . However. The electrolytic capacitor smooth’s out any long-term or low frequency variations. it will reduce its output voltage instead. such as digital IC switching effects. Therefore.25 volt). It also contains current-limiting circuitry and thermal overload protection. The two rectifier diodes keep recharging the reservoir capacitor on alternate half-cycles of the line voltage. so that the IC won't be damaged in case of excessive load current.01µf capacitors serve to help keep the power supply output voltage constant when load conditions change.3 Circuit diagram of power supply CIRCUIT DESCRIPTION The +5 volt power supply is based on the commercial 7805 voltage regulator IC.Fig 8. The 10µf and .01µf is included to bypass high-frequency changes. accurate to within 5% (0.

The LED and its series resistor serve as a pilot light to indicate when the power supply is on.3" red jumper wire. Then try the power supply again. LED is reversed. quickly note the results you did obtain. Turn on your voltmeter. then turn power off and look through the following troubleshooting chart. I like to use a miniature LED here. move your redvoltmeter lead to the positive lead of the 1000µf reservoir capacitor. 71 . Then I know it's safe to remove or install components for the next experiment. If you get the correct results. at the power supply output. I also use this LED to tell me when the reservoir capacitor is completely discharged after power is turned off. and then turn on power to your transformer and power supply circuit. possibly higher. Output voltage is steady at +5.75 to +5. If your results are different. but LED remains off. Connect the red lead to the upper end of the 0. and skip down to the Discussion below. If you get these results. turn off your power supply and voltmeter. You should see about +17 volts here. so it will serve that function without being obtrusive or distracting while I'm performing an experiment. and the red pilot LED should turn on. and connect the black (Common or Ground) lead to the negative lead of the 1000µf capacitor. Remove it and re-insert it in the opposite direction.25) here. TESTING: Set your voltmeter to measure voltages up to 20 volts. You should measure a steady +5 volts (+4.

it will explode and leave a large mess to be cleaned up. but then declines steadily. Once you are sure that your power supply is working correctly in all respects. Your main rectifier diodes are installed backwards. One or both electrolytic capacitors is reversed. If you leave power on too long. Then move down to the concluding discussion below.Resistor is the wrong value or connected incorrectly. Refer back to the assembly diagram and install them correctly. Check and correct capacitor orientation. Output voltage is incorrect. 16V. Make sure it is a 1K resistor (brown-black-red) and is connected from the lower end of the red jumper to the left (anode) end of the LED. The reversed one will be warm or hot to the touch.0. Verify correct installation and replace if necessary. Then try the power supply again.7805 three terminal +5V Voltage regulator D1.5V secondary 500mA 9.1uF disc ceramic capacitor T1.1000uF. 25V.transformer 220V primary 7.DB102 bridge diode D2.1N4001 silicon rectifier diode C1. turn off power to your circuit and your voltmeter. SOFTWARE MODULES TYPES OF MODULES: • CVAVR IDE TOOL 72 . Output voltage is negative. Output voltage rises to +5 volts. electrolytic capacitor C2. 7805 voltage regulator is installed incorrectly or is defective.10uF. and then try the power supply again. electrolytic capacitor C3. PARTS LIST U1.

allowing the entire programming and test procedure to be accomplished under the control of a single protocol. The primary advantage of this feature is that it allows manufacturers of electronic devices to integrate programming and testing into a single production phase. micro controllers. rather than requiring the chip to be programmed prior to installing it into the system. rather than requiring a separate programming stage prior to assembling the system. and other programmable electronic chips to be programmed while installed in a complete system. Most programmable logic devices use a variant of the JTAG protocol for ISP. in order to facilitate easier integration with automated testing procedures. Typically. Other devices usually use proprietary protocols or protocols defined by older standards. assembly programming still prevails. particularly for digital-signal 73 . However. This may allow manufacturers to program the chips in their own system's production line instead of buying preprogrammed chips from a manufacturer or distributor. chips supporting ISP have internal circuitry to generate any necessary programming voltage from the system's normal supply voltage. designers may implement a JTAG-controlled programming subsystem for non-JTAG devices such as flash memory and microcontrollers. and communicate with the programmer via a serial protocol. making it feasible to apply code or design changes in the middle of a production run. EMBEDDED C PROGRAMMING: High-level language programming has long been in use for embedded-systems development.• • ISP PROGRAMMER EMDEDDED C PROGRAMMING IN-SYSTEM PROGRAMMER It is the ability of some programmable logic devices. In systems complex enough to require moderately large glue logic.

it is a C language extension that is the subject of a technical report by the ISO working group named "Extensions for the Programming Language C to Support Embedded Processors" [3]. Unlike a conventional Load-Store (RISC) architecture. Address registers are taken out of the general-purpose register file and placed next to the memory units in a separate register file. Its goal is to allow easy porting of device-driver code between systems. DSPs have a highly specialized architecture to achieve the performance requirements for signal processing applications within the limits of cost and power consumption set for consumer applications. It aims to provide portability and access to common performance-increasing features of processors used in the domain of DSP and embedded processing. This coupling of performance to end-user features is characteristic of many of the real-time applications in which DSP processors are applied. and named registers gives the programmer direct access to features in the target processor. The key motivation for this practice is performance. The hardware I/O extension is a portability feature of Embedded C. thereby significantly improving the performance of applications. If the video decoding takes 80 percent of the CPU-cycle budget instead of 90 percent. DSPs are often programmed in assembly language by programmers who know the processor architecture inside out. there are twice as many cycles available for audio processing. A further specialization of the data path is the coupling of multiplication and addition to form a single cycle Multiply-accumulate unit (MAC). despite the disadvantages of assembly programming when compared to high-level language programming. DSPs have a data path with memory-access units that directly feed into the arithmetic units. It is combined with 74 . Embedded C is not part of the C language as such. Rather. The Embedded C specification for fixed-point.processor (DSP) based systems. for instance. In this article. named address spaces. we focus on the performance-improving features of Embedded C.

In certain markets. Current state-of-the-art embedded applications (mobile phones. and display management. either by hand or with compilers. but are not good at exploiting the special features that DSP processors have in place. multiple protocol stacks are implemented to be compatible with multiple service providers. Modern compilers can deal with none orthogonally reasonably well. Manual assembly programming is awkward because of the none orthogonally of the architecture and arbitrary restrictions that can be in place. DSP architectures are not easy to program optimally. One processor is a low-power RISC processor that takes care of all control processing. the signal-processing algorithms required become increasingly complex. Limits are often placed on the extent of memory-addressing operations. The localization of resources in the data path saves many data movements that typically take place in Load-Store architecture. user interaction.special-purpose accumulator registers. It is programmed in a high-level language using an SDK that includes a compiler. Staying with the mobile phone as an example. The other processor is a DSP. Communication protocols become more sophisticated and require much more code to implement. Fixed-point arithmetic can be implemented with little additional cost over integer arithmetic. Data memory is segmented and placed close to the MAC to achieve the high bandwidths required to keep up with the streamlined data path. which takes care of all of the signal processing. The most important. The signal-processing algorithms are typically hand-coded in assembly. Features such as stronger error correction and encryption must be added. In 75 . Changes in technological and economic requirements make it more expensive to continue programming DSPs in assembly. common arithmetic extension to DSP architectures is the handling of saturated fixed-point operations by the arithmetic unit. Automatic saturation (or clipping) significantly reduces the number of control-flow instructions needed for checking overflow explicitly in the program. which are separate from the general-purpose registers. for example) are implemented using two processors.

The key reason for this is that although the architecture is well matched to the requirements of the signal-processing application. assembly programs are non portable. and is driven by new features and fashion. Instead of using a primitive. programming DSPs is still done in assembly for the signal processing parts or. On the economic side. at best. Assembly programming has no place in this world. Despite this. most embedded processors are offered with C compilers. time-to-market for new technology puts increasing pressure on design time. the time-to-replacement for mobile phones is between one and two years.addition. the operation is spread over a number of statements that are difficult to recognize as a single primitive by a compiler. In the western world. there is no such primitive in Standard C. However. conditional statements. by using assembly-written libraries supplied by manufacturers. To express saturated arithmetic in C requires comparisons. For example. Today. and correcting assignments. These dependencies make a company vulnerable to employee and supplier chain changes. When assembly code is used. this lack of abstraction becomes a design restriction that impacts not only the interface to the assembly code but often the application as a whole. the number of mobile phones sold worldwide is in the order of 500 million. Saturated arithmetic. In 2004. Assembly code has limited support for data types and generally no support for data structures. Legacy code makes it extremely expensive to switch to a new technology. backward compatibility with older protocols is needed to stay synchronized with provider networks that are in a slow process of upgrading. is required in many algorithms and is supplied as a primitive in many DSPs. there is no way to express the algorithms efficiently and in a natural way in Standard C. Assembly programs are difficult to maintain and make a company dependent on a few specialists. By definition. DESIGN WINDOW OF AVRSTUDIO4 76 .

1 Design Window of AVRSTUDIO4 77 .Fig 9.

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