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Fainan A. Magueed Jan Svensson

Dept. of Energy and Environment ABB Power Technologies

Chalmers University of Technology SE-721 64 Västerås, Sweden

SE-412 96 Gothenburg, Sweden jan.r.svensson@se.abb.com

fainan.magueed@chalmers.se

Abstract— Grid-connected voltage source converters (VSCs) are the VSC because of overcurrent, in order to protect the IGBTs.

the heart of many applications with power quality concerns due Moreover, most faults are unbalanced and result in unbalanced

to their reactive power controllability. However, the major voltage dips, which produce current harmonics and unbalance

drawback is their sensitivity to grid disturbances. Moreover, that also cause current protection to trip.

when VSCs are used in DG applications, voltage unbalance may

be intolerant. The current protection may trip due to current Many controllers have been developed to deal with grid

unbalance or due to overcurrent. In this paper, a vector current voltage unbalance for a VSC system connected to the grid

controller for VSC connected to the grid through LCL-filter is through L-filter [5] - [8]. In [9], LCL-filter is considered along

developed with the main focus on producing symmetrical and with grid voltage unbalance. Moreover, a dual controller, that

balanced currents in case of unbalanced voltage dips. comprises one controller in the positive and one controller in

Implementing this controller helps the VSC system not to trip the negative sequence frame, has been implemented. The

during voltage dips. reference negative sequence currents are set to zero. One case

of voltage unbalance has been discussed showing the response

Keywords- DG, LCL-filter, power quality, VSC, vector current only in the grid current.

control, voltage dips.

In this paper, a vector current controller for VSC connected

I. INTRODUCTION to the grid through LCL-filter is developed with the main focus

on reducing current unbalance in case of different unbalanced

Voltage source converters (VSCs) are now widely used in voltage dips. The idea of implementing the controller in

many grid-connected applications including STATCOMs, positive synchronous reference frame with feed-forward of

UPFCs, DVRs and as active interfaces for distributed negative voltage (first introduced in [7]) is adopted and

generation (DG) systems (for instance photovoltaics, wind, fuel modified for the system with LCL-filter. The performance of

cells and microturbines). Benefits of using a VSC are this controller is compared with a dual vector controller (DVC)

sinusoidal grid currents and high controllability of both active regarding the VSC side current unbalance and the grid side

and reactive power. To make the VSC operating towards the current unbalance. This comparison is done by calculating the

grid, an inductor is needed in each phase to limit and to control amount of unbalance, which is the ratio of negative sequence to

the currents. For DG systems, the output voltage of the grid- positive sequence components, for each current and for

connected VSC needs often to be stepped up to the distribution different types of unbalanced voltage dips at the grid.

level. Therefore, a step-up transformer should be used and the

leakage inductance of the transformer will be equivalent to the

II. SYSTEM DESCRIPTION

needed series inductance. However, high frequency current

harmonics are generated due to PWM switching of the VSC, A scheme of the investigated system is shown in Fig. 1.

which may affect the EMC sensitive loads connected to the The VSC of rated power 69 kVA is connected to 400 V grid

same bus. The isolation of transformers is sensitive to high via LCL-filter, which has the parameters provided in Table I.

dv/dt. Therefore, the VSC voltages should be filtered. This can The inductor on the grid side represents the leakage inductance

be done by inserting a reactor (inductor) towards the VSC and of the transformer needed to match the grid requirement. Its

shunt-connected capacitors between the reactor and the inductance value is a ratio of the inductance at the VSC side.

transformer. Hence, LCL-filters are utilized to interface the The ratio is higher than one in order to limit the high frequency

VSC to the grid, which have the potential of improved grid harmonics in the VSC current. The choice of the LCL-filter

current harmonics [1]-[4]. parameters depends on the system rating. The criterion that is

described in [4] and [10] has been used to choose the

The major drawback of using VSC is its sensitivity to parameters. In this paper, the DC side has been assumed to

voltage disturbances, e.g. voltage dips. A voltage dip is a short have a constant DC voltage equal to 650 V. This assumption is

duration drop in voltage that is normally due to a fault. For a reasonable if the DC capacitance Cdc is high [2].

VSC, a sudden decrease in grid voltage normally causes an

increase in the current, as the control attempts at maintaining

the power to the DC link constant. This can lead to tripping of

The LCL-filter is described in the instantaneous time TABLE I. LCL FILTER PARAMETERS (BASE IMPEDANCE IS ZBASE =2.3Ω).

domain and with single-phase notation, using KVL in the outer Parameter Description pu

loop and KCL at the capacitor connection bus, as follows: L1 VSC side inductance 0.071

R1 VSC side inductor

0.1 L1

di1 − R1 1 1 resistance

= i1 − uc + u (1) L2 Grid side inductance 0.027

dt L1 L1 L1 R2 Grid side inductor

0.1 L2

resistance

di2 − R2 1 1 Cf Filter capacitance 0.1

= i2 + uc − e (2)

dt L2 L2 L2

u => i2

duc 1 1

80

= i1 − i2 (3)

dt Cf Cf 60

where 40

Gain [dB]

0

uc is the capacitor phase voltage;

u is the VSC phase voltage; −20

the VSC voltage to the grid current is calculated and shown in

Fig. 2. The figure shows that the LCL-filter has harmonic −80

peak equal to 1.1 kHz, thus eliminating the PWM switching −100

10

1 2

10

3

10

4

10

current harmonics. The switching frequency is set to 2.5 kHz. frequency [Hz]

The drawback of the LCL-filter is its peak gain at the

resonance frequency, which implies an oscillatory behavior and Figure 2. LCL-filter frequency response from VSC voltage to grid current.

consequently controller instability. Hence, this resonant peak

should be damped actively within the controller.

III. CONTROLLER DESCRIPTION

R2 L2

i2 i1 R1 L1

ua (t )

VSC iv (t ) A. Basic controller

ea (t ) ~+

+ The basic controller block diagram is shown in Fig. 1. The

ic ub (t) ~ three-phase grid currents and voltages, VSC currents and

eb (t ) ~+ Cdc udc(t) voltages, and capacitor three phase voltages, are all measured

ucc(t ) = and sampled with 5 kHz sampling frequency. All signals are

ec (t ) ~+

then transformed into vectors in the fixed αβ-frame and then in

+ SWabc the rotating dq-frame synchronized with the grid voltage. This

uc(t) Cf

PWM is done by using the transformation angle θ obtained by using a

PLL, which is assumed here to be slow and not to react on

voltage dips. To increase the stability limits and in the same

S&H and coordinate transformation time damping oscillations at resonant frequency, three

i1dq Transformation cascaded controllers are applied [13]. The outer controller (PI1)

u cdq to three-phase tracks the reference grid current vector i*2dq and the output is

edq i 2dq Smith

predictor the reference capacitor voltage vector u*cdq , which is the

iˆ1dq reference for the second controller (P2). In P2 the measured

P2 P3 capacitor voltage vector ucdq is compared with the reference

PI1 u*dq

(kp1, ki) (kp2) (kp3) command using a proportional controller, which produces the

* * for the third controller (P3).

reference VSC current vector i1dq

u*cdq i1dq

i*2dq

The third controller is also a proportional controller, which

Figure 1. Power circuit along with main controller blocks.

outputs the reference voltage vector u*dq . The equations

describing the cascaded controller in the dq-frame in the

discrete time domain are:

u*cdq ( k ) = edq ( k ) + ( R2 + jω L2 ) i 2dq ( k ) response considering the overshoot, the rise time and the

(4) damping at the resonance frequency.

( )

+ kp1 i*2dq ( k ) − i 2dq ( k ) + ∆u idq ( k )

TABLE II. LCL-CONTROLLER PARAMETERS.

*

i1dq ( k ) = i 2dq ( k ) + jω Cf u cdq ( k ) k1 1

(5) k2 1

(

+ kp2 u*cdq ( k ) − u cdq ( k ) ) k3

Ti

0.2

0.01 s

kps 0.07

where k is a sampling instant, edq is the grid voltage vector in

dq-frame, ∆uidq is the integration part that eliminates steady B. Performance in case of grid voltage unbalance

state errors and finally ω is the angular frequency of the grid To be able to analyze the grid voltage unbalance, the

voltage. The integration part is calculated using the following decomposition of the voltage vector into positive and negative-

equation: sequence is needed. This is performed in a dqp-frame with the

technique proposed in [8], which originates from [15]. By

(

∆u idq ( k + 1) = ∆u idq ( k ) + ki i*2dq ( k ) − i 2dq ( k ) ) (6) delaying the voltage vector by one fourth of the grid cycle T, a

vector composed of the same positive sequence component and

where ki = kp1Ts /Ti , Ti and Ts are the integral time constant and a negative sequence component with equal amplitude and

the sampling time respectively. The reference voltage is then opposite sign is obtained. Therefore, if this vector is added to

generated as: the measured supply voltage vector, the negative sequence

voltage will be removed. The positive sequence voltage

component can, thus, be extracted from the measured values as

u*dq ( k + 1) = u cdq ( k ) + ( R1 + jω L1 ) i1dq ( k )

(7)

(

*

+ kp3 i1dq ( k ) − iˆ1dq ( k − 1) ) e dqp (t ) = 1

2

(e dq (t ) + e dqp (t − T 4)) (10)

The controller constants kp1, kp2, and kp3 are fractions of the The negative sequence, in dqp-frame, can be calculated as

corresponding dead-beat gains, kDB1, kDB2, and kDB3, as

e dqn ( p ) (t ) = 1

2

(e dq (t ) − e dqp (t − T 4)) (11)

L R

kp1 = k1kDB1 = k1 2 + 2 The latter will be seen as a constant signal in the negative

Ts 2

rotating plane dqn, which utilizes the opposite angle for the dq-

C (8) transformation. This technique is applied to the current vectors

kp2 = k2 kDB2 = k2 f

Ts

as well, to be able to look at positive and negative sequence

currents resulting due to the voltage imbalance.

L R

kp3 = k3 kDB3 = k3 1 + 1

Ts 2 The voltage imbalance due to unbalanced voltage dips is

considered here. Three different dips are applied; one is due to

To compensate for the time delay due to the calculation a single phase fault, another is due to double phase fault, and

time, Smith predictor is used [14], which attempts to remove the third is due to double phase to ground fault. The phasor

the effect of the delay time from the closed loop control system diagram of voltage dips resulting from the three different faults

so that the controller can be designed as if no time delay was is shown in Fig. 3. The dip magnitude Edip, which is the

present. Hence, the Smith predictor is implemented in a way magnitude of the remaining voltage during the dip, is chosen

analogous to a state observer, which means running a model of such that all dips have the same positive sequence component.

the plant parallel to the plant itself. The predicted current The active current reference is chosen to be 1 pu while the

equation is then calculated in the dq-frame as: reactive current reference is set to zero to produce unity power

factor at the grid side. The resulting positive sequence current

R

T

L1

( )

iˆ1dq ( k + 1) = s u*dq ( k ) − u cdq ( k ) + 1 − 1 − jω Ts iˆ1dq ( k )

L1 (9)

is shown in Fig. 4. This current is the same for all dips apart

from the transients at the start and the end of the dip. This

transient time is produced mainly due to the delay introduced

ps ( 1dq

+ k i ( k ) − iˆ ( k − 1)1dq ) by the sequence detection algorithm.

where kps is the observer gain that compensates for the error E3=E3,dip E3 E3

between the actual and the predicted currents.

E3,dip E3,dip

Theoretically, choosing dead-beat gains for the controller E1, dip E1 E1=E1,dip E1=E1,dip

should result in fast transient response. However, this is not E2,dip

possible in cascaded controllers, since the operation of the E2,dip

controllers should be decoupled. To choose the proper gains,

E2=E2,dip E2 E2

the stability of the complete system has been examined looking (a) (b) (c)

at the pole location on the unit disc [13]. The controller

Figure 3. Voltage dips due to (a) single phase fault, (b) double phase fault,

parameters stated in Table II are chosen to produce an adequate and (c) double phase to ground fault.

A dip due to a single phase fault with 10 % remaining 2

voltage has been applied at 0.2 s for duration of 0.1 s, as shown 1

d−component

and grid sides, in dq-frame will be as shown in Fig. 6. The 0

[12], given by −2

0.15 0.2 0.25 0.3 0.35

2 2

i2dn + i2qn 2

ri = ×100 (12) d−component

2 2

i2dp + i2qp 1

is 132 % in this case. For a dip due to double phase fault with 0

q−component

40% remaining voltage, shown in Fig. 7, ri = 89 %. In this case, −1

the negative sequence currents are shown in Fig. 8. For the last

case, which is a dip due to double phase to ground fault, −2

0.15 0.2 0.25 0.3 0.35

ri = 69 %. The voltage and negative sequence current are Time [s]

shown in Fig. 9 and Fig. 10, respectively.

Figure 6. Negative sequence of VSC current (upper) and grid current

2 (lower): 10 % voltage dip due to single phase fault.

Converter current [p.u.]

1.5

d−component

1 1

0.5 0.8

q−component

0 0.6

−0.5 0.4

0.15 0.2 0.25 0.3 0.35

Grid voltage [p.u.]

0.2

2

0

Grid current [p.u.]

1.5 d−component

−0.2

1

−0.4

0.5 q−component −0.6

0

−0.8

−0.5

0.15 0.2 0.25 0.3 0.35 −1

Time [s]

0.15 0.2 0.25 0.3 0.35

Figure 4. Positive sequence VSC current (upper) and grid current (lower) in Time [s]

dq-frame.

Figure 7. Grid voltage: 40 % voltage dip due to double phase fault.

2

Converter current [p.u.]

1

d−component

1

0.8

0.6 0

0.4

Grid voltage [p.u.]

−1

q−component

0.2

−2

0 0.15 0.2 0.25 0.3 0.35

−0.2

2

−0.4

d−component

Grid current [p.u.]

1

−0.6

−0.8 0

−1

−1 q−component

−2

Time [s] 0.15 0.2 0.25 0.3 0.35

Time [s]

Figure 5. Grid voltage: 10 % voltage dip due to single phase fault.

Figure 8. Negative sequence of VSC current (upper) and grid current

(lower): 40 % voltage dip due to double phase fault.

d − R2 1 1

i = i − jωi 2dq + u − e (14)

1

dt 2dq L2 2dq L2 cdq L2 dq

0.8

0.6 d 1 1 (15)

u cdq = i1dq − i + jωu cdq

0.4 dt Cf Cf 2dq

Grid voltage [p.u.]

0.2

In steady state and dqn-frame, the foregoing equations are

0 read as follows:

−0.2

− R1 1 1

−0.4 i + jωi1dqn − u cdqn + u dqn = 0 (16)

L1 1dqn L1 L1

−0.6

−0.8

− R2 1 1

i + jωi 2dqn − u + e =0 (17)

−1

L2 2dqn L2 cdqn L2 dqn

0.15 0.2 0.25 0.3 0.35

Time [s] 1 1 (18)

i − i − jωu cdqn = 0

Cf 1dqn Cf 2dqn

Figure 9. Grid voltage: 55 % voltage dip due to double phase to ground

fault.

For the grid currents to be symmetrical, the negative

2 sequence components in dq-frame should be nullified; i.e.

Converter current [p.u.]

1 d−component

VSC voltage vector described in (7). Substituting with i2dqn=0

in (18) and using the result in (16) yields

0

−1 q−component

( )

u*dqn = u cdqn 1 + ω2 Cf L1 + jR1ωCf u cdqn (19)

−2

0.15 0.2 0.25 0.3 0.35

This is implemented using positive sequence grid and

capacitor voltage vectors within the controller equations and

2

the negative sequence capacitor voltage vector is fed-forward

to calculate the negative part of the VSC reference voltage

Grid current [p.u.]

d−component

1

vector, as suggested in Fig. 11.

0

iˆ1dq

−1

q−component

−2 i1dq

0.15 0.2 0.25 0.3 0.35

Time [s] u dqp

P3

Figure 10. Negative sequence of VSC current (upper) and grid current

(lower): 55 % voltage dip due to double phase to ground fault.

u*cdq

i 2dq P2 dqp

*

IV. PROPOSED CONTROLLER FOR BALANCED CURRENTS i1dq

i*2dq

PI1

A. One controller in the positive sequence frame with feed edq

forward for the negative sequence (NSFF)

u cdqp

Since the main interest of the controller is to deal with u*dq

u cdqn (19) dqn

dqn- frames) to derive relevant control laws. The dqp-frame is Figure 11. Schematic diagram for the controller for balanced currents.

synchronized with the grid voltage with the same direction of

rotation, while dqn-frame rotates in the opposite direction. However, recalculating (19) with the specified filter

parameters, yields

The LCL-filter equations (1) to (3), is described in the dqp-

frame as follows:

u *dqn ≈ u cdqn (20)

d R 1 1

i = − jωi1dq − 1 i1dq − u cdq + u dq (13) which is the condition for balanced converter currents. With

dt 1dq L1 L1 L1

this algorithm, the VSC currents are forced to be balanced,

which reduces the ratio of imbalance in the grid currents.

Moreover, substituting i1dqn = 0 and i2dqn = 0 in (17) results 1

in u*cdqn = edqn and in (18) results in u*cdqn = 0 . Since these 0.5

achieve symmetrical grid and VSC currents simultaneously.

−0.5

B. Dual vector controller (DVC)

The controller equations (4) to (9) can be described in dqp- −1

0.15 0.2 0.25 0.3 0.35

frame and dqn-frame, and then two parallel controllers, one for

each frame, can be implemented as shown in Fig. 12 [8]. To 1

unbalance, the reference negative sequence currents are set to 0.5

since there is no direct access to the VSC current reference.

−0.5

−1

i*2dqp (k )

0.15 0.2 0.25 0.3 0.35

Time [s]

Positive Figure 13. Negative sequence of VSC current (upper) and grid current

i 2dqp (k )

sequence u* (k )

vector dqp dqp (lower): NSFF and 10 % voltage dip due to single phase to ground fault.

i1dqp (k )

current 1.5

u cdqp (k ) controller

1

edqp (k ) 0.5

u*áâ (k ) 2

*

uabc (k )

+

0

3 −0.5

i*2dqn (k )

−1

i 2dqn (k ) Negative

u*dqn (k ) dqn

−1.5

sequence 0.15 0.2 0.25 0.3 0.35

i1dqn (k ) vector

current

u cdqn (k ) controller 1.5

Grid currents [p.u.]

1

edqn (k )

0.5

0

Figure 12. Dual vector controller.

−0.5

−1

C. Results −1.5

0.15 0.2 0.25 0.3 0.35

The first proposed controller, to achieve balanced currents Time [s]

in case of grid voltage unbalance, using the feed forward of the

negative sequence capacitor voltage (NSFF) is tested in case of Figure 14. VSC current phasors (upper) and grid current phasors (lower)

balanced current control.

unbalanced voltage dips. The VSC negative sequence current is

nullified, for the three introduced different voltage dips, while 1

Converter current [p.u.]

This is shown for the dip due to single phase fault, since it

produces the most amount of imbalance, in Fig. 13. This 0

when applying the current balancing algorithm. The three

−0.5

phase VSC and grid currents are also shown in Fig. 14. When −1

the dual controller, DVC, is implemented with the same

0.15 0.2 0.25 0.3 0.35

VSC currents is as shown in Fig. 15. The negative sequence of 1

the grid current is nullified during the dip, while the negative

Grid current [p.u.]

0.5

sequence of the VSC current is reduced to less that 5 %.

0

−0.5

−1

0.15 0.2 0.25 0.3 0.35

Time [s]

Figure 15. Negative sequence of VSC current (upper) and grid current

(lower): DVC and 10 % voltage dip due to single phase to ground fault.

V. CONCLUSIONS [5] H. Song. K. Nam, “Dual Current Control Scheme for PWM Converter

under Unbalanced Input Voltage Conditions,” IEEE Trans. on Industrial

A vector current controller for VSC connected to the grid Electronics, vol.46, pp. 953-959, October 1999.

through LCL-filter is developed with the main focus on [6] Y.Suh, V. Tijeras, T. A. Lipo, “A Nonlinear Control of the

reducing current imbalance in case of unbalanced voltage dips Instantaneous Power in dq Synchronous Frame for PWM AC/DC

at the grid. The controller is applied in the positive sequence Converter Under Generalized Unbalanced Operating Conditions,” in

Proc. IEEE Industry Applications Society Annual Meeting 2002, vol. 2,

frame and the negative sequence capacitor voltage vector is pp. 1189-1196.

fed-forward with relevant relations that are derived here.

[7] H.S. Kim, H.S. Mok, G.H. Choe, D.S. Hyun, S.Y. Choe, “Design of

Implementing this controller the currents on the VSC side are Current Controller for Three-Phase PWM Converter with Unbalanced

symmetrical while the amount of imbalance in the current on Input Voltage,” in Proc. of IEEE 29th Annual Power Electronics

the grid side is reduced from 132 % to 5 % in case of a voltage Specialists Conference (PESC’98), pp. 503-509.

dip due to a single phase fault with 10 % remaining voltage. [8] G. Saccomando, J. Svensson, “Transient Operation of Grid Connected

The controller has been tested also for dips due to double phase Voltage Source Converter Under Unbalanced Voltage Conditions,” in

fault and double phase to ground fault. The grid currents are Proc. of IEEE Industry Applications Society Annual Meeting 2001, vol.

4, pp. 2419–2424.

almost symmetrical during the different voltage dips, which

[9] E. J. Bueno, F. Espinosa, F. J. Rodriguez, J. Urena, and S. Cobreces,

results in protecting the VSC from tripping due to overcurrents “Current Control of Voltage Source Converters Connected to the Grid

or current imbalance during the dip period. This controller has Through an LCL-filter,” 35th Annual IEEE Power Electronics Specialists

been compared with a dual vector controller (DVC) that is Conference PESC’ 2004, pp 68-73.

composed of two controllers; one is implemented in the [10] M. Liserre, F. Blaabjerg, and S. Hansen, “Design and Control of an

positive sequence frame and the other is implemented in the LCL-filter Based Three-phase Active Rectifier,” 36th Industry

negative sequence frame. The DVC has been tested with the Applications Conference (IAS’01), 30th Sept.-4th Oct 2001, vol.1, pp.299

– 307.

same cases of grid voltage imbalance. The resulting grid side

[11] R. Ottersten, J. Svensson, “Vector Current Controlled Voltage Source

current is balanced while the VSC side current has an amount Converter- Deadbeat Control and Saturation Strategies,” IEEE Trans. on

of imbalance of less than 5 %. Power Electronics, vol. 17, no. 2, March 2002, pp. 279- 285.

[12] M.H.J. Bollen, Understanding power quality problems: voltage sags and

REFERENCES interruptions, New York, IEEE Press, 1999.

[13] F. A. Magueed, J. Svensson, and A. Sannino, “Transient Performance of

[1] F. Blaabjerg, E. Chiarantoni, A. Dell’Aquila, M. Liserre, and S.

Voltage Source Converter Connected to Grid through LCL-Filter under

Vergura, “Analysis of the Grid Side Behavior of a LCL-Filter Based

Unbalanced Voltage conditions,” accepted to be presented in Proc of

Three-Phase Active Rectifier,” IEEE International Symposium on

Power Tech Conference (PT’05), St. Petersburg, Russia, 27-30th June

Industrial Electronics (ISIE '03), 9-11 June 2003, pp. 775 – 780.

2005.

[2] E. Twining, D.G. Holmes, “Grid current regulation of a three-phase

[14] K. Dutton, S. Thompson, B. Barraclough, The Art of Control

voltage source inverter with an LCL input filter,” Power Electronics

Engineering, Addison-Wesley Longman, 1997.

Specialists Conference (PESC 02), vol. 3, 23-27 June, pp.1189 – 1194.

[15] T.-N. Le, “Kompensation schnell veränderlicher Blindströme eines

[3] Michael Lindgren, Modeling and Control of Voltage Source Converters

Drehstromverbrauchers,” etzArchiv, Bd. 11, (1989), H. 8, pp. 249-253,

Connected to the Grid, PhD Thesis, Chalmers University of Technology,

(in German).

Gothenburg, Sweden, November 1998, ISBN 91-7197-710-4.

[4] Martin Bojrup, Advanced Control of Active Filters in a Battery Charger

Application, Lic.Tech. thesis, Lund University, Sweden 1999, ISBN 91-

88934-13-6.

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