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Fainan A. Magueed

Dept. of Energy and Environment Chalmers University of Technology SE-412 96 Gothenburg, Sweden fainan.magueed@chalmers.se

Abstract— Grid-connected voltage source converters (VSCs) are the heart of many applications with power quality concerns due to their reactive power controllability. However, the major drawback is their sensitivity to grid disturbances. Moreover, when VSCs are used in DG applications, voltage unbalance may be intolerant. The current protection may trip due to current unbalance or due to overcurrent. In this paper, a vector current controller for VSC connected to the grid through LCL-filter is developed with the main focus on producing symmetrical and balanced currents in case of unbalanced voltage dips. Implementing this controller helps the VSC system not to trip during voltage dips. Keywords- DG, LCL-filter, power quality, VSC, vector current control, voltage dips.

Jan Svensson

ABB Power Technologies SE-721 64 Västerås, Sweden jan.r.svensson@se.abb.com

the VSC because of overcurrent, in order to protect the IGBTs. Moreover, most faults are unbalanced and result in unbalanced voltage dips, which produce current harmonics and unbalance that also cause current protection to trip. Many controllers have been developed to deal with grid voltage unbalance for a VSC system connected to the grid through L-filter [5] - [8]. In [9], LCL-filter is considered along with grid voltage unbalance. Moreover, a dual controller, that comprises one controller in the positive and one controller in the negative sequence frame, has been implemented. The reference negative sequence currents are set to zero. One case of voltage unbalance has been discussed showing the response only in the grid current. In this paper, a vector current controller for VSC connected to the grid through LCL-filter is developed with the main focus on reducing current unbalance in case of different unbalanced voltage dips. The idea of implementing the controller in positive synchronous reference frame with feed-forward of negative voltage (first introduced in [7]) is adopted and modified for the system with LCL-filter. The performance of this controller is compared with a dual vector controller (DVC) regarding the VSC side current unbalance and the grid side current unbalance. This comparison is done by calculating the amount of unbalance, which is the ratio of negative sequence to positive sequence components, for each current and for different types of unbalanced voltage dips at the grid. II. SYSTEM DESCRIPTION

I.

INTRODUCTION

Voltage source converters (VSCs) are now widely used in many grid-connected applications including STATCOMs, UPFCs, DVRs and as active interfaces for distributed generation (DG) systems (for instance photovoltaics, wind, fuel cells and microturbines). Benefits of using a VSC are sinusoidal grid currents and high controllability of both active and reactive power. To make the VSC operating towards the grid, an inductor is needed in each phase to limit and to control the currents. For DG systems, the output voltage of the gridconnected VSC needs often to be stepped up to the distribution level. Therefore, a step-up transformer should be used and the leakage inductance of the transformer will be equivalent to the needed series inductance. However, high frequency current harmonics are generated due to PWM switching of the VSC, which may affect the EMC sensitive loads connected to the same bus. The isolation of transformers is sensitive to high dv/dt. Therefore, the VSC voltages should be filtered. This can be done by inserting a reactor (inductor) towards the VSC and shunt-connected capacitors between the reactor and the transformer. Hence, LCL-filters are utilized to interface the VSC to the grid, which have the potential of improved grid current harmonics [1]-[4]. The major drawback of using VSC is its sensitivity to voltage disturbances, e.g. voltage dips. A voltage dip is a short duration drop in voltage that is normally due to a fault. For a VSC, a sudden decrease in grid voltage normally causes an increase in the current, as the control attempts at maintaining the power to the DC link constant. This can lead to tripping of

A scheme of the investigated system is shown in Fig. 1. The VSC of rated power 69 kVA is connected to 400 V grid via LCL-filter, which has the parameters provided in Table I. The inductor on the grid side represents the leakage inductance of the transformer needed to match the grid requirement. Its inductance value is a ratio of the inductance at the VSC side. The ratio is higher than one in order to limit the high frequency harmonics in the VSC current. The choice of the LCL-filter parameters depends on the system rating. The criterion that is described in [4] and [10] has been used to choose the parameters. In this paper, the DC side has been assumed to have a constant DC voltage equal to 650 V. This assumption is reasonable if the DC capacitance Cdc is high [2].

IAS 2005

572

0-7803-9208-6/05/$20.00 © 2005 IEEE

thus eliminating the PWM switching current harmonics. uc is the capacitor phase voltage. IAS 2005 573 0-7803-9208-6/05/$20. which is assumed here to be slow and not to react on voltage dips. To increase the stability limits and in the same time damping oscillations at resonant frequency. III. as follows: di1 − R1 1 1 i1 − uc + u = dt L1 L1 L1 di2 − R2 1 1 = i2 + uc − e dt L2 L2 L2 TABLE I.~+ ec (t ) . The figure shows that the LCL-filter has harmonic attenuation of 60 dB/decade at frequencies above the resonance peak equal to 1. e is the grid phase voltage. VSC currents and voltages.The LCL-filter is described in the instantaneous time domain and with single-phase notation.1 u => i2 duc 1 1 = i1 − i2 dt Cf Cf 60 where 40 i1 is the phase current on the VSC side.3Ω). The third controller is also a proportional controller. LCL-filter frequency response from VSC voltage to grid current. which is the cdq reference for the second controller (P2).1 L2 0.~+ eb (t ) . Using the foregoing equations. The switching frequency is set to 2.071 0. Basic controller The basic controller block diagram is shown in Fig. and capacitor three phase voltages. which produces the * reference VSC current vector i1dq for the third controller (P3). which implies an oscillatory behavior and consequently controller instability. are all measured and sampled with 5 kHz sampling frequency. CONTROLLER DESCRIPTION R2 L2 i2 ic i1 R1 L1 ua (t ) ub (t) ucc(t ) VSC iv (t ) ~ = Cdc + udc(t) SWabc Cf PWM S&H and coordinate transformation i1dq edq i 2dq u cdq Transformation to three-phase Smith predictor ˆ i 1dq A.5 kHz. The outer controller (PI1) tracks the reference grid current vector i* and the output is 2dq the reference capacitor voltage vector u* . the frequency response from the VSC voltage to the grid current is calculated and shown in Fig.00 © 2005 IEEE . Parameter L1 R1 L2 R2 Cf (1) (2) (3) 80 Description VSC side inductance VSC side inductor resistance Grid side inductance Grid side inductor resistance Filter capacitance pu 0. Hence. using KVL in the outer loop and KCL at the capacitor connection bus. u is the VSC phase voltage. 1. ea (t ) . 2. i2 is the phase current on the grid side. ki) i* 2dq u* cdq P2 (kp2) P3 (kp3) * i1dq u* dq Figure 1.1 kHz. The three-phase grid currents and voltages. In P2 the measured capacitor voltage vector ucdq is compared with the reference command using a proportional controller. The drawback of the LCL-filter is its peak gain at the resonance frequency.027 0. Power circuit along with main controller blocks. The equations dq describing the cascaded controller in the dq-frame in the discrete time domain are: PI1 (kp1. All signals are then transformed into vectors in the fixed αβ-frame and then in the rotating dq-frame synchronized with the grid voltage. three cascaded controllers are applied [13]. This is done by using the transformation angle θ obtained by using a PLL.1 L1 0.~+ + uc(t) - 20 Gain [dB] 0 −20 −40 −60 −80 −100 1 10 10 2 10 3 10 4 frequency [Hz] Figure 2. this resonant peak should be damped actively within the controller. LCL FILTER PARAMETERS (BASE IMPEDANCE IS ZBASE =2. which outputs the reference voltage vector u* .

The integration part is calculated using the following equation: ∆u idq ( k + 1) = ∆u idq ( k ) + ki i* ( k ) − i 2dq ( k ) 2dq ( ) (6) where ki = kp1Ts /Ti . a vector composed of the same positive sequence component and a negative sequence component with equal amplitude and opposite sign is obtained. if this vector is added to the measured supply voltage vector. the stability of the complete system has been examined looking at the pole location on the unit disc [13].dip E3. choosing dead-beat gains for the controller should result in fast transient response.u* ( k ) = edq ( k ) + ( R2 + jω L2 ) i 2dq ( k ) cdq + kp1 i* ( k ) − i 2dq ( k ) + ∆u idq ( k ) 2dq * i1dq ( ) (4) response considering the overshoot. 3. Ti and Ts are the integral time constant and the sampling time respectively. which utilizes the opposite angle for the dqtransformation. 4. this is not possible in cascaded controllers. By delaying the voltage vector by one fourth of the grid cycle T. The active current reference is chosen to be 1 pu while the reactive current reference is set to zero to produce unity power factor at the grid side.dip E2=E2. be extracted from the measured values as e dqp (t ) = 1 2 ( ) (7) (e dq (t ) + e dqp (t − T 4)) 1 2 (10) The controller constants kp1.dip E2. to be able to look at positive and negative sequence currents resulting due to the voltage imbalance. E3=E3. and (c) double phase to ground fault. which means running a model of the plant parallel to the plant itself. k1 k2 k3 Ti kps 1 1 0. This technique is applied to the current vectors as well. the rise time and the damping at the resonance frequency. thus.2 0. TABLE II.01 s 0. Performance in case of grid voltage unbalance To be able to analyze the grid voltage unbalance. which attempts to remove the effect of the delay time from the closed loop control system so that the controller can be designed as if no time delay was present.dip E2 E1=E1. in dqp-frame. another is due to double phase fault. kDB1. The predicted current equation is then calculated in the dq-frame as: R T ˆ i 1dq ( k + 1) = s u* ( k ) − u cdq ( k ) + 1 − 1 − jω Ts iˆ1dq ( k ) dq L1 (9) L1 ˆ + k i ( k ) − i ( k − 1) ( ) ps ( 1dq 1dq ) where kps is the observer gain that compensates for the error between the actual and the predicted currents. kDB2. which is the magnitude of the remaining voltage during the dip. ∆uidq is the integration part that eliminates steady state errors and finally ω is the angular frequency of the grid voltage. which originates from [15]. This is performed in a dqp-frame with the technique proposed in [8]. Hence. The reference voltage is then generated as: u* ( k + 1) = u cdq ( k ) + ( R1 + jω L1 ) i1dq ( k ) dq * + kp3 i1dq ( k ) − iˆ1dq ( k − 1) B. (b) double phase fault.dip E2. and kDB3.07 ( k ) = i 2dq ( k ) + jω Cf u cdq ( k ) + kp2 u* ( k ) − u cdq ( k ) cdq ( ) (5) where k is a sampling instant. The phasor diagram of voltage dips resulting from the three different faults is shown in Fig. LCL-CONTROLLER PARAMETERS. The voltage imbalance due to unbalanced voltage dips is considered here. dip E1 To compensate for the time delay due to the calculation time. is chosen such that all dips have the same positive sequence component. This transient time is produced mainly due to the delay introduced by the sequence detection algorithm. The dip magnitude Edip. Voltage dips due to (a) single phase fault. the decomposition of the voltage vector into positive and negativesequence is needed. as L R kp1 = k1kDB1 = k1 2 + 2 2 Ts C kp2 = k2 kDB2 = k2 f Ts L R kp3 = k3 kDB3 = k3 1 + 1 2 Ts The negative sequence. the Smith predictor is implemented in a way analogous to a state observer. can be calculated as e dqn ( p ) (t ) = (e dq (t ) − e dqp (t − T 4)) (11) (8) The latter will be seen as a constant signal in the negative rotating plane dqn. and the third is due to double phase to ground fault. IAS 2005 574 0-7803-9208-6/05/$20. Theoretically. This current is the same for all dips apart from the transients at the start and the end of the dip. kp2. edq is the grid voltage vector in dq-frame. The controller parameters stated in Table II are chosen to produce an adequate E3 E3. The resulting positive sequence current is shown in Fig. one is due to a single phase fault. Three different dips are applied. since the operation of the controllers should be decoupled. Therefore. To choose the proper gains.dip E1. and kp3 are fractions of the corresponding dead-beat gains. Smith predictor is used [14].dip E3 E1=E1.00 © 2005 IEEE . However. The positive sequence voltage component can. the negative sequence voltage will be removed.dip (a) E2 (b) (c) Figure 3.

] ri = ×100 (12) 2 d−component 1 is 132 % in this case. The resulting negative sequence currents. which is the ratio of negative sequence to positive sequence components at fundamental frequency [12].4 −0.35 Time [s] −2 0. 10.3 0. ri = 69 %. IAS 2005 575 0-7803-9208-6/05/$20.] 1. Negative sequence of VSC current (upper) and grid current (lower): 10 % voltage dip due to single phase fault.25 0.u.2 0 −0.25 0.2 1 d−component 0 Grid voltage [p.] 0.35 Time [s] Figure 5. 5. Time [s] Figure 7.2 0 −0. which is a dip due to double phase to ground fault.] −1 q−component −2 0.25 0.8 0.6 Grid voltage [p. Grid voltage: 10 % voltage dip due to single phase fault. 7. Figure 8.2 0.25 0.15 0. on the VSC and grid sides.3 0.2 0. d−component 1 q−component 0.2 0.5 0 −0.4 2 Grid current [p.2 0.6 −0.35 Time [s] Figure 6.2 0. in dq-frame will be as shown in Fig.25 0. The amount of imbalance.5 1 0. as shown in Fig. the negative sequence currents are shown in Fig. Positive sequence VSC current (upper) and grid current (lower) in dq-frame.00 © 2005 IEEE . For a dip due to double phase fault with 40% remaining voltage. Converter current [p.3 0.3 0.25 0.35 Grid current [p.5 0. For the last case.15 0 q−component −1 −2 0. In this case.5 0.4 0.15 0.] 2 1.u.35 2 Grid current [p.25 0.8 −1 d−component 1 0 −1 q−component 0.] 2 d−component 1 0 q−component −1 −2 0.2 s for duration of 0.15 0.u. Converter current [p. 9 and Fig.] 2 Grid voltage: 40 % voltage dip due to double phase fault.8 −0. 8.3 0.35 Figure 4.u. shown in Fig.15 0.6 0.u.15 0. ri = 89 %. The voltage and negative sequence current are shown in Fig.2 0.15 0.15 0.1 s.3 0.5 1 0.u.2 0. respectively. 6.5 0 d−component q−component −0.35 0.] −0.A dip due to a single phase fault with 10 % remaining voltage has been applied at 0. given by 2 2 i2dn + i2qn 2 2 i2dp + i2qp Converter current [p.6 −0.3 0.u. 1 0.25 0. Negative sequence of VSC current (upper) and grid current (lower): 40 % voltage dip due to double phase fault.35 −1 Time [s] 0.2 −0.2 0.u.3 0.8 0.4 0.

4 0. yields u * ≈ u cdqn dqn (20) (13) which is the condition for balanced converter currents. the LCL-filter should be described in positive and negative sequence synchronous frames (dqp.35 i1dq u dqp Time [s] P3 Figure 10.8 −1 − R2 d 1 1 i = i − jωi 2dq + u − e dt 2dq L2 2dq L2 cdq L2 dq d 1 1 u cdq = i1dq − i + jωu cdq dt Cf Cf 2dq (14) (15) Grid voltage [p. 11. One controller in the positive sequence frame with feed forward for the negative sequence (NSFF) Since the main interest of the controller is to deal with voltage imbalance.2 0. is described in the dqpframe as follows: R d 1 1 i = − jωi1dq − 1 i1dq − u cdq + u dq dt 1dq L1 L1 L1 (19) dqn ab + + ab u* dq dqp Figure 11.6 −0.] In steady state and dqn-frame.2 −0.8 0. PROPOSED CONTROLLER FOR BALANCED CURRENTS i 2dq i* 2dq edq u cdqp u cdqn u* cdq P2 * i1dq dqp ab PI1 A. which reduces the ratio of imbalance in the grid currents.2 0.] 2 1 1 i − i − jωu cdqn = 0 Cf 1dqn Cf 2dqn 1 d−component 0 For the grid currents to be symmetrical.2 0 −0.u. Schematic diagram for the controller for balanced currents. the foregoing equations are read as follows: − R1 1 1 i + jωi1dqn − u cdqn + u dqn = 0 L1 1dqn L1 L1 − R2 1 1 i + jωi 2dqn − u + e =0 L2 2dqn L2 cdqn L2 dqn 0.and dqn. recalculating (19) with the specified filter parameters.3 0. The LCL-filter equations (1) to (3). With this algorithm.3 0. the negative sequence components in dq-frame should be nullified. IV. i. as suggested in Fig.frames) to derive relevant control laws. IAS 2005 576 0-7803-9208-6/05/$20. However. Negative sequence of VSC current (upper) and grid current (lower): 55 % voltage dip due to double phase to ground fault.25 0. ˆ i 1dq 0 −1 q−component −2 0.15 Time [s] Figure 9.4 −0.] d−component 1 This is implemented using positive sequence grid and capacitor voltage vectors within the controller equations and the negative sequence capacitor voltage vector is fed-forward to calculate the negative part of the VSC reference voltage vector.2 0.35 2 Grid current [p.25 0.u. The dqp-frame is synchronized with the grid voltage with the same direction of rotation. That should be achieved by adjusting the reference VSC voltage vector described in (7). i2dqn=0.6 0.00 © 2005 IEEE . Grid voltage: 55 % voltage dip due to double phase to ground fault.e. Substituting with i2dqn=0 in (18) and using the result in (16) yields u* = u cdqn 1 + ω2 Cf L1 + jR1ωCf u cdqn dqn −1 q−component ( ) (19) −2 0.u. while dqn-frame rotates in the opposite direction.15 0.15 0. Converter current [p.25 0.1 0. the VSC currents are forced to be balanced.3 0.35 (16) (17) (18) 0.

to achieve balanced currents in case of grid voltage unbalance.25 0.25 0. This is shown for the dip due to single phase fault. can be implemented as shown in Fig. DVC.5 −1 i 2dqn (k ) i1dqn (k ) u cdqn (k ) Negative sequence vector current controller u* (k ) dqn dqn ab −1. This amount of unbalance is reduced from 132 % to less than 5 % when applying the current balancing algorithm. since there is no direct access to the VSC current reference.5 −1 0.35 Time [s] Figure 15.3 0. in Fig.35 Time [s] i 2dqp (k ) u cdqp (k ) Converter currents [p.Converter current [p.00 © 2005 IEEE .] edqn (k ) 1 0. When the dual controller. Results The first proposed controller.3 0. is implemented with the same voltage dip.5 Grid current [p.15 0.5 −1 0.] 1 0.3 0.2 0. Negative sequence of VSC current (upper) and grid current (lower): NSFF and 10 % voltage dip due to single phase to ground fault. while the negative sequence grid current is significantly reduced. the reference negative sequence currents are set to zero.25 0.35 1 0.3 0.5 0 Grid current [p. 15.2 0. for the three introduced different voltage dips.35 1 0.15 0. 14.2 0. IAS 2005 577 0-7803-9208-6/05/$20.2 0. The VSC negative sequence current is nullified.u.2 0.5 i* ( k ) 2dqp −1 0.15 0. Negative sequence of VSC current (upper) and grid current (lower): DVC and 10 % voltage dip due to single phase to ground fault. Dual vector controller (DVC) The controller equations (4) to (9) can be described in dqpframe and dqn-frame. it is not possible to achieve symmetrical grid and VSC currents simultaneously.u. the resulting negative sequence in the grid and VSC currents is as shown in Fig. 12 [8]. Since these cdqn cdqn conditions contradict with each other. while the negative sequence of the VSC current is reduced to less that 5 %.5 1 edqp (k ) 0. using the feed forward of the negative sequence capacitor voltage (NSFF) is tested in case of unbalanced voltage dips. 0 −0.3 0.35 1. 1.] C. −0.3 0. and then two parallel controllers.25 0.5 −1 0.5 0 −0.5 0 −0.35 Time [s] Figure 14. The negative sequence of the grid current is nullified during the dip. −1 −1.u. To achieve symmetrical grid currents during grid voltage unbalance.2 0.u.5 0.25 0.u. The three phase VSC and grid currents are also shown in Fig.25 0. since it produces the most amount of imbalance.5 q+Dq i* ( k ) 2dqn + 2 3 0 −0.15 0.5 Grid currents [p.] i1dqp (k ) Positive sequence u* (k ) dqp dqp vector current ab controller u* ( k ) áâ * uabc (k ) Figure 13.5 0 −0.5 Figure 12.] Moreover.5 0. substituting i1dqn = 0 and i2dqn = 0 in (17) results in u* = edqn and in (18) results in u* = 0 . 13.u.15 0. This controller cannot achieve symmetrical VSC current. Dual vector controller. one for each frame. VSC current phasors (upper) and grid current phasors (lower) balanced current control.] B. Converter current [p. 1 0.15 0.

T. 9-11 June 2003. vol.H. [6] [7] [8] [9] [10] [11] [12] [13] [2] [14] [15] [3] H. Tijeras. Vergura. Espinosa. of IEEE 29th Annual Power Electronics Specialists Conference (PESC’98). Hansen. PhD Thesis. F. 953-959.H. pp. The controller has been tested also for dips due to double phase fault and double phase to ground fault. vol. March 2002. E. 8. 249-253. 4. Svensson. pp.” Power Electronics Specialists Conference (PESC 02). J. October 1999.1189 – 1194.-4th Oct 2001. Advanced Control of Active Filters in a Battery Charger Application. 279.Y. New York. This controller has been compared with a dual vector controller (DVC) that is composed of two controllers. G. Ottersten. Chiarantoni. F. Choe. R. and S. D. F. “Dual Current Control Scheme for PWM Converter under Unbalanced Input Voltage Conditions. “Current Control of Voltage Source Converters Connected to the Grid Through an LCL-filter. 23-27 June. 2419–2424. “Kompensation schnell veränderlicher Blindströme eines Drehstromverbrauchers. 503-509.” in Proc. Lund University. Martin Bojrup. Bueno. J.” accepted to be presented in Proc of Power Tech Conference (PT’05). Y. Saccomando. F. 775 – 780.” IEEE Trans. G. which results in protecting the VSC from tripping due to overcurrents or current imbalance during the dip period. Barraclough. 1997. 1189-1196. St. Implementing this controller the currents on the VSC side are symmetrical while the amount of imbalance in the current on the grid side is reduced from 132 % to 5 % in case of a voltage dip due to a single phase fault with 10 % remaining voltage. CONCLUSIONS [5] A vector current controller for VSC connected to the grid through LCL-filter is developed with the main focus on reducing current imbalance in case of unbalanced voltage dips at the grid. 27-30th June 2005. pp. REFERENCES [1] F. 30th Sept. The DVC has been tested with the same cases of grid voltage imbalance.G. 2. 1999. Sweden. H. Chalmers University of Technology. Le. Bollen. “Transient Operation of Grid Connected Voltage Source Converter Under Unbalanced Voltage Conditions.V. “A Nonlinear Control of the Instantaneous Power in dq Synchronous Frame for PWM AC/DC Converter Under Generalized Unbalanced Operating Conditions. Dutton. Thompson. J.Suh. T. pp 68-73.S. Modeling and Control of Voltage Source Converters Connected to the Grid. K. (in German). 11. Lic. H. Cobreces. Petersburg. vol. Russia. Understanding power quality problems: voltage sags and interruptions. of IEEE Industry Applications Society Annual Meeting 2001. A. Bd. thesis. “Grid current regulation of a three-phase voltage source inverter with an LCL input filter. one is implemented in the positive sequence frame and the other is implemented in the negative sequence frame. pp. “Design of Current Controller for Three-Phase PWM Converter with Unbalanced Input Voltage. on Power Electronics. The controller is applied in the positive sequence frame and the negative sequence capacitor voltage vector is fed-forward with relevant relations that are derived here.J. 17. Magueed. vol.” IEEE International Symposium on Industrial Electronics (ISIE '03). Nam. Dell’Aquila.S. Holmes. J. IEEE Press. Mok. The Art of Control Engineering. S. A. pp. K. Blaabjerg.299 – 307.” 36th Industry Applications Conference (IAS’01). November 1998. M. J. Svensson. vol. V. Blaabjerg. pp. Addison-Wesley Longman. “Analysis of the Grid Side Behavior of a LCL-Filter Based Three-Phase Active Rectifier. “Transient Performance of Voltage Source Converter Connected to Grid through LCL-Filter under Unbalanced Voltage conditions. and S. D. Twining. Choe. M.-N. (1989).Tech. “Vector Current Controlled Voltage Source Converter. J. E. “Design and Control of an LCL-filter Based Three-phase Active Rectifier. Kim. The resulting grid side current is balanced while the VSC side current has an amount of imbalance of less than 5 %. IEEE Industry Applications Society Annual Meeting 2002. vol. pp. Sweden 1999.285. on Industrial Electronics. Svensson.” in Proc. Liserre. Rodriguez. A. Hyun.” etzArchiv. Urena. pp.” 35th Annual IEEE Power Electronics Specialists Conference PESC’ 2004. Gothenburg. Lipo.Deadbeat Control and Saturation Strategies. Liserre. 2. Sannino. and S. [4] IAS 2005 578 0-7803-9208-6/05/$20. ISBN 9188934-13-6. ISBN 91-7197-710-4. H. The grid currents are almost symmetrical during the different voltage dips.1.” in Proc.00 © 2005 IEEE . E. S.S. Song. no.46. M. and A.” IEEE Trans. Michael Lindgren. 3. B. pp.

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