Service Manual

Model #: VIZIO P50HDM

V, Inc 320A Kalmus Drive Costa Mesa, CA 92626 TEL : +714-668-0588 FAX :+714-668-9099

-TOP Confidential -

Table of Contents
CONTENTS Sections 1. Features 2. Specifications 3. On Screen Display 4. Factory Preset Timings 5. Pin Assignment 6. BLOCK DIAGRAM 7. Main Board I/O Connections 8. Theory of Circuit Operation 9. Waveforms 10. Trouble Shooting 11. Spare Parts List 12. Complete Parts List Appendix 1. Main Board Circuit Diagram 2. Main Board PCB Layout 3. Assembly Explosion Drawing Block Diagram 1-1 2-1 3-1 4-1 5-1 6-1 7-1 8-1 9-1 10-1 11-1 12-1 PAGE

VIZIO P50HDM Service Manual

VINC
COPYRIGHT © 2000 V, INC. ALL RIGHTS RESERVED.

Service Manual
VIZIO P50HDM

IBM and IBM products are registered trademarks of International Business Machines Corporation. Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc. VINC and VINC products are registered trademarks of V, Inc. VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards Association (VESA). Energy Star is a registered trademark of the US Environmental Protection Agency (EPA). No part of this document may be copied, reproduced or transmitted by any means for any purpose without prior written permission from VINC. FCC INFORMATION This equipment has been tested and found to comply with the limits of a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy, and if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that the interference will not occur in a particular installation. If this equipment does cause unacceptable interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures -- reorient or relocate the receiving antenna; increase the separation between equipment and receiver; or connect the into an outlet on a circuit different from that to which the receiver is connected. FCC WARNING To assure continued FCC compliance, the user must use a grounded power supply cord and the provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized changes or modifications to Amtrak products will void the user’s authority to operate this device. Thus VINC Will not be held responsible for the product and its safety. CE CERTIFICATION This device complies with the requirements of the EEC directive 89/336/EEC with regard to “Electromagnetic compatibility.” SAFETY CAUTION Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL); Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric Appliance Control Act); or an AC cord that meets the local safety standards.

VIZIO P50HDM Service Manual

Chapter 1
Wall-mountable

Features

New WIDE HD Plasma Panel:1366 x 768 (H x V) TruSurround XT sound system and DCDi by Faroujia video image High definition digital interface – HDMI HDCP supportive Multiple-screen display (picture-on-picture/picture-in-picture) Selectable picture mode 4-language On Screen Display 2 S-video and Composite video inputs 2 Component video inputs 2 HDMI inputs 6 audio stereos, 1 PC Mini-Jack Supporting DVI converted to HDMI Closed caption Gloss front bezel The thinnest model of this size: 99 mm

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Page 1-1 File No. SG-0173

024 (B) colors 1106. INPUT SOURCE RGB Signal: H: support to 30-80KHz V: support to 60-85Hz Pixel Clock: support to 108MHz HDMI Signal: H: 15.024 (G) x 1. dark room) 1. SG-0173 .300±0.02 White (w/glass filter) Warm (5400K) Standard (6500K) Cool (9300K): 2.300 cd/m 8000:1 (Typical.02.1 mm(V) 1000 cd/m2 (Typical) Min.300±0.734KHz H: 31KHz H: 45KHz H: 33KHz V: 60Hz (480i) V: 60Hz (480p) V: 60Hz (720p) V: 60Hz (1080i) S-Video: Video (Y): Analog 0. y=0.810 mm (H) X 0.024 (R) x 1.286p-p/75Ω CONFIDENTIAL – DO NOT COPY Page 2-1 File No.810mm (V) Non-stripe 1.1Vp-p/75Ω Video (C): Analog 0.5 mm (H) x 622.Chapter 2 Specification Item Specification 1366 (H) x 768 (V) pixels 0. OPTICAL CHARACTERISTICS Display Pixels Pixel Pitch Pixel Type Color Depth Active Display Area Brightness (panel spec) (w/glass filter) Contrast ratio (panel spec) Color Coordinates (typical) White (Panel spec) x=0.

734KHz H: 31KHz H: 45KHz H: 33KHz V: 60Hz (NTSC) V: 60Hz (NTSC-480i) V: 60Hz(NTSC-480p) V: 60Hz(NTSC-720p) V: 60Hz(NTSC-1080i) 3.734KHz Component signal: YPbPr/YCbCr H: 15. OUTPUT CONNECTORS a. 3. Audio RCA Jack x 2 AV2 AV1 Input Label ANALOG HD1 ANALOG HD2 Connector Type YPb/Cb Pr/Cr RCA Jack x 3 Audio RCA Jack x 2 YPb/Cb Pr/Cr RCA Jackx 3 Audio RCA Jack x 2 RCA Jack (CVBS) x 3 S-video 4 pin mini DIN x 1 RCA Jack (CVBS) x 3 S-video 4 pin mini DIN x 1 b. POWER SUPPLY Consumption: 550W MAXPower OFF: less than 3W 6. SG-0173 . INPUT CONNECTORS Input Label SERVICE DIGITAL HD1 DIGITAL HD2 RGB Connector Type RJ-11 x 1 19 pin HDMI x 1 Audio RCA Jack x 2 19 pin HDMI x 1 Audio RCA Jack x 2 D-sub 15 pin x 1 Mini Jack x 1 (Audio input) 4. SPEAKER Output 8Ω/10W (max) X2 CONFIDENTIAL – DO NOT COPY Page 2-2 File No.5mm Mini-jack earphone x 1 5.Composite Video signal: H: 15.

560 ft Non-operating a. SG-0173 .2 +/. Temperature: 0~40℃ b. Temperature: -20~60℃ b.7. Depth: 310 mm (with standard). Relative humidity: 10%~90% RH Altitude: 0~9.2 +/. WEIGHT a.0. 99 mm (without standard) 9. Net: 55.5 kgs b.0.5 kgs CONFIDENTIAL – DO NOT COPY Page 2-3 File No. Height: 871 mm b.840 ft 8. c. DIMENSIONS a. Width: 1241mm c. Gross: 65. c. ENVIRONMENT Operating a. Relative humidity: 20%~80% RH Altitude: 0~6.

Chapter 3
Main unit button
POWER

On Screen Display

MENU
▲ ▼

VOL-/ VOL+/ INPUT

OSD Adjustment
Mode Image Settings VIDEO Picture Mode(User, Vivid, Movie, Game, Sport) Brightness(0~100) Contrast(0~100) VIDEO VIDEO VIDEO Saturation(0~100) Hue(-50~50) Sharpness(0~24) Advanced VIDEO VIDEO VIDEO VIDEO VIDEO PC PC PC PC PC PC CONFIDENTIAL – DO NOT COPY Fleshtone Dynamic (0, 1, 2, 3) Auto Adjustment Image Position Phase Clocks / Line Color Temp Warm(5400K) Page 3-1 File No. SG-0173 Contrast Noise Reduction Motion(0~16) Digital(0~64) Off, High, Moderate, Low

PC PC PC PC PC PC Display Settings VIDEO PC Aspect Ratio Aspect Ratio PIP PIP Mode Wide, Normal,

Standard(6500K) Cool(9300K) User Red(0~100) Green(0~100) Blue(0~100)

Zoom, Panoramic* Wide, Normal

Off, Large PIP, Small PIP, POP Top-Left, Top-Right,

PIP Position

Bottom-Left, Bottom-Right

PIP Input** Audio Settings Bass(0~20) Treble(0~20) Balance(-10~10) SRS TS XT(Off, On) Auto Volume(On, Off) Speakers(On, Off) Audio Out*** Fixed Volume,

Variable Volume Parental Controls VIDEO VIDEO VIDEO Password Settings TV Rating

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VIDEO

TV Youth (Unblocked, Blocked)

VIDEO

TV Youth 7 (Unblocked, Blocked)

VIDEO

TV G (Unblocked, Blocked)

VIDEO

TV PG (Unblocked, Blocked)

VIDEO

TV 14 (Unblocked, Blocked)

VIDEO

TV MA (Unblocked, Blocked)

VIDEO VIDEO VIDEO Movie Rating

Unblocked

Movie G (Unblocked, Blocked)

VIDEO

Movie PG (Unblocked, Blocked)

VIDEO

Movie PG-13 (Unblocked, Blocked)

VIDEO

Movie R (Unblocked, Blocked)

VIDEO

Movie NC-17 (Unblocked, Blocked)

VIDEO

Movie X (Unblocked, Blocked)

VIDEO Block Unrated (No, Yes) CONFIDENTIAL – DO NOT COPY

Unblocked

Page 3-3 File No. SG-0173

VIDEO VIDEO

Change Password Please enter new password

VIDEO

Please re-enter new password

VIDEO Setup Closed Caption

Clear All (No, Yes)

Off, Display CC4,

CC1,

CC2,

CC3,

TEXT1,

TEXT2,

TEXT3, TEXT4 Captions on mute (On, Off) Language English, Français, Español, Italiano Factory Reset (Yes, No) Image Cleaner Firmware Version

* HDMI and Component 720P/1080i inputs do not support Panoramic. ** See below for detailed information regarding the PiP sources.

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SG-0173 . S-Video has priority.Main \ Sub AV1 (S-VIDEO) AV2 (S-VIDEO) AV1 (VIDEO) AV2 (VIDEO) Analog HD1 Analog HD2 Digital HD1 Digital HD2 RGB AV1 AV2 AV1 AV2 (VIDEO) Analog HD1 Analog HD2 Digital HD1 Digital HD2 (S-VIDEO) (S-VIDEO) (VIDEO) RGB x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Remark: (1):“x” – Indicates which inputs are available for PIP and POP modes. If a signal is connected to AV1 S-Video by itself or signals are connected to AV1 S-Video and AV1 Video simultaneously. If a signal is connected to AV1 Video only. then S-Video will be the only choice for AV1. (2):For AV1 and AV2. then Video will be the only choice for AV1. *** When Speakers off CONFIDENTIAL – DO NOT COPY Page 3-5 File No. The same input priority scheme applies to AV2.

4 56.7 63.000 Windows Windows Windows Windows Windows Windows Windows Windows Windows Windows Pixel Rate (MHz) Remark Mode No.94 75.5 37.Chapter 4 Factory preset timings This timing chart is already preset for this plasma monitor. PC analog preset modes Refresh Horizontal Resolution Rate (Hz) 640x480 640x480 800x600 800x600 800x600 1024x768 1024x768 1024x768 1366X768 1280X1024 60 75 60 75 85 60 70 75 60 60 (KHz) 31.750 85.7 48.5 60.06 60.07 75.5 37. Frequency Frequency 1 2 3 4 5 6 7 8 9 10 Remark: P:positive,N: negative 1024x768 @60 Hz: Primary CONFIDENTIAL – DO NOT COPY Page 4-1 File No.98 Vertical (Hz) 59.01 70.9 53.000 49. SG-0173 .0 47.03 60.9 46.000 75.175 31.500 56.00 60.500 108.500 40. 1.00 60.250 65.317 75 85.000 78.02 Horizontal Sync Polarity (TTL) N N P P P N N P P P Vertical Sync Polarity (TTL) N N P P P N N P N P 25.

3.175 Windows Remark Mode No. HD video digital preset modes at HDMI Mode No.5 Vertical Frequency (Hz) 59. 1 CONFIDENTIAL – DO NOT COPY Page 4-2 File No. 1 2 3 4 Resolution 480i 480p 720p 1080i Resolution 480i 480p 720p 1080i 3.94 Horizontal Vertical Sync (TTL) N Sync (TTL) N Polarity Polarity Pixel Rate (MHz) 25.3. HD digital preset modes at DVI Through HDMI interface by an optional interface cable 2. 1 2 3 4 3.3.2.2 PC input Refresh Horizontal Resolution Rate (Hz) 640x480 60 Frequency (KHz) 31.1 video input. SG-0173 . 1 Video input Mode No.

1. Impedance: e.1. female V: 60-85Hz 5 5 1 10 15 11 6 1 6 11 10 15 Pin Number 1 2 3 4 5 6 7 Pin Assignment Red video input Green video input Blue video input Ground Ground Red video ground Green video ground Pin Number 9 10 11 12 13 14 15 +5V Pin Assignment Ground No connection (SDA) Horizontal sync (Composite sync) Vertical sync (SCL) CONFIDENTIAL – DO NOT COPY Page 5-1 File No.1 Analog 1. Frequency: c. Video bandwidth: g. Signal level: d.7Vp-p 75Ω H/V separate sync: TTL H/V composite sync: Sync on Green TTL 135MHz 15-pin D-Sub.Chapter 5 1. SG-0173 .Input Pin Assignment There are analog and digital connectors as video input source in this model. Connector type: Analog H: 30-80KHz 0. Synchronization f. Type: b.1 RGB Connector a.

Signal level: c. Frequency: b. Connector type: 1.734KHz Y: 1Vp-p 75Ω 4-pin mini DIN V: 60Hz C: 0.734KHz H: 31KHz H: 45KHz H: 33KHz b.2 RCA-type (Yellow) Composite Video Connector a. Impedance: d. 2 = GND 3 = Luminance (Y) 4 = Chrominance(C) a. SG-0173 .1.4 Y-Cb/Pb-Cr/Pr Component video signal a. Signal level: c. Connector type: 1Vrms 47KΩ 3.286Vp-p (NTSC) 1.350Vp-p CONFIDENTIAL – DO NOT COPY Page 5-2 File No.3V below Video (Y+C) 4 2 3 1 1.734KHz 1Vp-p 75Ω RCA jack V: 60Hz Sync (H+V): (NTSC) 0. Signal level: c. Impedance: d.1.350Vp-p (NTSC-480i) (NTSC-480p) (NTSC-720p) (NTSC-1080i) Pr: ±0.3 S-Video Connector H: 15.5 φ mini jack Y: 1Vp-p 75Ω RCA jack V: 60Hz V: 60Hz V: 60Hz V: 60Hz Pb: ±0. Frequency: H: 15.1. Impedance: d. Signal level: b. Frequency: b.1.1. Impedance: c. Connector type: 1.5 PC audio in a. Connector type: H: 15.

Impedance: d. Frequency Response: 250Hz-20KHz Pin 19 Pin 1 Pin 2 CONFIDENTIAL – DO NOT COPY Page 5-3 File No. Pin Assignment: Positive or Negative Type A Please see below V: 60Hz V: 60Hz V: 60Hz V: 60Hz 0. Connector type: 1.6 Video audio in a. Frequency: H: 15.1. SG-0173 . Polarity: c.HDMI a.1. Signal level: b.7Vrms 47KΩ RCA L/R: c. Type: d.734KHz H: 31KHz H: 45KHz H: 33KHz b.2 Digital .

2 Audio output a. Signal level: b.C. Frequency Response: d. Output: d. SG-0173 . Impedance: c. Connector type: 2.1 Earphone a. on device) SDA +5V Power 2.Pin 1 3 5 7 9 11 13 15 17 19 Signal Assignment TMDS Data2+ TMDS Data2TMDS Data1 Shield TMDS Data0+ TMDS Data0TMDS Clock Shield CEC SCL DDC/CEC Ground Hot Plug Detect Pin 2 4 6 8 10 12 14 16 18 Signal Assignment TMDS Data2 Shield TMDS Data1+ TMDS Data1TMDS Data0 Shield TMDS Clock+ TMDS ClockReserved (N. Impedance: c. Signal level: b.7Vrms 47KΩ 250Hz-20KHz RCA L/R: 1Vrms (max. Output 2. Connector type: 0.) 32Ω 50 mW Earphone mini jack CONFIDENTIAL – DO NOT COPY Page 5-4 File No.

SG-0173 .Chapter 6 Block Diagram System Block Diagram POWER BOARD Y DRIVER BOARD X DRIVER BOARD LVDS BOARD W1 CN12 CN13 CN5 CN3 CN1 CN2 J8 MAIN BOARD J7 IR BOARD EMI Fillter CONFIDENTIAL – DO NOT COPY Page 6-1 File No.

SG-0173 .Main board System Block Diagram J9 2 1 3 J10 2 1 3 ARXD ATXD_HUD ATXD ARXD_HUD U26 MAX232A ATXD_HUD ARXD_HUD VEDIO U40 24LC128 EEPROM(8051) UC_SCL/UC_SDA U38 SST89C58 U20 4052 I/O SW 51_RXD/51_TXD HY5DU56822CT-D4 U17 DDR RAM CTZ HY5DU56822CT-D4 U16 DDR RAM HUD FL8532_CTZ Frame Store DDR Interface Frame Store DDR Interface KEY PAD CN5 CN12 CN13 W8 U42 Sil 9011 HDMI RS ADATA[0:23] IPCLK0/AHS/AVS/AHREF_DE HDMI1 AUDIO 51_RXD/51_TXD ARXD ATXD IPCLK0/AHS/AVS/AHREF_DE IPCLK1/BHS/BVS/BDE MSTR2_SCL/MSTR2_SDA MSTR1_SCL/MSTR1_SDA VGA_SCL / VGA_SDA ADATA[0:23] BDATA[0:23] UART 2 Wire Controller SCL-33V / SDA-33V U25 F75373S MSTR0_SCL/MSTR0_SDA CN17 U37 24LC02 EEPROM HDMI1 U35 Sil 9011 HDMI RS BDATA[0:23] IPCLK1/BHS/BVS/BDE HDMI2 AUDIO GPIO 2 Wire Controller 2 Wire Controller Digital A Input Digital B Input VGA_SCL / VGA_SDA W13 U40 24LC02 EEPROM HDMI2 ANLOG DDC U21 24LC02 EEPROM VGA U45 74HCT14 Inverting Schmitt Trgger LVDS Display Interface W1 Display VS / HS CN16 R G B U22 M61323FP VEDIO SW A4/B4/C4 AIR_RAW_HS_CS/AIR_RAW_VS SV4_CTZ SV2_CTZ SV3_CTZ/A1_CTZ B1_CTZ/C1_CTZ A4/B4/C4_CTZ A3/B3/C3_CTZ A2/B2/C2_CTZ JTAG_BS_TCK/TDO/TMS/TDI/TRST Analog input JTAG Boundary Scan OCM External SRAM XU1 A29LV320D MEMERY_CTZ W6 U23 M61323FP VEDIO SW ATSC Y Pr Pb A3/B3/C3_CTZ MSTR1_SCL/MSTR1_SDA 2 Wire Controller JTAG Boundary Scan UART I2CCM U11 24LC32 EEPROM HUD U12 SST25VF040 FLASH 512K HUD NC7SB3157 U18 BUS SW Y Pr Pb Y Pr Pb W7 U24 M61323FP VEDIO SW A3/B3/C3_HUD JTAG_BS_TCK/TDO/TMS/TDI/TRST ATXD_HUD ARXD_HUD AIR_RAW_HS_CS/AIR_RAW_VS A4/B4/C4_HUD A3/B3/C3_HUD A2/B2/C2_HUD SV4_HUD SV2_HUD SV3_HUD/A1_HUD B1_HUD/C1_HUD COMP1_Audio_R/L COMP2_Audio_R/L W11 AudioAV1_R/L CVBS1 CVBS2 W14 AudioAV2_R/L A2/B2/C2 Analog input Serial ROM Interface IPCLK1/BHS/BVS/BDE GPIO BDATA[0:23] LVDS Display Interface FL8125_HUD W10 Y1/C1 Y2/C2 U37 CS3443 HDMI2 LR DAC U36 CS3443 HDMI1 LR DAC U46 IDTQS3253 HDMI1 AUDIO SW U42 IDTQS3253 HDMI1 AUDIO SW HDMI1_AUDIO_L/R HDMI2_AUDIO_L/R AudioAV1_R/L AudioAV1_R/L MSTR2_SCL/MSTR2_SDA AUDIO W5 VGA_AUDIO_L/R U28 MAX4550 AUDIO SW 4/2 I/O U27 MAX4550 AUDIO SW 4/2 I/O CH4_R/L CH3_R/L Lineout_R/L W13 AUDIO L/R OUT W12 COMP1_Audio_R/L COMP2_Audio_R/L VGA_AUDIO_L/R CH2_R/L CH1_R/L U32 P4450G AUDIO PROCESS U33 PT2308 AUDIO DRIVER U34 PT2308 AUDIO DRIVER TDA8946AD AUDIO_AMP J7 Speaker R J8 Speaker L HLIN/HRIN Headphone CONFIDENTIAL – DO NOT COPY Page 6-2 File No.

Chapter 7 Main Board Internal I/O Connections CN1 “DC POWER INPUT’ PIN 1 2 3 4 5 6 7 8 9 10 11 12 CN2 “DC POWER INPUT’ PIN 1 2 3 4 CN3 “DC POWER INPUT/OUTPUT’ PIN 1 2 3 4 Description GND VS_ON RLY_ON PDP_+5Vsb Description PDP_Audio PDP_Audio GND GND Description PDP_+5Vsc PDP_+5Vsc PDP_+5Vsc GND GND GND PDP_+12V PDP_+12V GND GND PDP_+12V_FAN PDP_FGND CONFIDENTIAL – DO NOT COPY Page 7-1 File No. SG-0173 .

SG-0173 .CN5 CONNECTION “KEYPAD” PIN 1 2 3 4 5 6 7 8 9 10 P1 P2 Description LED2_KEYPAD KEY_VCC IR ADC_IN2 NC GND +3.3V_LBADC ADC_IN1 LED1_KEYPAD_BUF GND GND GND CN6 CONNECTION “HDMI/ATSC_UP” PIN 1 2 3 4 Description +5V 51_TXD 51_RXD GND CN7 CONNECTTION “ODC2BI” PIN 1 2 3 Description VGA_SCL_CTZ VGA_SDA_CTZ GND CONFIDENTIAL – DO NOT COPY Page 7-2 File No.

SG-0173 .CN12 FAN CONNECTION PIN 1 2 3 4 Description NC FANIN1 +12V_FAN FGND CN13 FAN CONNECTION PIN 1 2 3 Description FANIN1 +12V_FAN FGND J7 CONNECTION “SPEAKER R” PIN 1 2 3 Description RLRL+ NC J8 CONNECTION “SPEAKER L” PIN 1 2 Description LLLL+ CONFIDENTIAL – DO NOT COPY Page 7-3 File No.

SG-0173 . “OFF” NO JUMPER CONFIDENTIAL – DO NOT COPY Page 7-4 File No.3V_I/O +5V Default ON OFF “ON” ADD JUMPER .W1 CONNECTION “LVDS” PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 Description GND TXA3TXACTXA2+ TXA1+ TXA0+ GND +5V_SW +5V_SW GND NC NC TXB3VS_ON SDA_33V GND PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Description TXA3+ TXAC+ GND TXA2TXA1TXA0GND +5V_SW GND NC NC TXB3+ GND SCL_33V NC J3 SELECT KEY POWER PIN 1-2 2-3 Description +3.

“OFF” NO JUMPER CONFIDENTIAL – DO NOT COPY Page 7-5 File No. “OFF” NO JUMPER J10 CONNECTION “PROGRAMUPDATA” PIN 1-2 2-3 Description ATXD ATXD_HUD Default ON OFF “ON” ADD JUMPER .J9 CONNECTION “PROGRAMUPDATA” PIN 1-2 2-3 Description ARXD ARXD_HUD Default ON OFF “ON” ADD JUMPER . SG-0173 .

▼▲. They are “Power. and the state will be reader by FLI8532 through internal ADC to act corresponding function. Source. 3. Figure 8-1 User Interface Block Diagram The operation of keypad There are 8 keys to control and select the function of SHD-3010 and also have two LED to indicate the status of operation. MENU.The LED is constructed with two color LED which color is Yellow and Green.The other seven keys are on high state because the pull up resistor but will transit to low state dependent on which key pressed.The power key controls video processor FLI8532. CONFIDENTIAL – DO NOT COPY Page 8-1 File No.Chapter 8 Theory of Circuit Operation The operation of User Interface The following diagram provides a brief overview of the user-interactive components of the firmware. FLI8532 will receive a low signal to turn on or off system while press the power key. The FLI8532 direct control the LED’s when FLI8532 (VPCON) is low the LED is Yellow (Close power) when FLI8532 (VPCON) is high the LED is Green (Open power). 1. + -” keys and LED. 2. SG-0173 .

All additional clocks are internal clocks derived from one or more of these: 1. See Figure 9. and other VBI technologies. and noise reduction.Digital Input Video/Graphics Clocks (IPCLK0.Crystal Input Clock (TCLK and XTAL). and enhance any video or PC graphic format. The FLI8532 supports many worldwide VBI standards for applications of Teletext. This is the input pair to an internal crystal oscillator and corresponding logic. SG-0173 . If an external crystal is being used. connect a 10K pull-up to OCMADDR_19. a single-ended TTL/CMOS clock oscillator can be driven into the TCLK pin (leave XTAL as N/C in this case). 2. video enhancement.Audio Delay Clock (AVS_CLK) The FLI8532 TCLK oscillator circuitry is a custom designed circuit to support the use of an external oscillator or a crystal resonator to generate a reference frequency source for the FLI8532device. process.The operation of Video Processor FLI8532 The Genesis Microchip FLI8532 includes an integrated 3-D Digital Video Decoder with Faroudja DCDi CinemaTM video format conversion. Closed Captioning. CONFIDENTIAL – DO NOT COPY Page 8-2 File No. IPCLK2 and IPCLK3) 3.6608 MHz TV crystal is recommended for best noise immunity with the 3D decoder. IPCLK1. Alternatively. Figure 8-2 FLI8532 Block Diagram Clock Generation: The FLI8532 features six clock inputs. The auto-detection and Faroudja DCDi CinemaTM technology allow the FLI8532 to detect. V-Chip. A 19.

). B). HS.Analog Input Port (AFE): The FLI8532 chip has a sophisticated Analog Front End with 16 reconfigurable inputs through and analog multiplexer to anti-alias filters before the Analog to Digital Converters (ADCs). Pb) or RGB (R. YPrPb (Y. Figure 8-3 Analog Front End The figure above depicts the data-path for the AFE and Decoder blocks with connections to the input multiplexer that selects whether the data follows the Main Video Channel or PIP video channel. The analog front end of FLI8532 provides the capability to capture 16 analog video inputs which can be a combination of Composite (CVBS). etc.G. Digital Input Port (DFE): The Digital Input Port is a 48bit data input with flexible configuration to support a wide range of digital sources. Pr. SG-0173 . and 4 input clocks. Up to 4 different inputs are supported as long as at least 2 of these inputs are 8bit CCIR656. These integrated features eliminate the need for any devices between the input connector and the pin of the FLI8532. It consists of two 24bit ports (PORTA and PORTB). CONFIDENTIAL – DO NOT COPY Page 8-3 File No. S-Video (SY. SC). ODD. two sets of control signals (VS.

Due to pin sharing. Sync and clock polarity is programmable. The following digital video formats are supported by FLI8532 digital video graphic port: • ITU-BT-656 • 8-bit 4:2:2 YCbCr or YPbPr • 16-bit 4:2:2 YCbCr or YPbPr • 24-bit 4:4:4 YCbCr or YPbPr • 24-bit RGB Digital Input Port Configuration: The Digital Input Port offers flexible mapping of the input buses for PORTA and PORTB and allows individual Bus Flipping (MSB to LSB) for each group of 8bit inputs. Figure 8-4 Digital Input DATA bus assignment CONFIDENTIAL – DO NOT COPY Page 8-4 File No. DIP_EXT_COAST. Bits 7 to 0 of PORTA can be configured as a bidirectional interface for media card applications. DIP_CLEAN_HS_OUT) for interfacing to external ADC/PLL devices. SG-0173 . The purpose of this flexible mapping is to ease the circuit board design when interfacing to other devices. This table below shows how the input DATA buses can be arbitrarily assigned through host registers.PORTA also includes optional signals (DIP_EXT_CLAMP. These signals are not present on PORTB. PORTB is not available when using 48bit double wide TTL output to the panel. Inputs to the digital input port are TTL compatible with a maximum clock speed of 135MHz.

then OSD OVL LVDS bit is clamped to 0. SG-0173 . C3_EVEN with register CONFIDENTIAL – DO NOT COPY Page 8-5 File No. The following diagram shows the available LVDS mapping for 30-bit LVDS output which is applying to PDP panel spec: 30-bit LVDS Output Stream To Configure for 30-bit LVDS with this data mapping: LVDS_POWER (0x8726) = 0x3F LVDS_DIGITAL_CTRL (0x8728) = 0bUU00UU00.LVDS Transmitter: Two LVDS channels (A and B) are available on the output of the FLI8532 to transmit data and timing information to the display device. If 0x8500[9] = 0. the following bus remappings are supported: Swap LVDS serial stream (6:0)、(0:6) with register 0x8728[7] Swap LVDS positive and negative differential outputs with register 0x8728[3] Swap LVDS bus data CH0_EVEN C3_ODD and CH1_EVEN 0x8728[2] Note: OSD OVL data bit is enabled with register 0x8500[9] with polarity controlled by 0x8500[10]. DISPLAY_CONTROL(0x862C)[11] = 1 For 30-bit LVDS. where U is user options.

Genesis Workbench is a GUI based tool for defining OSD menus. This is illustrated above. and functionality. It programs the FLI8532 and manages other devices in the system such as the keypad and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO) pins. CONFIDENTIAL – DO NOT COPY Page 8-6 File No. FLI8532 I2C Master Serial Protocol : The two-wire protocol consists of a serial clock MSTR_SCL and bi-directional serial data line MSTR_SDA. These busses can be independently taken “off-line” or pulled up to different voltages without affecting the other busses. Both firmware and OSD content must be compiled into a HEX file and then loaded onto the external ROM. External Flash-ROM memory requirements range from 512Kbytes to 4Mbytes depending on the application. as well as driver-level (or Application Programming Interface – API) functions residing in internal ROM. The OSD content is generated using Genesis Workbench. all driven by a common Master Serial Controller. SG-0173 . The OCM can address a 22-bit address space to utilize 4 MB external ROM Figure 8-5 FLI8532 OCM block diagram The OCM executes a firmware program running from external ROM.On Chip Microcontroller: The FLI8532 on-chip micro-controller (OCM) serves as the system micro-controller. There are three isolated Master Serial busses. commercially available ROM or programmable Flash ROM devices in either 8 or 16-bit configurations. This port connects directly to standard. The FLI8532 acts as bus master and drives MSTR_SCL and either the master or slave can drive the MSTR_SDA line (open drain) depending on whether a read or write operation is being performed. A parallel port with separate address and data busses is available for this purpose. navigation.

Each byte is transmitted with the most significant bit (MSB) first. A transfer is terminated by a STOP (a low-to-high transition on MSTR_SDA while MSTR_SCL is held high) or by a START (to begin another transfer). The addressed receiver is obliged to acknowledge each byte that has been received. A two-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in the figure below. Figure 8-7 FLI8125 System Block Diagram CONFIDENTIAL – DO NOT COPY Page 8-7 File No. The number of bytes that can be transmitted per transfer is unrestricted. we use FLI8125 to process most of PIP source input and then output digital video signal to FLI8532. the master releases the MSTR_SDA line and the receiver asserts the MSTR_SDA line low to acknowledge receipt of the data. The operation of Video Processor FLI8125 FLI8125 is another video processor designed by Genesis. bytes). Figure 8-6 Two-Wire Protocol Data Transfer Each transaction on the MSTR_SDA is in integer multiples of 8 bits (i.e. The master device generates the MSTR_SCL pulse during the acknowledge cycle. SG-0173 . After the eight data bits. A transfer is initiated (START) by a high-to-low transition on MSTR_SDA while MSTR_SCL is held high.The two-wire protocol requires each slave device to be addressable by a 7-bit identification number. In this product.

In case of analog composite video input this runs in open loop. 3.Host Interface Transfer Clock (SCL). 6. SG-0173 . Clock Synthesis Additional synthesized clocks using PLLs: 1. This is shared with ROM Address line 11.Extended Clock (ECLK) synthesized by EDDS.Video Port VCLK 5. Used by the decoder. a single ended TTL/CMOS clock input can be driven into the XTAL pin (leave TCLK as n/c in this case). Used as OCM_CLK domain driver.External Clocks on various GPIOs for test purposes 3.Reference Clock (R_CLK) synthesized by RCLK PLL using T_CLK or EXTCLK as the reference. This is the input pair to an internal crystal oscillator and corresponding logic.A fixed frequency clock created by LDDS (LCLK). CONFIDENTIAL – DO NOT COPY Page 8-8 File No. Used by the expander in case of panoramic scaling. The DDDS also uses the R_CLK to drive internal digital logic.Crystal Input Clock (TCLK and XTAL). Alternatively.Second Video port clock. The SDDS also uses the R_CLK to drive internal digital logic. T_CLK is derived from the TCLK/XTAL pad input.Input Source Clock (SCLK) synthesized by SDDS PLL using input HS as the reference. This is available only when parallel ROM interface is not used. 2. I2C slave SCL for DDC2Bi and another SCL for Serial Inter-Processor Communication (SIPC) 4.Clock Generation The FLI8125 accepts the following input sources: 1. 2. 5.Display Clock (DCLK) synthesized by DDDS PLL using IP_CLK as the reference.Fixed Frequency Clock (FCLK) synthesized by FDDS. 4.Main Timing Clock (T_CLK) is the output of the chip internal crystal oscillator. 7.

Overall application cost is reduced by providing analog switching capabilities for 16 separate analog signals. S-Video. These signals are re-configurable as different combinations of composite. SG-0173 . CONFIDENTIAL – DO NOT COPY Page 8-9 File No. The Analog Front End directs inputs through an analog multiplexer to anti-alias filters before the Analog to Digital Converters (ADCs). These integrated features eliminate the need for any devices between the input connector and the AFE pin connection.Figure 8-8 FLI8125 Internally Synthesized Clocks Analog Front End The Analog Front End is responsible for selecting and capturing the desired analog input video stream. YPrPb and RGB video streams depending upon the end application. The following figure depicts the data-path for the AFE and Decoder blocks with connections to the input multiplexer .

or Y. Color Conversion. There are two types of switching required: Channel Selection. The Input to the DFE is 10 bit 40MHz Data. SG-0173 . G. Chroma Downscaling and 4fSC re-sampling. AGC Control. The Analog Source Selectors are responsible for switching the desired analog inputs to the ADCs for digitization. The DFE performs Digital Clamp Loop Control for each channel. S-Video (SY. Pr. SC). Pb) or RGB (R. Y. Digital Front End (Digital Processing after AFE) The DFE consists of 3 channels that can support the following Fixed-position formats: Channels 1. 2 and 3 can be either R.Figure 8-9 Analog Input Port The Analog Front End provides the capability to capture 16 analog video inputs which can be a combination of Composite (CVBS). Fast Blank Switching. B).V or 2 channels of Y and C or one channel of CVBS.B. C or YUV or just 10 bit CVBS. YPrPb (Y. CONFIDENTIAL – DO NOT COPY Page 8-10 File No.G. The Output is 4fsc Sampled CVBS.U.

16-bit or CCIR656 inputs HS/CSYNC – Horizontal sync or composite sync signal VS/SOG – Vertical sync input or SOG input DV/CLAMP – Data valid input indicator NOTE: Unused pins of the Digital Input Port can be reprogrammed as GPIOs to increase the total number of GPIOs available. The 24-bit Digital Input Port provides control signals to simplify signal detection. CCIR656 data streams embedd all timing markers. a selectable color space converter is used to transform RGB video input data from a DVI Rx to internal 16-bit 4:2:2 YUV. 16-bit 4:2:2 YUV data or 24-bit RGB data. for the 24-bit and 16-bit inputs the following signals are provided: CLK1 – Input pixel clock for 24-bit. video decoders. Other RGB input data streams.Figure 8-10 Digital Datapath Digital Input Port The Digital Input Port is 24-bit input bus that can be connected to external DVI receivers. For RGB input data. and ACM in the image processing block. etc. ACC. and is able to accept either 8-bit CCIR656 data. Inputs to the digital input port are TTL compatible with a maximum clock speed of 135MHz. Sync and clock polarity is programmable. CONFIDENTIAL – DO NOT COPY Page 8-11 File No. This allows the input data to be processed by the Horizontal Enhancment Module (HEM). such as computer inputs. SG-0173 . remain in the RGB space and are processed as such.

For all other inputs. For a flat panel TV. CONFIDENTIAL – DO NOT COPY Page 8-12 File No. Only data within the programmable window is allowed through the data pipeline for subsequent processing. the Input Capture Window is referenced with respect to Horizontal and Vertical Sync. Data that lies outside of the window is ignored. Figure 8-11 Input Capture Window Input cropping is required in a video system since video signals are normally over scanned. The selected input data stream is cropped using a programmable input capture window.Input Capture The Input Capture block is responsible for extracting valid data from the input data stream and creating the required synchronization signals required by the data pipeline. in order to over scan the image. SG-0173 . a smaller portion of the input image needs to be selected and then expanded to fill the entire screen. This block also provides stable timing when no stable input timing exists. Input data streams originating from CCIR656 sources are cropped with reference to the start and end of active video flags encoded into the data stream.

DCDi Edge processing is optimized for a memory architecture that is unified with the memory used for scaling. To reduce the amount of memory required for the vertical scaling process. The maximum number of pixels per line supported by the vertical scalar is 1366. Figure 8-12 Imange Processing Block Diagram Faroudja DCDi Edge Processing Faroudja DCDi Edge processing is used to reduced/eliminate objectionable stair stepping that occurs on interlaced diagonal lines.Image Processing The following figure shows the various image processing blocks that operate on the captured video data stream. CONFIDENTIAL – DO NOT COPY Page 8-13 File No. horizontal shrink is performed prior to vertical scaling and horizontal expansion happens after vertical scaling. A flexible tap structure is used so that the number of taps can be increased based on the number of pixels per line and whether the input is 4:2:2 YUV or 4:4:4 RGB. When a processing block is bypassed. This block can process 24-bit RGB. It is capable of scaling the input by a factor of 0. SG-0173 . Each block is individually selectable and can be removed from the processing chain via a selectable bypass path. it automatically enters a low power mode to help reduce overall power consumption.05 to 5.0. 16-bit 4:2:2 YUV or 16-bit 4:2:2 YPrPb data streams. Scaling Engine The Scaling Engine accepts both 16-bit 4:2:2 YUV and 24-bit RGB inputs.

to display OSD messages or a splash screen) or for testing purposes. Frame Sync Mode: The display frame rate is synchronized to the input frame or field rate. All display data and timing signals are synchronous with the DCLK display clock. In free-run mode.Display Output Interface The Display Output Port provides data and control signals that permit the connection to a variety of flat panel devices using a 24-bit TTL or LVDS interface. This mode is used when there is no valid input timing (i. Output timing is fully programmable via the host interface register set enabling this device to be used as a display controller of a PIP processor for other Genesis Microchip devices. CONFIDENTIAL – DO NOT COPY Page 8-14 File No. The integrated LVDS transmitter is programmable to allow the data and control signals to be mapped into any sequence depending on the specified receiver format.e. SG-0173 . The following display synchronization modes are supported: standard operation. Vertical values are programmed in line increments relative to the leading edge of the vertical sync signal. the display timing is determined only by the values programmed into the display window and timing registers. Display Timing Programming Horizontal values are programmed in single-pixel increments relative to the leading edge of the horizontal sync signal. The output interface is configurable for single or dual wide LVDS in 18 or 24-bit RGB pixels format. DC balanced operation is supported as described in the Open LDI standard. This mode is used for Free Run Mode: No synchronization.

Typically the Display Active Window is set to the same size as the output of the Scaling Engine. This value is dithered down to either 8-bits for 24-bit per pixel panels. This window is always in the foreground and lies on top of all other output windows. Output Dithering The CLUT outputs a 10-bit value for each color channel. SG-0173 . then the extra space to the left and bottom of the Display Active Window is forced to the Background Window color.7 million colors on a LCD panel with 6-bit column drivers. In this way it is possible to display 16. CONFIDENTIAL – DO NOT COPY Page 8-15 File No.Figure 8-13 Display Windows and Timing Data captured by the Input Capture Window and processed by the various image manipulation blocks is output in the Display Active Window. If the Display Active Window is set too large. If the Display Active Window is set too small. or 6-bits for 18-bit per pixel panels. then the bottom and right hand edges of the image data are cropped. except OSD overlay windows.

Two dithering algorithms are available: random or ordered dithering. navigation. All gray scales are available on the panel output whether using 8-bit panel (dithering from 10 to 8 bits per pixel) or using 6-bit panel (dithering from 10 down to 6 bits per pixel). The LVDS transmitter can support the following: Single pixel mode 24-bit panel mapping to the LVDS channels 18-bit panel mapping to the LVDS channels Programmable channel swapping (the clocks are fixed) Programmable channel polarity swapping Supports up to SXGA 75Hz output On-Chip Microcontroller (OCM) The on-chip microcontroller (OCM) is a 16-bit x86 100MHz processor capable of acting as either the overall system controller or a slave controller. SG-0173 . Dual Channel LVDS Transmitter An integrated LVDS transmitter with programmable input to output configuration is provided to enable drive of all known panels. as well as driver-level (or Application Programming Interface – API) functions residing in internal ROM. commercially available ROM or programmable FLASH ROM devices. A serial FLASH ROM may be used with the serial peripheral interface (SPI) and cache controller inside the Genesis device. The OCM executes firmware running from external ROM. and functionality. Ordered dithering is recommended when driving a 6-bit panel. The OSD content is generated using Genesis Workbench. CONFIDENTIAL – DO NOT COPY Page 8-16 File No. Genesis Workbench is a GUI based tool for defining OSD menus. receiving commands from an external controller. Dithering works by spreading the quantization error over neighboring pixels both spatially and temporally. A parallel port with separate address and data busses is available for this purpose. Both firmware and OSD content must be compiled into a HEX file and then loaded onto the external ROM. This port connects directly to standard.The benefit of dithering is that the eye tends to average neighboring pixels and a smooth image free of contours is perceived.

Figure 8-14 FLI8125 OCM Programming The operation of HDMI Sil9011 The SiI 9011 provides one HDMI input port. SG-0173 . CONFIDENTIAL – DO NOT COPY Page 8-17 File No. The SiI 9011 video output goes to a video processor while the audio output goes to an audio DAC.

The +5V supply from the HDMI connector is used as a cable detect indicator. The microcontroller can also poll registers in the SiI9011 to check whether an HDMI cable is connected.Figure 8-15 HDMI 9011 Block Diagram TMDS Digital Core The core performs 10-to-8-bit TMDS decoding on the audio and video data received from the three TMDS differential data lines along with a TMDS differential clock. SXGA and UXGA. These states are accessible in register bits. The SiI 9011 can monitor the presence of this +5V supply and. The TMDS core supports link clock rates to 165MHz. including CE modes to 720p/1080i/1080p and PC modes to XGA. if and when necessary. CONFIDENTIAL – DO NOT COPY Page 8-18 File No. Active Port Detection The PanelLink core detects an active TMDS clock and detects an actively toggling DE signal. SG-0173 . useful for monitoring the status of the HDMI input or for automatically powering down the receiver. provide a fast audio mute without pops when it senses the HDMI cable pulled.

Therefore the receiver’s firmware will have to program the scaling depending on the detected video format. and directs it to the appropriate logic block. The receiver can also process the video data before it is output. In some applications the 8-bit input range uses the entire span of 0x00 (0) to 0xFF (255) values. and there is no required range specification in the HDMI AVI packet.) Figure 8-16 HDMI Video Processing Path Color Range Scaling The color range depends on the video format. (See page 38 for a more detailed path diagram. When the receiver outputs embedded syncs (SAV/EAV codes). In other applications the range is scaled narrower. it also limits the YCbCr output values to 1 to 254. Refer to the SiI 9011 Programmer’s Reference (SiI-PR-0006) for more details.Data Input and Conversion Mode Control Logic The mode control logic determines if the decrypted data is video. as shown in Figure 5. audio or auxiliary information. The receiver cannot detect the incoming video data range. Each of the processing blocks may be bypassed by setting the appropriate register bits. according to the CEA-861B specification. SG-0173 . Figure 8-17 CONFIDENTIAL – DO NOT COPY Digital Video Output Formats Page 8-19 File No. Video Data Conversion and Video Output The SiI 9011 can output video in many different formats (see examples in Table 2).

7) CONFIDENTIAL – DO NOT COPY Page 9-1 File No.Chapter 9 1. Ripple Voltage Waveforms (1) PDP_+5Vsc (CN1.1) (2) PDP_+12V (CN1. SG-0173 .

SG-0173 .4) (4) FLI8125 (U10) +3.3V_I/O_HUD CONFIDENTIAL – DO NOT COPY Page 9-2 File No.(3) PDP_+5Vsb (CN3.

3V_ADC_HUD +1. SG-0173 .+3.8V_ADC_HUD CONFIDENTIAL – DO NOT COPY Page 9-3 File No.

SG-0173 .8V_ADC CONFIDENTIAL – DO NOT COPY Page 9-4 File No.(5) FLI8532 (U13) +3.3V_I/O +1.

+2.5V_DDR +1. SG-0173 .8V_CORE CONFIDENTIAL – DO NOT COPY Page 9-5 File No.

U17) (7) Am29LV320DT90-ED (XU1) CONFIDENTIAL – DO NOT COPY Page 9-6 File No.(6) NT5DS16M16CS-5T (U16. SG-0173 .

(8) LM2660 (-5V_N of the U29) CONFIDENTIAL – DO NOT COPY Page 9-7 File No. SG-0173 .

Clock Timing (1) NT5DS16M16CS-5T DDR clock (pin 45 of the U16 or U17) (2) FLI8125 Crystal clock (pin 15 of the U10) CONFIDENTIAL – DO NOT COPY Page 9-8 File No.2. SG-0173 .

SG-0173 .Hudson output clock (3) FLI8532 Crystal clock (pin B26 of the U13 or pin 1 of the C155) Cortze output clock CONFIDENTIAL – DO NOT COPY Page 9-9 File No.

SG-0173 .(4) MSP4450G crystal clock (pin 55 of the U32) CONFIDENTIAL – DO NOT COPY Page 9-10 File No.

(5) SiI9011CLU crystal clock (pin 84 of the U35 and U42) (6) IC SM5964C40J crystal clock (pin 20 of the U38) CONFIDENTIAL – DO NOT COPY Page 9-11 File No. SG-0173 .

Timing (1) VGA input (1024x768x60Hz) H-sync CONFIDENTIAL – DO NOT COPY Page 9-12 File No.3. SG-0173 . Horizontal and Vertical sync.

V-sync CONFIDENTIAL – DO NOT COPY Page 9-13 File No. SG-0173 .

(2) SiI9011CLU (U35 and U42) CLK BHS-sync CONFIDENTIAL – DO NOT COPY Page 9-14 File No. SG-0173 .

BVS-sync CONFIDENTIAL – DO NOT COPY Page 9-15 File No. SG-0173 .

SG-0173 .CONFIDENTIAL – DO NOT COPY Page 9-16 File No.

Chapter 10 PDP Trouble Shooting A. SYSTEM OVERVIEW Power supply board X driver board Y driver board Main board Audio Voltage selectior Display board EMI filter Audio power IR board CONFIDENTIAL – DO NOT COPY Page 10-1 File No. SG-0174 .

BOARD PICTURE MAIN BOARD CONFIDENTIAL – DO NOT COPY Page 10-2 File No. AMPLIFIER THE AUDIO SIGNAL TO THE SPEAKER IR BOARD 385000120189 385000120156 RECEIVE THE REMOTE CONTROLER AND DISPLAY SYSTEM STATUS LED DISPLAY BOARD KEYPAD FUNCTION FOR MANUAL OPERATE TV C. PCB PARTS NAME/NUMBER AND FUNCTION DESCRIPTION PART NAME POWER SUPPLY BOARD PART NUMBER FUNCTION DESCRIPTION PROVIDE ALL THE POWER FOR TV SET X ELECTRODE DRIVING BOARD X DRIVER BOARD Y DRIVER BOARD AUDIO POWER SELECTOR Y ELECTRODE DRIVING BOARD AUDIO POWER SUPPLY(+30V OR +24V) MAIN BOARD 385000120150 CONNECTING TO TRANSFER DISPLY SIGNAL TO PDP SET. SG-0174 .B.

SG-0174 .DISPLAY BOARD IR BOARD CONFIDENTIAL – DO NOT COPY Page 10-3 File No.

PDP DISPLAY NOTHING 1. Main board block diagram J9 1 U26 MAX232A ATXD_HUD ARXD_HUD 2 ARXD ATXD_HUD ATXD ARXD_HUD 3 J10 2 1 3 U40 24LC128 EEPROM(8051) UC_SCL/UC_SDA U38 SM5964-C40J HY5DU56822CT-D4 U17 DDR RAM CTZ U20 4052 4/1 x2 I/O HY5DU56822CT-D4 U16 DDR RAM HUD W8 U42 Sil 9011 HDMI RS ADATA[0:23] 51_RXD/51_TXD ARXD ATXD SV4_CTZ SV2_CTZ SV3_CTZ A1_CTZ B1_CTZ C1_CTZ KEY PAD CN5 F75373S U25 風扇控制 CN17 U37 24LC02 EEPROM HDMI1 U35 Sil 9011 HDMI RS BDATA[0:23] SCL-33V / SDA-33V VGA_SCL / VGA_SDA W13 U40 24LC02 EEPROM HDMI2 ANLOG DDC VGA_SCL / VGA_SDA U21 24LC02 EEPROM VGA U45 74HCT14 Inverting Schmitt Trgger NC7SB3157 U18 BUS SW FL8532_CTZ W1 Display VS / HS CN16 R G B U22 M61323FP VEDIO SW XU1 A29LV320D MEMERY_CTZ VGA input W6 U23 M61323FP VEDIO SW ATSC Y Pr Pb ATXD_HUD ARXD_HUD Component 1 W7 Component 2 Y Pr Pb Y Pr Pb U24 M61323FP VEDIO SW FL8125_HUD SV4_HUD SV2_HUD SV3_HUD A1_HUD B1_HUD C1_HUD U11 24LC32 EEPROM HUD U11 SST25VF040 FLASH 512K HUD W11 AudioAV1_R/L CVBS1 W14 CVBS2 AudioAV2_R/L Y1/C1 Y2/C2 W10 U37 CS3443 HDMI2 LR ADC U36 CS3443 HDMI1 LR ADC U46 IDTQS3253 HDMI1 AUDIO SW U42 IDTQS3253 HDMI1 AUDIO SW W5 HDMI1_AUDIO_L/R HDMI2_AUDIO_L/R AudioAV1_R/L AudioAV1_R/L U28 MAX4550 AUDIO SW 4/2 I/O U27 MAX4550 AUDIO SW 4/2 I/O CH4_R/L CH3_R/L Lineout_R/L U33 PT2308 AUDIO DRIVER U34 PT2308 AUDIO DRIVER TDA8946AJ AUDIO_AMP COMP1_Audio_R/L COMP2_Audio_R/L VGA_AUDIO_L/R W13 CH2_R/L CH1_R/L U32 P4450G AUDIO PROCESS HLIN/HRIN W12 CONFIDENTIAL – DO NOT COPY Page10-4 File No. SG-0174 .

CN3’s cable Check main board CN3 pin 4 studyby +5V Check CN3 pin 3 RLY_ON(high) Check CN3 pin 2 VS_ON(high) No Power LED is lighting? Yse Check CN1 pin 1. SG-0174 .D11 LED is lighting? Yes Check U8 1.6 and pin 7.2.3V_SW .8 = +12V No No Yes Panel power fail Check Fuse open? (F2.3 = +5V pin 7.5V No Yes U13 fail If power_off high U2.CN1’s cable 2. No Check W1 pin 27 is high? (Display_ON) No Remove R87. Is AD14 high? No U13 fail Yes No Check internal cable? 1.8) Check U3. Does scaler detect the signal? U13 fail CONFIDENTIAL – DO NOT COPY Page10-5 File No.PDP DISPLAY NOTHING(Analog HD1/AC on/off default) Start No Power LED is lighting? Check AC power cord Yes No Power LED is lighting? Press Meun or Info.R191 Yes 1 No Use GProbe connect from main to PC. Is there any OSD’s logo No Yes Check input source Check internal cable? 1.3V No U3 fail No U8 fail No U9 fail No U2. Check U13 pin AD14.+12V_SW (pin 5.F3.+5V_SW.8V Yes Yes Check U9 2.4 3.LVDS cable.U5 ON Check +3.U5 fail Block 1 PDP DISPLAY NOTHING(Analog HD1 without Y signal) No Is picture on screen? Check component 1 (Y signal) C252 Is there sync? No Trace componect 1 from Input To U13 circuit Check R190.F4) No Fuse fail Yes D10.

Does scaler detect the signal? U13 fail PDP DISPLAY NOTHING(Analog HD1 without Pr signal) BLOCK 1 No Is picture on screen? Check component 1 (Pr signal) C264 Is there sync? No Trace componect 1 from Input To U13 circuit Check R204.R198 Yes No Use GProbe connect from main to PC.PDP DISPLAY NOTHING(Analog HD1 without Pb signal) BLOCK 1 No Is picture on screen? Check component 1 (Pb signal) C259 Is there sync? No Trace componect 1 from Input To U13 circuit Check R196.R201 Yes No Use GProbe connect from main to PC. Does scaler detect the signal? U13 fail PDP DISPLAY NOTHING(Analog HD1 on PIP mode without Y signal) BLOCK 1 No Is picture on screen? Check component 1 (Y signal) =>C255 Is there sync? No Trace componect 1 from Input To U10 circuit Check R193. Does scaler detect the signal? U10 fail 2 CONFIDENTIAL – DO NOT COPY Page10-6 File No.R191 Yes No Use GProbe connect from main to PC. SG-0174 .

R204 Yes No Use GProbe connect from main to PC. Does scaler detect the signal? Yes U13 fail Check before U23’s circuit 1.PDP DISPLAY NOTHING(Analog HD1 on PIP mode without Pb signal) BLOCK 1 No Is picture on screen? Check component 1 (Pb signal) C255 Is there sync? No Trace componect 1 from Input To U10 circuit Check R200.R195 Is there sync? No Yes Check U23 outnput pin 31 Input pin 13 Input clamp voltage pin 3(+5V) Output clamp voltage pin 32(+5V) VCC3 pin 22. Does scaler detect the signal? U10 fail PDP DISPLAY NOTHING(Analog HD1 on PIP mode without Pr signal) BLOCK 1 No Is picture on screen? Check component 1 (Pr signal) C255 Is there sync? No Trace componect 1 from Input To U10 circuit Check R205.C263.23(+5V) Input_switch_select high(+5V) No U23 fail No Use GProbe connect from main to PC. Does scaler detect the signal? U10 fail PDP DISPLAY NOTHING(Analog HD2 without Y signal) BLOCK 1 No Is picture on screen? Check component 2 (Y signal) C258. SG-0174 .C265(AC coupled) 2.R198 Yes No Use GProbe connect from main to PC.R209 3.R216(75ohm) No Input source fail 3 CONFIDENTIAL – DO NOT COPY Page10-7 File No.

SG-0174 . Does scaler detect the signal? Yes U13 fail Check before U23’s circuit 1. Does scaler detect the signal? Yes U13 fail Check before U23’s circuit 1.R218(75ohm) No Input source fail PDP DISPLAY NOTHING(Analog HD2 on PIP mode without Y signal) BLOCK 1 No Is picture on screen? Check component 2 (Y signal) C287.C256.R215 3.R192 Is there signal? No Yes Check U23 outnput pin 34 Input pin 11 Input clamp voltage pin 1(+5V) Output clamp voltage pin 35(+5V) VCC3 pin 22.C261(AC coupled) 2.23(+5V) Input_switch_select high(+5V) No U23 fail No Use GProbe connect from main to PC.R212 Is there sync? No Yes Check U24 outnput pin 31 Input pin 13 Input clamp voltage pin 3(+5V) Output clamp voltage pin 32(+5V) VCC3 pin 22.R211 3.R217(75ohm) No Input source fail PDP DISPLAY NOTHING(Analog HD2 without Pr signal) BLOCK 1 No Is no red color on screen? Check component 2 (Pr signal) C254.23(+5V) Input_switch_select high(+5V) No U24 fail No Use GProbe connect from main to PC. Does scaler detect the signal? Yes U10 fail Check before U24’s circuit 1.C282.C285(AC coupled) 2.PDP DISPLAY NOTHING(Analog HD2 without Pb signal) BLOCK 1 No Is no blue color on screen? Check component 2 (Pb signal) C260.C269(AC coupled) 2.R216(75ohm) No Input source fail 4 CONFIDENTIAL – DO NOT COPY Page10-8 File No.C268.23(+5V) Input_switch_select high(+5V) No U23 fail No Use GProbe connect from main to PC.R209 3.R197 Is there sync? No Yes Check U23 outnput pin 28 Input pin 15 Input clamp voltage pin 5(+5V) Output clamp voltage pin 29(+5V) VCC3 pin 22.

R184 Is there signal? No Check U45 H sync input U45 pin1.C290(AC coupled) 2.PDP DISPLAY NOTHING(Analog HD2 on PIP mode without Pb signal) BLOCK 1 No Is no blue color on screen? Check component 2 (Pb signal) C288.R186. Does scaler detect the signal? Yes U10 fail Check before U24’s circuit 1.C221.C281(AC coupled) 2.R175(75ohm) Pin 6.C276.C241(AC coupled). C239.34 G signal C237. SG-0174 .R169.R171.3V Yes No Yes Check input source U45 fail Check U22’s signal output R signal C238.C234.23(+5V) Input_switch_select high(+5V) No U24 fail No Use GProbe connect from main to PC.R177.R211 3.23(+5V) Input_switch_select high(+5V) No U24 fail No Use GProbe connect from main to PC.R173(75ohm) Yes Check U22 Input clamp voltage pin 1(+5V_V1) Output clamp voltage pin 35(+5V) VCC3 pin 22.R174. Does scaler detect the signal? Yes U10 fail Check before U24’s circuit 1.R172(75ohm) Pin 4.U22.R213 Is there sync? No Yes Check U24 outnput pin 28 Input pin 15 Input clamp voltage pin 5(+5V) Output clamp voltage pin 29(+5V) VCC3 pin 22.R181 V sync output U45 pin8.R210 Is there signal? No Yes Check U24 outnput pin 34 Input pin 11 Input clamp voltage pin 1(+5V) Output clamp voltage pin 35(+5V) VCC3 pin 22.31 B signal C235.C236(AC coupled).28 No R G B Check U22 input signal pin 2.R217(75ohm) No Input source fail PDP DISPLAY NOTHING(Analog HD2 on PIP mode without Pr signal) BLOCK 1 No Is no red color on screen? Check component 2 (Pr signal) C284.C224(AC coupled).R176.C289.R218(75ohm) No Input source fail PDP DISPLAY NOTHING(RGB) BLOCK 1 No Is picture on screen? Check U45 H sync output U45 pin4.R180.R164.R166.R215 3.R187 Yes Check U45 pin 14 +3.U22.23(+5V) Input_switch_select low (0V) No U22 fail 5 CONFIDENTIAL – DO NOT COPY Page10-9 File No.U22.R185 V sync input U45 pin5.

R181 V sync output U45 pin8.R173(75ohm) Yes Check U22 Input clamp voltage pin 1(+5V_V1) Output clamp voltage pin 35(+5V) VCC3 pin 22.R171.C241(AC coupled).23(+5V) Input_switch_select low (0V) No U22 fail 6 CONFIDENTIAL – DO NOT COPY Page10-10 File No.31 B signal C231.U22.C224(AC coupled).U22. SG-0174 .R169.C234.C236(AC coupled).R166.R176.R185 V sync input U45 pin5.R184 Is there signal? No Check U45 H sync input U45 pin1.R174. C239.U22.R180.R175(75ohm) Pin 6.34 G signal C232.PDP DISPLAY NOTHING(RGB on PIP mode without screen) BLOCK 1 No Is picture on screen? Check U45 H sync output U45 pin4.R172(75ohm) Pin 4.3V Yes No Yes Check input source U45 fail Check U22’s signal output R signal C233.R187 Yes Check U45 pin 14 +3.R186.C221.28 No R G B Check U22 input signal pin 2.R177.R164.

R276 3.R273. SG-0174 . Is there signal? No Check Q28’s Base.R276 3. Is there signal? No Check Q28’s Base.PDP DISPLAY NOTHING(Composite 1 without screen) BLOCK 1 No Is picture on screen? Check C310.R279(75ohm impedance) Is there signal? No Check input source 7 CONFIDENTIAL – DO NOT COPY Page10-11 File No. Is there signal? Check collector voltage(+5V). No Q28 fail Use GProbe connect from main to PC. Does scaler detect the signal? No Q13 fail Yes Check: 1.C309 (signal AC coupled) 2. No Q28 fail Use GProbe connect from main to PC. Is there signal? Check collector voltage(+5V).R279(75ohm impedance) Is there signal? No Check input source PDP DISPLAY NOTHING(Composite 1 on PIP without screen) BLOCK 1 No Is picture on screen? Check C308.C309 (signal AC coupled) 2.R275. Does scaler detect the signal? No Q10 fail Yes Check: 1.R274 Is there signal? Yes No Check Q28’s emitter.R274 Is there signal? Yes No Check Q28’s emitter.

R282 3. SG-0174 . Is there signal? Check collector voltage(+5V). Is there signal? Check collector voltage(+5V).R283(75ohm impedance) Is there signal? No Check input source 8 CONFIDENTIAL – DO NOT COPY Page10-12 File No.R286. Is there signal? No Check Q29’s Base.R284.C315 (signal AC coupled) 2. No Q29 fail Use GProbe connect from main to PC.R285 Is there signal? Yes No Check Q29’s emitter. Does scaler detect the signal? No Q10 fail Yes Check: 1. Is there signal? No Check Q29’s Base. No Q29 fail Use GProbe connect from main to PC.R282 3.R283(75ohm impedance) Is there signal? No Check input source PDP DISPLAY NOTHING(Composite 2 on PIP without screen) BLOCK 1 No Is picture on screen? Check C316.R285 Is there signal? Yes No Check Q29’s emitter.C315 (signal AC coupled) 2.PDP DISPLAY NOTHING(Composite 2 without screen) BLOCK 1 No Is picture on screen? Check C316. Does scaler detect the signal? No Q13 fail Yes Check: 1.

Is there signal? Check collector voltage(+5V). No Q31 fail Use GProbe connect from main to PC.R298(75ohm impedance) Is there signal? No Check input source 9 CONFIDENTIAL – DO NOT COPY Page10-13 File No.R293.R307 Is there signal? Yes No Check Q31’s emitter. SG-0174 .C319 (signal AC coupled) 2. Is there signal? No Check Q31’s Base.C327 (signal AC coupled) 2.PDP DISPLAY NOTHING(S-VIDEO 1 without screen) BLOCK 1 No Is picture on screen? Check C320.R297 3.R292 Is there signal? Yes No Check Q30’s emitter.R299(75ohm impedance) Is there signal? No Check input source No Is picture color ok? Check C328. Does scaler detect the signal? No Q13 fail Yes Check: 1. Does scaler detect the signal? No Q13 fail Yes Check: 1.R308.R296 3. Is there signal? Check collector voltage(+5V). No Q30 fail Use GProbe connect from main to PC. Is there signal? No Check Q30’s Base.

Is there signal? No Check Q30’s Base.C319 (signal AC coupled) 2. Is there signal? Check collector voltage(+5V).PDP DISPLAY NOTHING(S-VIDEO 1 on PIP mode without screen) BLOCK 1 No Is picture on screen? Check C318. SG-0174 .R298(75ohm impedance) Is there signal? No Check input source 10 CONFIDENTIAL – DO NOT COPY Page10-14 File No.R291.R297 3. Is there signal? Check collector voltage(+5V).C327 (signal AC coupled) 2.R306. No Q30 fail Use GProbe connect from main to PC.R296 3. No Q31 fail Use GProbe connect from main to PC. Is there signal? No Check Q31’s Base.R299(75ohm impedance) Is there signal? No Check input source No Is picture color ok? Check C326.R292 Is there signal? Yes No Check Q30’s emitter.R307 Is there signal? Yes No Check Q31’s emitter. Does scaler detect the signal? No Q10 fail Yes Check: 1. Does scaler detect the signal? No Q10 fail Yes Check: 1.

C333 (signal AC coupled) 2. Is there signal? Check collector voltage(+5V).R316. Does scaler detect the signal? No U13 fail Yes Check: 1. Is there signal? No Check Q32’s Base. Is there signal? No Check Q33’s Base.R302(75ohm impedance) Is there signal? No Check input source No Is picture color ok? Check C336.R319. No Q32 fail Use GProbe connect from main to PC.R320 Is there signal? Yes No Check Q33’s emitter.PDP DISPLAY NOTHING(S-VIDEO 2 without screen) BLOCK 1 No Is picture on screen? Check C332.R301 3.C335 (signal AC coupled) 2. No Q33 fail Use GProbe connect from main to PC.R300 3. SG-0174 .R303(75ohm impedance) Is there signal? No Check input source 11 CONFIDENTIAL – DO NOT COPY Page10-15 File No.R318 Is there signal? Yes No Check Q32’s emitter. Does scaler detect the signal? No U13 fail Yes Check: 1. Is there signal? Check collector voltage(+5V).

R301 3.C335 (signal AC coupled) 2.R318 Is there signal? Yes No Check Q32’s emitter.PDP DISPLAY NOTHING(S-VIDEO 2 on PIP mode without screen) BLOCK 1 No Is picture on screen? Check C331. Is there signal? No Check Q32’s Base.R303(75ohm impedance) Is there signal? No Check input source 12 CONFIDENTIAL – DO NOT COPY Page10-16 File No. Does scaler detect the signal? No U10 fail Yes Check: 1. No Q33 fail Use GProbe connect from main to PC. Is there signal? Check collector voltage(+5V). Does scaler detect the signal? No U10 fail Yes Check: 1. SG-0174 .R302(75ohm impedance) Is there signal? No Check input source No Is picture color ok? Check C334.R317. Is there signal? No Check Q33’s Base.R300 3.R313. Is there signal? Check collector voltage(+5V).C333 (signal AC coupled) 2. No Q32 fail Use GProbe connect from main to PC.R320 Is there signal? Yes No Check Q33’s emitter.

FB20.RP11 G RP12.FB21.8V_HDMI1 Yes Check crystal Y2=28.FB22 U41 +1.RP17 14 CONFIDENTIAL – DO NOT COPY Page10-17 File No.3V) Yes Check U35 I2C bus CSDA pin 39 CSCL pin 40 Yes No Check Q44 Gata high(5V) No Q44 fail No I2C addr.322MHz Yes Check Q44 source high(3.RP14 R RP16.PDP DISPLAY NOTHING(Digital 2 U35 with PORT B without screen) BLOCK 1 No Is picture on screen? Check input source? Yes Check U37 I2C bus SCL Pin 6 SDA pin 5 No Check U37 power 5V Pin 8 No Check D66 and D65 Are there 5V output? No D66 fail or D65 fail No Is picture on screen? Check U35 pin 90 high V sync R419 H sync R420 clock R421 No Check +3.3V_SW FB19. SG-0174 . R424 No Check Block 2 Yes Check U35 all power U35 fail No Is picture color ok? Check U35’s RGB data bus B RP10.

is ok? No Check U38’s power Pin 44.Block 2 start HDMI’s chip communicate with SM5964.35 Yes No Check U2’s +5V_SW pin 7.8 Check Y3 11.0592MHz Yes No Pin 10 Check U38’s UART TxD pin 13 RxD pin 11 Check U20 pin 16 +5V output select=high Yes No U20 fail No Check R143. SG-0174 .R144 U13 fail 15 CONFIDENTIAL – DO NOT COPY Page10-18 File No.

Is compliant protocol? End CONFIDENTIAL – DO NOT COPY Page10-19 File No.Is compliant protocol? Yes Support DDC2B 1.TROUBLE OF DDC READING Start No Analog DDC OK? Support DDC2B 1.Voltage of +5V_BUF ok? 3. SG-0174 .Check U44 4.HDMI cable ok? 2.Check U21 4.Voltage of VCC5_E2P_1 ok? 3.Analog cable ok? 2.HDMI cable ok? 2.Check U37 4.Is compliant protocol? No Digital HDMI1 DDC OK? Yes No Digital HDMI2 DDC OK? Support DDC2B 1.Voltage of VCC5_E2P_2ok? 3.