Pollachi Institute of Engineering and Technology

Pollachi – 645 205

Academic Year 2017-18 (ODD Semester)
Department of Electronics and Communication Engineering
Lesson Plan
Name of the Course / Programme : B.E/ECE
Class : IV ECE
Subject Code /Title : EC6009/ Advanced Computer Architecture
Name of the Faculty member : Ms.B.MENAKADEVI

Date Initial of
Text / Ref Date of No of Teaching Cumulative Initial Initial of
Lecture (Period) of the
Topics to be covered book Page Lecture Periods aids / Number of of the the
Hours Lecture Faculty
No. Planned Planned Remarks period(s) HOD Principal
delivered Member

UNIT – I FUNDAMENTALS OF COMPUTER DESIGN

1. Review of Fundamentals of
CH1 :2-4 12/07/17 1 PPT 1
CPU
2. Memory and IO CH1 :5-7 13/07/17 1 PPT 2
3. Trends in technology CH1 :8 14/07/17 1 BB 3

4. Trends in technology in terms

CH1 :9 17/07/17 1 BB 4
of power

5. Trends in technology in terms

CH1 :10-12 19/07/17 1 BB 5
of energy and cost

6. Dependability of computer
CH1 :12-14 20/07/17 1 BB 6
design
7. Performance evaluation of
CH1 :16 21/07/17 1 BB 7
computer design

8. Review I - 22/07/17 1 BB 8

UNIT- II INSTRUCTION LEVEL PARALLELISM

9. ILP concepts CH2:2-15 22/07/17 Unit1 - 1 BB 9

10. Pipelining overview CH2:16 24/07/17 1 BB 10

Compiler Techniques for
11. CH2:18 26/07/17 1 BB 11
Exposing ILP
PPT
12. Dynamic Branch Prediction CH2:20-23 27/07/17 1 12

PPT
13. Dynamic Scheduling CH2:26 28/07/17 1 13

14. Multiple instruction Issue CH2:28 29/07/17 1 BB 14

15. Hardware Based Speculation CH2:30 29/07/17 1 BB 15

16. Static scheduling CH2:35-37 31/07/17 1 BB 16

17. Multi-threading CH2:41 04/08/17 1 BB 17

Limitations of ILP-Case
18. CH2:42-44 05/08/17 1 BB 18
Studies
19. Review II CH2:45 05/08/17 1 PPT 19

UNIT – III DATA-LEVEL PARALLELISM

Vector architecture -
20. CH3:16 07/08/17 1 PPT 20
Introduction

Vector architecture and its CH3:17

21. 09/08/17 1 BB 21
types
 PPT
22. SIMD extensions CH3:5 10/08/17 1 22
PPT
23. SIMD extensions procedure CH3:7-9 11/08/17 1 23

24. Graphics Processing units CH3:19 12/08/17 1 BB 24

25. Graphics Processing units CH3:19 12/08/17 1 BB 25

26. Loop level parallelism. CH3:24 16/08/17 1 BB 26

Loop level parallelism with

27. CH3:26 17/08/17 1 BB 27
some examples

28. Review III - 18/08/17 1 PPT 28

UNIT – IV THREAD LEVEL PARALLELISM

29. Symmetric Shared Memory

CH4:5-13 21/08/17 1 PPT 29
Architectures
Distributed Shared Memory
30. CH4:15-17 23/08/17 1 BB 30
Architectures
31. Performance Issues CH4:20 24/08/17 1 BB 31

32. Synchronization CH4:21-24 26/08/17 1 BB 32

Models of Memory
33. CH4:25-27 26/08/17 1 PPT 33
Consistency

34. Case studies: Intel i7 Processor CH4:29 28/08/17 1 PPT 34

35. SMT Processors CH4:32 30/08/17 1 BB 35

36. CMP Processors CH4:34 31/08/17 1 BB 36
 37. Review IV - 01/09/17 1 BB 37

UNIT – V MEMORY AND I/O

38. Cache Performance CH5:8 04/90/17 1 BB 38

39. Reducing Cache Miss Penalty CH5:8 09/09/17 1 BB 39

40. Reducing Cache Miss Rate CH5:9 09/09/17 1 BB 40

41. Reducing Hit Time CH5:10 11/09/17 1 BB 41

Main Memory and
42. CH5:15-19 13/09/17 1 PPT 42
Performance
43. Memory Technology CH5:21 14/09/17 1 PPT 43

44. Types of Storage Devices CH5:23-26 15/09/17 1 BB 44

45. Buses CH5:27-30 18/09/17 1 PPT 45

46. RAID CH5:34-40 20/09/17 1 BB 46

Reliability, Availability and

47. CH5:40 21/09/17 1 BB 47
Dependability
48. I/O Performance Measures CH5:42 22/09/17 1 BB 48

49. Review V - 23/09/17 1 PPT 49

Total No of Periods = 45 (49 Hours)

Content beyond the Syllabus

1. Parallel processing challenges.
2. Flynn's classification
Text Books:
1. John L Hennessey and David A Patterson, “Computer Architecture A Quantitative Approach”, Morgan Kaufmann/ Elsevier,
Fifth Edition, 2012.
.

Reference Books:
1. Kai Hwang and Faye Briggs, “Computer Architecture and Parallel Processing”, Mc Graw- Hill International Edition, 2000.
2. Sima D, Fountain T and Kacsuk P, ”Advanced Computer Architectures: A Design Space Approach”, Addison Wesley, 2000

Faculty In-Charge HoD/ ECE Principal

(Ms.B.Menakadevi) (Dr.K.P.Dhanabalakrishnan)