In this paper, we present a multiprecision (MP) reconfigurable multiplier that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. Previous paper in used the PLL for the frequency division. If use the PLL for frequency division its hardware complexity increases .If frequency division is done by software using some frequency division method means hardware complexity is decrease and also speed is increases. All of the building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision multiplications. Given the userâ€™s requirements (e.g. throughput) a dynamic voltage/frequency scaling management unit configures the multiplier to operate at the proper precision and frequency.
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- Multi-precision Multiplier

In this paper, we present a multiprecision (MP) reconfigurable multiplier that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. Previous paper in used the PLL for the frequency division. If use the PLL for frequency division its hardware complexity increases .If frequency division is done by software using some frequency division method means hardware complexity is decrease and also speed is increases. All of the building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision multiplications. Given the userâ€™s requirements (e.g. throughput) a dynamic voltage/frequency scaling management unit configures the multiplier to operate at the proper precision and frequency.
https://journalnx.com/journal-article/20150036

© All Rights Reserved

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VESCOMM-2016

4th NATIONAL CONFERENCE ON “RECENT TRENDES IN VLSI, EMBEDED SYSTEM, SIGNAL PROCESSING AND COMMUNICATION

In Association with “The Institution of Engineers (India)” and IJRPET

February 12th, 2016

MODIFIED INPUT SCANNING METHOD USED TO 32 BIT X 32 BIT

MULTIPRECISION MULTIPLIER

Miss.Bhosale Shubhangi A. Prof.Mantri D.B.

Department of Electronics & Telecommunication Department of Electronics & Telecommunication

VVPIET, Solapur, MS, India VVPIET, Solapur, MS, India

shubhangibhosale@gmail.com dbmantri@yahoo.co.in

Abstract-In this paper, we present a multiprecision low power consumption as well as high speed. There is wide

(MP) reconﬁgurable multiplier that incorporates variable range of multipliers. Based on the way the data is processed,

precision, parallel processing (PP), razor-based dynamic they are classified as serial, parallel and serial-parallel

voltage scaling (DVS), and dedicated MP operands scheduling multipliers.

to provide optimum performance for a variety of operating Therefore, it is crucial to develop a multiplier with

conditions. Previous paper in used the PLL for the frequency high performance but low power consumption. Multiplier is

division. If use the PLL for frequency division its hardware typically designed for a fixed maximum word-length to suit

complexity increases .If frequency division is done by the worst case scenario. However, the real effective word-

software using some frequency division method means lengths of an application vary dramatically. The use of a non-

hardware complexity is decrease and also speed is increases. proper word-length may cause performance degradation or

All of the building blocks of the proposed reconﬁgurable inefficient usage of the hardware resources. In addition, the

multiplier can either work as independent smaller-precision minimization of the multiplier power budget requires the

multipliers or work in parallel to perform higher-precision estimation of the optimal operating point including clock

multiplications. Given the user’s requirements (e.g. frequencies, supply voltage, and threshold voltage [2].In most

throughput) a dynamic voltage/frequency scaling management VLSI system designs, the supply voltage is also selected based

unit conﬁgures the multiplier to operate at the proper precision on the worst case scenario. In order to achieve an optimal

and frequency. power/performance ratio, a variable precision data path

Keywords- Computer arithmetic, dynamic voltage scaling, solution is needed to cater for various types of applications.

low power design, multi-precision multiplier. Dynamic Voltage Scaling (DVS) can be used to match the

circuit’s real working load and further reduce the power

I. INTRODUCTION consumption.

Nowadays, the demand for low power, high II. HISTORY

performance portable devices has been greatly increased. The An 8-bit multiplication computed on a 32-bit Booth

growing market of portable electronic systems demands multiplier would result in unnecessary switching activity and

microelectronic circuits design with low power dissipation. power loss. Many analyzed this word length optimization.

The power dissipation mainly due to internal components [1]. They proposed an ensemble of multipliers of different

In Digital Signal Processing applications, most frequently precisions, with each optimized for a particular scenario. Each

used arithmetic operation is multiplication. So Multipliers play pair of incoming operands is routed to the smallest multiplier

an important role in today’s digital signal processing and that can give the result to take advantage of the lower energy

various other applications. With advances in technology, the consumption of the smaller circuit. This ensemble the systems

following design targets – high speed, low power consumption is reported to consume the low power but this came at the

and hence less area or even combination of them in one high cost, chip area given the used ensemble structure. To

multiplier thus making them suitable for various high speed, address this issue, [3] proposed to share and reuse some

low power VLSI implementation. functional modules within the ensemble. In [3], an 8-bit

Multipliers used in these applications have large area multiplier is reused for the 16-bit multiplication, adding

and consume considerable power. Therefore design of low- scalability without large area penalty. Extended this method

power multiplier has been an important part in low- power by implementing pipelining to further improve the multiplier’s

VLSI system design. A multiplier is an important part of performance. Combining multi-precision (MP) [1] with

digital signal processing systems, like frequency domain dynamic voltage scaling (DVS) can provide a reduction in

filtering (FIR and IIR), frequency-time transformations (FFT), power consumption. In proposed technique twin-precision is

Correlation, Digital Image processing etc. Multipliers have used rather than multi-precision array multiplier. Power and

large area, long latency and consume considerable power. delay is reduced dramatically than multi-precision multiplier.

While many previous works focused on implementing high- Due to the complex structure and interconnections, multipliers

speed multipliers, recently there have been many attempts to have large amount of unbalanced path which causes unwanted

reduce power consumption. This is due to the increased signal generation and propagation. This can be avoided by

demand for portable multimedia applications, which require proper internal balancing through architectural and transistor

1

Proceedings of

VESCOMM-2016

4th NATIONAL CONFERENCE ON “RECENT TRENDES IN VLSI, EMBEDED SYSTEM, SIGNAL PROCESSING AND COMMUNICATION

In Association with “The Institution of Engineers (India)” and IJRPET

February 12th, 2016

level optimization.in most cases of multipliers, maximum All the five building blocks are working together to perform

word length is provided. Hence small multiplications are done multiplication with variable precision. Input operands are

in large multipliers, this causes unwanted switching activity given through IOS blocks which rearrange the inputs to

and also power consumption. So word length optimization is reduce voltage transitions and given to the MP multiplier.

the best method in which 8-bit multiplier is reused for 16-bit This multiplier initially works at standard supply voltage of

and 32- bit multiplication. Here it is possible to incorporate the 3.3v. Since LUT stores the minimum voltage for each

pipelining for increasing the speed of the multiplier. combinations, depending on the incoming operands precision

In conventional DVS technique, LUT tunes to supply adjust the input voltage suitable for that particular

voltages which are stored as predefined voltage and frequency combination.

relationship by considering all worst case conditions. It will

consume more time and area. In razor based DVS technique,

minimum voltage required for multiplication is found using

razor based feedback and also many voltage transitions

occurred during the calculation of particular product.

Due to this voltage transitions power consumptions

and delay for product calculation is also increases. Because of

dynamic voltage scaling unit, increased number of

preemptions and frequency switching occurs which leads to

worst case power consumption and delay and did not get

optimum performance at various operating conditions. The

previous work has many drawbacks. It takes more time for

calculation of particular products and increased number of

hardware components causes increased power consumption. Fig-2: Possible configuration modes of MP multiplier

III PROPOSED TECHNOLOGY Fig 2 shows the proposed multiplier which consists

Fig.1 shows over all multiplier system architecture. nine 8x 8 bit multipliers. All these multipliers perform

The overall multiplier system mainly consists mainly 5 units. individual 8x8 bit operation and also can perform parallel

1) input operand scheduler which rearranges the input data and multiplication for 16-bit and 32-bit multiplication. The

hence reduce the supply voltage transition, thus power processing elements of multiplier can either work as 9

consumption will be reduced. independent multipliers or work in parallel to form 1, 2, or

2) MP multiplier is one which performs multiplication with three 16 x 16 bit multiplier or a single 32- bit multiplication

variable precision and parallel processing. operation.

3) Look Up Table is like a storage element used to store The pipelining method reduces delay and also gets

voltage required for multiplication. fast multiplication result without error. Parallel processing is

4) Frequency scaling unit (FSU) which provides required the ability of a device to simultaneously process incoming

frequency for the multiplication. different inputs. Pipelining increases instruction throughput

5) voltage and frequency management unit (VFMU) which is by performing multiple operations at the same time

receives user requirement and control the LUT and FSU by (concurrently), but does not reduce instruction latency (the

giving suitable voltage and frequency for proper operation of time to complete a single instruction from start to finish) as it

MP still must go through all the steps.

multiplier. IV. MP RECONFIGURABILITY AND OVERHEAD

The structure of the input interface unit, which is a

sub module of the MP multiplier as shown in Fig.2. The role

of this input interface unit is to distribute the input data

between the nine independent processing elements (PEs) of

the 32 × 32 bit MP multiplier, considering the selected

operation mode. The input interface unit uses an extra MSB

sign bit to enable both signed and unsigned A 3-bit control

bus indicates whether the inputs are 1/4/9 pair(s) of 8-bit

operands, or 1/2/3 pair(s) of 16-bit operands, or 1 pair of 32-

bit operands, respectively. Depending on the selected

operating mode, the input data stream is distributed between

the PEs to perform the computation. Fig. 2shows how three

8 × 8 bit PEs are used to realize a 16 × 16 bit multiplier. The

32 × 32 bit multiplier is constructed using a similar approach

Fig-1: Overall Multiplier System Architecture but requires 3 × 3 PEs. A 3-bit control word defines which

PEs work concurrently and which PEs are disabled.

2

Proceedings of

VESCOMM-2016

4th NATIONAL CONFERENCE ON “RECENT TRENDES IN VLSI, EMBEDED SYSTEM, SIGNAL PROCESSING AND COMMUNICATION

In Association with “The Institution of Engineers (India)” and IJRPET

February 12th, 2016

supply voltage and the clock frequency may be scaled down

according to the actual workload.

V METHODOLOGY

In block diagram consist of input operands

schedeler,frequency voltage management unit, voltage scaling

unit, frequency scaling unit, multiprecision multiplier.in this

paper only focus on frequency division module .

The clk is the main frequency and fsel is the control signal.

Out is output signal.

If we select 01 mean frequency is f/4 its use for 8x8 bits

multiplier.

If we select 10 mean frequency is f/2 its use for 16x16 bits

multiplier.

If we select 11 mean frequency is f its use for 32x32 bits

multiplier.

RESULT

1] First input:

first select the selmud=0 and give input value to in32=56;

after change the value of selmud=1 and again give the value to

Fig 3.Overall multiplier system architecture in32=135;the output is generate control signal=1 and k3=56

VI Frequency division and k33=135 because both value of in32 is less than 256

In this paper use the three multiprecision multiplier like that’s via output is generate like that.

8x8bits,16x16bits and 32x32bits.The 8x8bits multiplier

required less frequency as compare to the 16x16 bits 2] Second input:

multiplier and 16x16bits multiplier required less frequency as first select the selmud=0 and give input value to in32=2456;

compare to 32x32bits multiplier. If 32x32bits multiplier after change the value of selmud=1 and again give the value to

require f frequency then 16x16bits require f/2 and 8x8bits in32=756;the output is generate control signal=2 and

require f/4 frequency. k2=2456 and k22=756 because both value of in32 is less than

In Previous paper used the PLL circuit for the frequency 32768 that’s via output is generate like that.

division it’s very complex hardware, in this paper we replace

the PLL by softwarlly frequency division module. In this 3] Third input:

module we use the f frequency as the circuit frequency and is First select the selmud=0 and give input value to

divide into the f/2,f4. in32=3562145; after change the value of selmud=1 and again

Below is the schematic diagram of the frequency division give the value to in32=249632166;the output is generate

module. The main frequency is divide into the f/2,f/4 control signal=3and k1=3562145 and k11=249632166because

according to the control signal its generate from input operand both value of in32 is greater than 32768 that’s via output is

scheduler. generate like that.

3

Proceedings of

VESCOMM-2016

4th NATIONAL CONFERENCE ON “RECENT TRENDES IN VLSI, EMBEDED SYSTEM, SIGNAL PROCESSING AND COMMUNICATION

In Association with “The Institution of Engineers (India)” and IJRPET

February 12th, 2016

Here we present a Modified Input Scanning Method Used to

32 bit x 32 bit Multiprecision Multiplier. Further we are

going to study a multiprecision (MP) reconﬁgurable multiplier

that incorporates variable precision, parallel processing (PP),

razor-based dynamic voltage scaling (DVS), and dedicated

MP operands scheduling to provide optimum performance for

a variety of operating conditions.

REFERENCES

[1] Xiaoxiao Zhang, and Amine Bermak,”32 Bit×32 Bit

Multiprecision Razor-Based DynamicVoltage Scaling

Multiplier With Operands Scheduler”,IEEE Trans. Very Large

ScaleIntegr. (VLSI) Syst., vol. 22, no. 4,Apr 2014.

IEEE,”32 Bit×32 Bit Multiprecision Razor-Based Dynamic

Voltage Scaling Multiplier With Operands Scheduler” IEEE

Transactions On Very Large Scale Integration (Vlsi) Systems,

Vol. 22, No. 4, April 2014 759. [3] Shyamal pampattiwar

“literature survey on NFC, applications”IJSER feb-2012.

study between static and dynamic sleep signal generation

techniques for leakage tolerant designs,” IEEE Trans. Very

Large Scale Integration multiplier,” IEEE Trans. Circuits Syst.

I, Reg. Papers, vol. 57,no. 3, pp. 568–580, Mar. 2010.

4

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