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# UNIT II COMBINATIONAL CIRCUITS

COMBINATIONAL CIRCUITS

1. Combinational LOGIC CIRCUITS: 2. Sequential

Combinational logic circuits (circuits without a memory): Combinational switching networks whose outputs depend only on the current inputs. Sequential logic circuits (circuits with memory): In this kind of network, the outputs depend on the current inputs and the previous inputs. These networks employ storage elements and logic gates.

COMBINATIONAL CIRCUITS

Most important standard combinational circuits are: • Adders • Subtractors • Comparators • Decoders • Encoders • Multiplexers

Available in IC’s as MSI and used as standard cells in complex VLSI (ASIC)

**ANALYSIS OF COMBINATIONAL LOGIC
**

= ABC

= T3 + T2

= A+ B+C

= F2 'T1

= AB + AC + BC

**ANALYSIS OF COMBINATIONAL LOGIC
**

F1 = T3 + T2 = F2 ' T1 + ABC = ( AB + AC + BC )' ( A + B + C ) + ABC = ( A'+ B' )( A'+C ' )( B'+C ' )( A + B + C ) + ABC = ( A'+ B' C ' )( AB'+ AC '+ BC '+ B' C ) + ABC = A' BC '+ A' B' C + AB' C '+ ABC

F2 = AB + AC + BC

**ANALYSIS OF COMBINATIONAL LOGIC
**

Inputs INPUTS A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Outputs OUTPUTS F1 0 1 1 0 1 0 0 1 F2 0 0 0 1 0 1 1 1

From the truth table can you tell the function of the circuit?

**DESIGN OF COMBINATIONAL LOGIC
**

1. From the specifications of the circuit, determine the number of inputs and outputs 2. Derive the truth table that defines the relationship between the input and the output. 3. Obtain the simplified Boolean function using x-variable K-Map. 4. Draw the logic diagram and verify the correctness of the design.

**DESIGN OF COMBINATIONAL LOGIC
**

Example: Design a combinational circuit with three inputs and one output. The output is a 1 when the binary value is less than three. The output is 0 otherwise.

x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F 1 1 1 0 0 0 0 0

yz 00 0 x 1

y 01 11 10

1

1

1

F = x' y '+ x' z '

z

x y F

z

**BINARY ADDER – Half Adder
**

A 0 1 0 1 B 0 0 1 1 O 0 1 1 0 C 0 0 0 1

**BINARY ADDER - Full Adder
**

Inputs INPUTS A B C

0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

Outputs OUTPUTS F1 F2

0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1

C

Full Adder in SOP

**Implementation Full Adder with two half Adders
**

S = z ⊕ ( x ⊕ y) = z ' ( xy '+ x' y ) + z ( xy '+ x' y )' = z ' ( xy '+ x' y ) + z[( x'+ y )( x + y ' )] = z ' ( xy '+ x' y ) + z ( x' y '+ xy ) = xy'z' + x'yz '+ xyz + x' y ' z

**CASCADE 4-BIT FULL ADDER
**

3

0 1 0 1 0

2

1 0 0 1 0

1

1 1 1 1 1

0

0 1 1 0 1

i

Ci Ai Bi Si Ci+1

Carry Propagation

Addition of two numbers in parallel implies that all bits are available for computation. Total propagation delay = propagation delay of a gate × # gate levels

available only after C3 has propagated through

Carry Propagation

Q: Find the total C propagation delay in the 4-bit full adder circuit.

Carry Propagation

The carry propagation time is a limiting factor on the speed with which two numbers are added. The most widely technique for reducing the carry propagation time in a parallel adder uses the principle of carry lookahead.

Carry Propagate Pi = Ai ⊕ Bi Carry Generate

Si = Pi ⊕ Ci Ci +1 = Gi + Pi Ci

Gi = Ai Bi

**Carry Lookahead Generator
**

C0 = input carry C1 = G0 + P0C0 C2 = G1 + P C1 = G1 + P (G0 + P0C0 ) = G1 + P G0 + P P0C0 1 1 1 1 C3 = G2 + P2C2 = G2 + P2G1 + P2 P G0 + P2 P P0C0 1 1

4-bit Adder with Carry Lookahead

Q: What is the propagation delay?

Binary Subtractor

The subtraction of unsigned binary numbers can be done by complements. Review complements: 1’s complement of N = (2n-1) – N (N is a binary #) 1’s complement can be formed by changing 1’s to 0’s and 0’s to 1’s 2’s complement of a number is obtained by leaving all least significant 0’s and the first 1 unchanged, and replacing 1’s with 0’s and 0’s with 1 in all higher significant digits. Taking the 1’s complement and adding 1 to the least significant bit in the number.

**‘Programmable’ Binary Adder/Subtractor
**

Control M controls the the operation (addition or subtraction) M = 0 Adder: A plus B, C0 = 0 B ⊗ 0 = ( B ⋅1) + ( B'⋅0) = B M = 1 Adder: A plus 2’s complement and a C0 = 1 A - B M = 1: B ⊗ 1 = ( B ⋅ 0) + ( B'⋅1) = B '

Overflow

Overflow occurs when two numbers of n digits are added and the sum occupies n +1 digits.

If V = 0 no overflow: n-bit results is correct. If V = 1 overflow: The result contains n + 1 bits, and the (n+1)th bit is the actual sign.

V = C3 ⊗ C 4

Binary Multiplier

Multiplication of binary numbers is done in the same way as decimal numbers. Multiplicand B is multiplied by the multiplier A starting from the LSB. Successive partial products are shifted one position from the left and the final product is obtained from the sum of partial products.

HA is used because there are more bits in the partial product. The LSB is formed by the output of the first AND and doesn’t need to go through the HA.

4-Bit by 3-Bit Binary Multiplier

JxK J x K AND gates (J-1) K-bit adders Result: J + K bits

Magnitude Comparator

A magnitude comparator is a combinational circuit that compares two numbers, A and B, and then determines their relative magnitudes. A>B A=B A<B Algorithm Consider two numbers, A and B, with four digits each:

A = A3 A2 A1 A0 B = B3 B2 B1 B0

xi = Ai Bi + Ai ' Bi ' for i = 0, 1, 2, 3 XNOR xi = 1 if A = B = 0 or A = B = 1 For equality to exist, all xi variables must be equal to 1: ( A = B) = x3 x2 x1 x0 → AND operation

Magnitude Comparator

To determine if A is greater than or less than B, we inspect the relative magnitudes of significant digits. If the two digits are equal, we compare the next lower significant pair of digits. The comparison continues until a pair of unequal digits is reached. The sequential comparison can be expressed by:

' ' ( A > B ) = A3 B3' + x3 A2 B2 + x3 x2 A1 B1' + x3 x2 x1 A0 B0 ' ' ( A < B) = A3' B3 + x3 A2 B2 + x3 x2 A1' B1 + x3 x2 x1 A0 B0

Compare: A = 1010 and B = 0101 → ( A > B ) = 1

A = 0101 and B = 1010 → ( A < B) = 1

4-bit Magnitude Comparator

XNOR

' ' = A3' B3 + x3 A2 B2 + x3 x2 A1' B1 + x3 x2 x1 A0 B0

' ' = A3 B3' + x3 A2 B2 + x3 x2 A1 B1' + x3 x2 x1 A0 B0

= x3 x2 x1 x0