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ECE6421 Homework 3

R, L, C, Inverter and Gate Delay Due 10/07 in class

1. For the inverter in the figure below, with an output load of 3pF and 0.25 um technology.

a. Calculate tpHL, tpLH, and tp.

b. Are the rising and falling delays equal? Why and why not?

Answer: During the pull-down (discharging) process, the NMOS M1 is beginning from

saturation mode. Vout begins from VDD and decreases. At this point,

1 W 1 1.5

I dn = kn n (VDD − VTn ) 2 = ×115 × × (2.5 − 0.43)2 = 739.1452 µ A

2 Ln 2 0.5

V

Req 0 = DD = 3.3823K Ω

I dn

VDD

When Vout = , the discharging process is ended. At this point, M1 is in linear region. Thus:

2

VDD − Vout = I RL × RL = Idn 1 × RL

and

Wn VDS2 Wn Vout2

I dn1 = kn (V − V

DD Tn DS )V − =

n k (V − V )V

DD Tn out −

Ln 2 Ln 2

We can get I dn1 = 353.6250 µ A .

Req1 = Vout / I dn1 = 3.5348K Ω

Req 0 + Req1 3.3823K + 3.5348 K

So Req = = = 3.4586 K Ω . Thus

2 2

t pHL = ln(2) × ( Req || RL ) × CL = 0.69 × 3.3061K × 3 ×10−12 = 6.8436ns

Similarly:

t pLH = ln(2) × RL × CL = 0.69 × 75K × 3 ×10−12 = 155.25ns

Then, we get:

t +t

t p = pLH pHL = 81.0468ns

2

a. In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with input

capacitance Ci = 10 fF), you decide to introduce a two-state buffer as shown in Figure

ECE 6421 Instructor: Dr. Yunsi Fei Student: Jifeng Chen

3.2. Assume that the propagation delay of a minimum size inverter is 70 ps. Also assume

that the input capacitance of a gate is proportional to its size. Determine the sizing of the

two additional buffer stages that will minimize the propagation delay. (Assume γ =1 )

CL 20 pF

Answer: F = = = 2000 , let CL / Ci be evenly distributed over the 3 inverters, we

Ci 10 fF

Figure 3.2 Buffer insertion for driving large loads

get: f = 3 F = 3 2000 = 12.5992 .

So the sizing for the two additional buffers is 12.6 and 158.76 times of the minimum

size, respectively.

b. If you could add any number of stages to achieve the minimum delay, how many stages

would you insert? What is the propagation delay in this case?

N

F ln F

Answer: Assume N stages are inserted, we should have: γ + N F − = 0 . When γ =1,

N

f opt is around 3.6. Thus N = log 3.6 2000 ≈ 6(integer) . Thus 5 stages should be inserted.

So t p = Nt p 0 (1 + N F / γ ) = 6 × 70 p × (1 + 6 2000 /1) = 1910.8 ps .

c. Describe the advantages and disadvantages of the methods shown in (a) and (b).

Answer: For method in (a), the overall delay is larger than the delay by method (b). But

compared with method (a), method (a) will insert more inverter, it needs more area (inverters

and interconnects), which introduce more resistance and capacitance. This will lead to more

power consumption and potential degradation to the circuit, for example, crosstalk.

Size the devices so that the output resistance is the same as that of an inverter with an NMOS

W/L=2 and PMOS W/L=6. Which input pattern(s) would give the worst and best equivalent

pull-up or pull-down resistance?

__ __ __ __ __ __ __ __________________________ _

Answer: X = (( A+ B )(C + D + E ) + F ) G = ( AB + CDE ) F + G

In the following figure, the number close to each transistor means the sizing factor of that

transistor:

ECE 6421 Instructor: Dr. Yunsi Fei Student: Jifeng Chen

G 12

24 24 24

C D E

12

F

24 24

A B

F 4

8 12

A C

12 2

D G

8 12

B E

For pull-up, when all PMOSs are on, the pull-up capability is highest, thus

ABCDEFG = 0000000 . When only one pull-up path is on, and the current from VDD goes

through most PMOSs, it is a worst case. This kind of paths include:

ABCDEFG = {0101110,1001110, 0110110,1010110, 0111010,1011010}

For pull-down, when all NMOSs are on, the pull-down capability is highest, thus

ABCDEFG = 1111111 . When only one pull-down path is on, and the current from Vout goes

through most NMOSs, it is a worst case. This kind of paths include:

ABCDEFG = {0000001,1100010, 0011110}

a. Find the logic functions of circuits A and B in the figure below.

___ ___ ___ ___

Answer: For (a), F = AB + A B . For (b), F = AB + A B . They are functionally same.

b. Which one is a dual network and which one is not?

Answer: (a) is a dual network, while (b) isn’t.

c. Is the nondual network still a valid static logic gate? Explain why or why not.

Answer: Yes. Because for any input combinations of AB, there is always a path from output

to supply voltage or ground. The circuit works fine.

d. List any advantages of one configuration over the other.

Answer: (b) is better. For any input combination, there will always be only one path

conducted, the output capacitance is smaller compared with (a).

ECE 6421 Instructor: Dr. Yunsi Fei Student: Jifeng Chen

5. Given a chain of gates as shown below in the figure. Select gate sizes x and y for least

delay from A to B. Also for each stage, in order to get equivalent tpHL and tpLH, what size

should their PMOS and NMOS be? Note that the load capacitance CL = 45 Cunit, the input

gate capacitance of any gate is proportional to its size.

x

y

x

45

A 8

x

y B

45

4 5 5

F = 45 / 8 = 5.6250 ; G = × × = 3.7037 ; B = 3 × 2 = 6 ; Then H = GFB = 125 .

3 3 3

Thus, the best stage effort: h = 3 H = 5 → Parasitic delay: P = 2 + 3 + 2 = 7Units

The total path delay will be: D = P + N × h = 7 + 3 × 5 = 22Units .

Thus the effective fan-out for each stage is: f i = h / gi . For each stage, we can get:

5

f1 = h / g1 = = 3.75

4/3

5

f 2 = h / g2 = =3

5/3

5

f 3 = h / g3 = =3

5/3

1 5 1

So, x = g1s1 / g 2 × f1 / b1 = 4 / 3 × 8 × × × =8

5/3 4/3 3

1 5 1 5 1

y = g1s1 / g3 × f1 / b1 × f2 / b2 = 4 / 3 × 8 × × × × × = 12

5/3 4/3 3 5/3 2

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