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t may initially appear to be a long step from the generic microprocessor of the previous section to a real PC system, but in reality it’s not. In this section we will investigate how advanced microprocessors used in 8-, 16-, 32- and 64-bit systems expand the basic concepts developed in the $1.98 computer. This investigation includes the 80386SX microprocessor used in the Turbo-PC system. The overall operation of both systems is based on the same fundamental, binary concepts. As a matter of fact, both computers could have been constructed using only the basic NAND and NOR gates. Figure 1 depicts the various blocks that make up an 8088-based, XT-compatible system and illustrates how these blocks are connected together. Understanding and working with any electronic system (digital systems included) requires that you understand the function of the individual blocks which make up the system. At the heart of PC and PC-XT compatible systems is the 40-pin 8088 mP. The 8088 is a high performance HMOS microprocessor which has attributes of both 8 and 16-bit processors. Its internal structure supports 16-bit words but it only uses an 8-bit data bus. In this manner, its internal data registers can be used as single 16-bit registers, divided into higher and lower order bytes, or used as independent 8-bit register pairs. This allows the 8088 to perform both 8 and 16-bit signed and unsigned arithmetic operations, using binary or decimal numbers. These operations include both multiplication and division. The 8088 supports a 20-bit address bus that allows it to directly access 1 Megabyte (1,048,576) of memory and I/O addresses. The 8088-2 version can run at either of two standard clock rates; a 4.77 MHz normal clock frequency and a high-speed (Turbo) 8 MHz clock frequency. In addition, the 8088 can be used in two configuration modes: (1) maximum mode, in which the system uses a full line of 8088 support chips and can accommodate high speed numeric and I/O co-processors, and (2) minimum mode, where the 8088 handles system functions, such as bus control, by itself. In PC compatibles, the 8088 is configured for maximum mode operation.
THE 8088 MICROPROCESSOR 1
Figure 1: XT-Compatible System Block Diagram
THE 8088 MICROPROCESSOR 2
Figure 1: XT-Compatible System Block Diagram
THE 8088 MICROPROCESSOR 3
INSIDE THE 8088
Figure 2 illustrates the basic architecture of the 8088 in block diagram form. One of the most noticeable features of the 8088’s internal structure is its large and very flexible register set. The register set consists of fourteen 16-bit registers which can be divided into four functional groups, as follows: the data group, the index and pointer registers, the segment registers, and the instruction pointer and flag registers.
Figure 2: Inside the 8088
The most interesting of these registers has to be the data group (AX, BX, CX and DX). These highly flexible registers are unique in that each can be treated as a single 16-bit register, or they may be used as two, independent 8-bit registers (AH and AL, BH and BL, CH and CL, and DH and DL). The “H” and “L” designators refer to the higher and lower order bytes of the basic 16-bit register. All of these registers correspond roughly to the accumulator register. Arithmetic and logic operations can be performed, and results can be stored in each of the data registers. (These operations can also be performed in the two index and pointer registers). Although the data registers can be used to perform a number of different functions, each is assigned at least one specialized function. The AX register is designated as the 8088’s “official” accumulator register. It is also used in all input and output instructions, such as fetching data from the keyboard buffer and outputting data bytes to the display memory. The BX or base register is used by the 8088 to perform a special form of memory addressing called indexed addressing. The CX, or count register is used as a counter to keep track of the number of times certain repetitive operations are performed. The DX, or data register is used by the system to hold I/O port addresses during input/output instructions.
THE 8088 MICROPROCESSOR 4
You may wonder how the 8088 can support a 20-bit address bus if its internal registers are only 16-bits wide. Actually, the 20-bit address is constructed inside the 8088 by combining the contents of two registers. The 8088’s memory addresses are divided into 64K-byte blocks called segments. These segments can be assigned to the segment registers in the 8088. Within each 64K segment, individual addresses can be accessed using only a 16-bit address called the offset address. To obtain the entire 20-bit address, the 16-bit offset address is added to a 16-bit segment address which has been shifted left four binary places. This concept is illustrated in Figure 3. During instruction cycles, the 8088’s address is the sum of the Instruction Pointer (IP) and Code Segment (CS) registers.
Figure 3: 8088 Addressing
During execution cycles, the address produced is the sum of the operand address portion of the instruction word and the contents of one of the segment registers (DS, SS, or ES). In special addressing operations involving the Stack, the contents of the Stack Segment (SS) register is added to the contents of either the Base Pointer (BP) or the Stack Pointer (SP) registers to obtain the address. The Data Segment (DS) register is used whenever data is moved to or from the memory. These combinations can be confusing at times, but fortunately, most of the time these combinations are performed automatically by the hardware. Another interesting aspect of the 8088’s internal structure is the presence of four, 1-byte instruction registers configured for First-In, First-Out (FIFO) operation. This block of registers is referred to as the instruction queue and is used by the 8088 to pre-fetch instructions from memory before they are needed. This speeds up the execution of programs by allowing the 8088 to execute instructions from the on-board queue instead of waiting for a Memory Read cycle to be performed. The 8088’s control unit works to keep the instruction queue filled at all times. When a JUMP instruction is encountered in the program, the control unit “dumps” the contents of the queue and begins reloading it, starting with the instruction at the address indicated by the JUMP instruction. The operation of the instruction queue is performed automatically by the 8088.
THE 8088 MICROPROCESSOR 5
THE 8088 FROM THE OUTSIDE
As a repair technician, you will probably be more interested in the external operation of the 8088, than in its internal structure. The pin assignments and definitions of the 8088 mP are described in Figure 4. In order to hold the number of pins on the IC down to a reasonable level, the 8088’s designers multiplexed many of its pins to perform different functions under different circumstances. Some pins are time-multiplexed to perform given functions, depending upon what part of the machine cycle the microprocessor is in. Other pins perform different functions which are dependent on the configuration of the circuitry surrounding the microprocessor.
Figure 4: 8088 Pin Assignments
The most notable of the multiplexed pins are the address/data lines (AD0–AD7) and the address/status pins (A16/S3–A19/S6). Pins AD0 through AD7 are time-multiplexed to act as address lines during the first clock pulse of the machine cycle, and then turn into bidirectional data lines throughout the remainder of the machine cycle. Likewise, the address/status pins are multiplexed to act as address lines during the first clock pulse and then change to processor status lines for the remainder of the machine cycle. The S3 through S6 lines are special status lines used to indicate the segment register used during memory accesses. These lines could be used for advanced addressing techniques, but most XTcompatibles do not use them. Collectively, the AD0–AD7, A8–A15, and A16/S3–A19/S6 lines are combined to form the system’s 20-bit address bus. The XT type computer uses two 74LS373 transparent octal latches to latch address bits AD0–AD7 and A16–A19 during the first clock pulse and hold them throughout the machine cycle. A line buffer IC is used for the non-multiplexed address bits (A8–A11). The outputs of these three devices provide the demultiplexed, 20-bit address bus for the system. In addition, they also free-up the lines to carry data through the remainder of the machine cycle. The operation of the address latches is controlled by the Address Latch Enable (ALE) signal from the bus controller IC (see the Status/Control Lines below). The 8088 uses the entire 20-bits when it is addressing memory locations, but only lines A0 through A15 are used when addressing Input/Output devices.
THE 8088 MICROPROCESSOR 6
After the address has been latched, the AD0-AD7 lines are available for bi-directional data transfers. The computer system uses a bi-directional line-buffer to assist the 8088 in driving the system’s data bus. The transfer of data through the line-buffer is controlled by a pair of signals from the bus controller. The bus controller issues a data enable (DEN) signal to activate the buffer, along with a data transmit/receive (DT/R) direction signal, which properly configures the buffer so that the mP can Read (receive) or Write (transmit) through them. Figure 5 illustrates how the 8088’s address/data/status pins are demultiplexed to form the address and data buses.
Figure 5: System Bus Demultiplexing
In maximum mode, the 8088 employs an 8288 bus controller IC to allow some of its pins to perform more advanced functions. The 8088 issues binary coded control signals to the 8288 via its S0-S2 status lines. The 8288 decodes these signals and develops bus control signals for the system. We’ve already discussed several of these signals in the preceding section. When the 8088 is used in minimum mode, its pins assume many of the typical microprocessor control line definitions.
Interrupt Function Lines
The 8088 uses a number of pins besides those involved directly with the data and address buses. Of the remaining pins, the 8088 devotes two of these to handling I/O interrupts. These are the interrupt request (INTR) and non-maskable interrupt (NMI) pins.
THE 8088 MICROPROCESSOR 7
When an I/O device wants to communicate with the 8088, it does so by sending an interrupt request signal. This signal is applied to the interrupt controller chip, which in turn, places a high logic level on the 8088’s INTR line. Upon receipt of the INTR signal, the 8088 finishes the instruction that is currently in progress, stores the contents of its internal registers on the stack, and sends the bus controller a signal on lines S0-S2. The bus controller responds by dropping its interrupt acknowledge (INTA) line low. The INTA signal notifies the interrupt controller that the processor is responding to interrupts, and prompts it to specify the starting address (interrupt vector) of the particular interrupt handler subroutine desired. When the interrupt controller responds with the interrupt vector, the 8088 jumps to the memory location specified by the interrupt vector. At this location, the 8088 finds the starting address of the specified interrupt service routine. The 8088 jumps to this address, executes the subroutine to service the interrupting device, and then returns to the program it was working before it received the interrupt request. The original contents of its internal registers are restored and it begins execution of the old program at the first instruction following the one it was working on when it was interrupted. This type of interrupt can be initiated by hardware or through software instructions (call routines). In addition, the 8088 has the capability to ignore, or mask, this type of interrupt request. The NMI pin represents a slightly different type of interrupt request, in that its effects cannot be ignored by the processor. When a high priority device, such as the power supply, parity checking circuitry, or other circuits which require the ability to absolutely interrupt the mP, needs to communicate with the mP, it simply places a signal on the NMI line and the 8088 must respond. Unlike the INTR line, which is active high, the NMI line is an edge-triggered signal, meaning that it is activated by a transition from one logic level to the other, instead of by a given logic level.
Wait State Control Lines
Another interesting set of control lines are those which have the capability to place the 8088 in a Wait state for a short period of time. These pins include the READY pin, the RQ/GT0 and RQ/GT1 pins, and the QS0-QS1 pins. The 8088’s READY line serves exactly the same purpose as the one described there. Any device which cannot place data on the data bus in the time allotted by the 8088’s machine cycles can force the mP to stop and wait, by dropping this line to a low logic level. The 8088 produces the WAIT state by inserting extra clock cycles into its machine cycle. During the WAIT state, the 8088 does nothing but wait for its READY line to return to a high logic level. If the READY line is held low for longer than 2 microseconds, the 8088 will lock-up and stop processing (crash). The READY line is also used by the DMA controller to cause the 8088 to insert extra waitstate clock pulses in its machine cycle during high speed DMA transfer activities. During these activities, the DMA controller takes control of the system’s data, address, and control buses at the end of a machine cycle, to carry out high-speed data transfers. These transfers are also dependent on the 8088’s LOCK line being in a high state. This line is used by the 8088 to deny other processors, or processor-like devices, such as the DMA controller or math coprocessors, access to memory locations during critical operations.
THE 8088 MICROPROCESSOR 8
The 8088’s other wait-state producing pins, RQ/GT0, RQ/GT1, QS0 and QS1, are used to coordinate activities between the 8088 and any co-processors, such as the 8087 high-speed math co-processor, which may also be in the system. When the co-processor requires access to the buses, it places a low going request pulse on the RQ/GT1 line for one clock cycle. The 8088 responds by placing a similar signal on the same line and floating its bus lines. Upon receipt of the grant signal, the 8087 loads whatever data it needs to carry out the instruction which was passed to it (via an escape code), prior to the request pulse. When the co-processor has all of the data that it requires, it applies a release pulse to the RQ/GT1 line and the two processors can run simultaneously. The 8088’s RQ/GT0 line performs the same handshaking routine but is not used in the operation of most XT compatibles. In addition to the simple RQ/GT handshaking line, the 8088 uses the QS0, QS1 and LOCK lines to coordinate the operation of dual processors within the system. The QS0 and QS1 outputs indicate the condition of the 8088’s internal instruction queue and are used along with its select lines to cue the 8087. The 8088 uses its LOCK output to lock-out co-processors and processor-like devices, called bus masters, during the execution of certain procedures. To prevent the coprocessor from interrupting during these procedures, the 8088 sends its LOCK line low, which places the co-processor in a wait state.
As is the case with all IC chips, the 8088 must have power supply connections. These consist of a single +5Vdc pin (40) and two ground pins (1 and 20). Recall that without proper supply voltages, IC’s simply don’t work. Equally essential to a mP is its clock input. The 8088’s clock input is supplied by an 8284 clock generator whose purpose is to keep te different devices in the system synchronized. The signal applied to the 8088 is an asymmetrical square wave with a 33% duty factor. That is, the clock signal is high only 33% of the time. The 8088-2 version of the 8088 mP has two standard clock rates that it can operate with; a standard 4.77MHz signal and the turbo 8MHz clock signal. In these turbo machines, the 8088’s clocking mode can usually be selected by a software command, or by a hardware jumper located on the system board. The function of the 8088’s RESET line is the same as that of the RESET pin . When the system is booted-up (either a cold or a warm boot), the RESET line goes high and the 8088 clears its DS, ES and SS, and its IP registers to zero. The CS register is set to FFFF. Therefore, the first instruction word address produced by the 8088 after the RESET Line returns to a high logic state is FFFF0. This is, of course, the starting address of the ROM BIOS start-up routine. Although PC and PC-XT compatibles use the 8088 in maximum mode, it can also be used in minimum mode (without the 8288 bus controller) quite effectively. The 8088’s mode of operation is governed by the logic level applied to the MN/MX pin. A high logic level at this pin places the 8088 in minimum mode, while a low logic level places it in maximum mode. The Turbo-PC only uses the 8088 in maximum mode, so the MN/MX pin is tied low (GND). It’s worth noting that in maximum mode, the two remaining pins, Read Data (RD) and a special status line (SS0) are not used.
THE 8088 MICROPROCESSOR 9
8088 BUS CYCLE
The 8088 will follow a certain sequence each time the it accesses the address and data buses for a read or write operation. This sequence of events is called its bus cycle, or machine cycle. The 8088 is capable of carrying out the eight bus cycle types listed in Table 1. It indicates which type of bus cycle is about to be initiated via coded status signals, S0, S1, S2, that tell the bus controller what signals to generate. The bus controller IC is a simple decoding device which takes in the status signals from the 8088, along with a clock signal from the clock generator IC, decodes them, and generates the appropriate signals to supervise the operation of the system’s data and address buses. This relationship is shown in Figure 6.
Table 1: 8288 Select Codes
0 0 0
S2 0 (LOW)
S1 0 0 1 1 0 0 1 1
S0 0 1 0 1 0
CHARACTERISTICS INTERRUPT ACKNOWLEDGEMENT READ I/O WRITE I/O HALT INSTRUCTION FETCH READ DATA FROM MEMORY WRITE DATA FROM MEMORY PASSIVE (NO BUS CYCLE)
1 (HIGH) 1 1 1
When the bus controller receives the status signals from the 8088, it decodes them and generates either a memory read (MEMR), memory write (MEMW), I/O read (IOR), or I/O write (IOW) signal, to carry out the CPU’s wishes. The signal is produced after it has caused the address to be latched into the 74LS373, through it’s ALE signal. All of the control bus signals are active low. (They are normally held in a high logic state and go to a low logic state when the bus controller activates them).
THE 8088 MICROPROCESSOR 10
Figure 6: 8088 Read I/O Bus Cycle
The machine cycle for the 8088 requires at least four clock cycles. These are referred to as T1, T2, T3, and T4: T1 always begins the machine cycle and T4 will always indicate the end of the machine cycle. A machine cycle for a Read I/O operation is illustrated in Figure 7. This figure shows the major signals necessary to read a byte of data from an I/O port. The first signal to note is the clock. As described earlier, its purpose is to keep the different chips of the system synchronized. The clock signal comes from the clock generator IC. The next signals of importance are the status lines from the 8088. Finally, there are the address bus signals shown as AD0 - AD7, A8 - A15, A16/S3 - A19/S6. The remainder of the signals originate from the bus controller.
THE 8088 MICROPROCESSOR 11
Figure 7: The IBM-PC AT Block Diagram
THE 8088 MICROPROCESSOR 12
The 8088 initiates the bus cycle by outputting the status signals, which indicate what operation is about to take place. In this example, a Read I/O operation (001 for S2, S1, S0 respectively) is designated. When the bus controller receives these signals, it knows a bus cycle is starting. More specifically, it knows it’s the start of T1. Since the bus controller also receives the clock signal, it is able to keep up with the different steps of the bus cycle and knows exactly where the 8088 is at each step. During T1, the 8088 outputs an address of the I/O port to read from. This address is specified on AD0 - AD7 and A8 - A15. Recall that during I/O data transfers, only the 16 lower address lines are used. This is why the other address lines (A16/S3 - A19/S6) are shown as low logic in Figure 7. During this part of the bus cycle, the time multiplexed address signals (AD0 AD7 and A16/S3 - A19/S6) contain only address information. Address signals A8 - A15 are not multiplexed; therefore they maintain address information throughout the entire bus cycle. Also during T1, the bus controller activates its ALE pin, which is used to latch address information from the time-multiplexed lines into the 74LS373 latch. The latching occurs on the falling edge of the ALE signal (when ALE makes a transition from high logic to low logic since this is an edge-triggered signal). The 74LS373 will hold this address until it receives another falling edge of ALE. During T2 the AD0 - AD7 lines float to a high impedance state (effectively disconnecting themselves from the bus) while they change over inside the 8088 to become bi-directional data lines. During this period, A16/S3 - A19/S6 lines also change functions to become status signals S3 - S6. These status lines are not used in an XT-compatibles. However, these lines have to be separated from the bus because the address lines A16 - A19 are needed and this phase of the operation is inherent to the 8088. During T2, the bus controller activates the IOR signal to indicate to the I/O port that it is to output data form the selected address. At the beginning of T2 the bus controller also activates the DT/R line, which determines data direction through the 74LS245 buffer, along with a DEN signal to enable the 74LS245. At the beginning of T3 the data lines (D0 - D7) are ready to accept data from the addressed I/O port. The IOR, DT/R, DEN lines remain active to pass this data to the 8088. In the middle of T3 the status lines S0 - S2 go to a high logic state to indicate to the bus controller that the 8088 is nearing the last portion of the bus cycle and that T4 is approaching. During T4 the 8088 and bus controller will finish the bus cycle. At this time the 8088 will accept the data that is on the data lines and all control signals will be deactivated, so IOR, DT/R, DEN return to high logic indicating the end of the bus cycle. All of the events in this description have been for the specific example of a Read I/O operation. However the other bus cycle types do not differ much from this sequence. The major difference occurs with the read or write signal used. For example, if we examined a Memory Write operation, the difference would be that MEMW is used instead of IOR, and that the DT/R line would remain at high logic since data would travel from the 8088 to memory through the 74LS245. The other actions in the bus cycle would remain the same. Basically, the microprocessor can only do one of two things when it accesses the bus and that is either read data or write data. In more specific terms, the microprocessor can perform a read or write operation on either memory or an I/O port. Any of the read or write bus cycles may have wait states inserted into them. The wait states are added between states T3 and T4. When the 8088 is executing a bus cycle, it will sample the condition of the READY line just prior to the beginning of T3. If this line is low, the microprocessor will insert wait-states into the bus cycle. When the 8088 is inserting wait-states, other bus masters may gain access to the buses.
THE 8088 MICROPROCESSOR 13
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