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ISSN 2277-2685

IJESR/June 2014/ Vol-4/Issue-6/319-323


Himanshu Shekhar et al./ International Journal of Engineering & Science Research

DESIGN HIGH SPEED, LOW NOISE, LOW POWER TWO STAGE CMOS
OPERATIONAL AMPLIFIER
Himanshu Shekhar*1, Amit Rajput1
1
Department Of Electronics &Communication, RITS, Bhopal (MP), India.

ABSTRACT
The objective of this paper is to design a Low-Voltage, Low-Power and High-Gain Operational Amplifier used
for high speed compensated CMOS op-amp which specifies open loop circuit parameters to obtain enhanced
gain, settling time and closed loop stability An Op-Amp is designed in a 0.18 µm standard digital CMOS
Technology The low noise high speed Op-Amp is designed using 180nm CMOS technology and exhibits. Slew
rate to 17 V/ms and gain-bandwidth product to 63 MHz, gain margin 80db, phase margin 77 db Performance of
an op-amp at supply voltage 1.8V .

Keywords: Two Stage OP-Amp high speed low noise OP-Amp Circuit , Op-Amp, Phase Margin, gain margin,
precision circuit.

INTRODUCTION
The designing of high performance analog integrated circuits is becoming most essential with the continuous
trend towards the reduced supply voltages and transistor channel length. MOS is most success among all
because it can be scaled down to smaller dimensions for higher performance. The size can be reduced to
micrometer or nanometer for getting higher performance. On scaling down the Transistor size the most
important advantage iswe can integrate more number of transistors on the same size and we can get a faster
amplifier compared to previous one. This leads to continuous growth of the processing capacity per chip and
operating frequency. To achieve high gain with continued scaling in CMOS fabrication processes, use of
multiple stage op-amps has become indispensable. Many applications require high-speed analog-to-digital
converters (ADCs) due to increasing data rates. Hence, they require high accuracy op-amps with very high dc
gain and high unity gain frequency in order to meet both accuracy and settling requirements of the system. The
op-amp is one of the most important building blocks of the analog circuit technology.

Fig 1: Block diagram of op-amp


Almost all amplification and filtering functions can be realized using op-amps. Several fundamental issues and
trade-offs exist when selecting an optimal Amplifiers are the most common building blocks. So as the transistor
channel length and power supply is reduced then the design of Op amps face continuous challenge. Due to
different aspect ratio (W/L), there is a trade off among speed, gain, power and the other parameters. The
implementation of a CMOS OPAMPs that combines a considerable dc gain with higher unity gain frequency
has been a most difficult problem. There have been several circuits proposed to evaluate this problem. The
purpose of the design methodology in this paper is to propose accurate equations for the design of high- gain2
staged CMOS op-amp.

*Corresponding Author www.ijesr.org 319


Himanshu Shekhar et al./ International Journal of Engineering & Science Research

BLOCK DIAGRAM OF TWO STAGE CMOS OP-AMP


Operational Amplifiers are the backbone for many analog circuit designs. The speed and accuracy of these
circuits depends on the bandwidth and DC gain of the Op-amp, the implementation of a CMOS OPAMPs that
combines a considerable dc gain with higher unity gain frequency has been a most difficult problem. There have
been several circuits proposed to evaluate this problem. The purpose of the design methodology in this paper is
to propose accurate equations for the design of high- gain2 staged CMOS op-amp.

Fig 2: Block diagram of two op-amp Fig 3: Equivalent circuit of op-amp


Generic block diagram with all the basic building blocks of simple two-stage Op–amp is shown below. Each
box in the figure can be replaced with an actual circuit implemented in modern VLSI technology.
Design of Two Stage OPAMP
The specific two stage CMOS OPAMP is shown in figure, on the basis of the circuit, various blocks of the each
stage are configured, like adder, sample and hold, and amplifier. Thus, it is one of the most important circuits of
the pipeline ADC. The circuit consists of an input differential stage with active load followed by a common
source stage. Since this is the part of the internal blocks of the each stage and is only required to drive a fixed on
chip capacitive load of few Pico farads. Its main drawback is the non dominant pole formed by the load
capacitance and the output impedance of the second stage, which reduces the achievable bandwidth. Another
potential disadvantage is the right half plane zero that arises from the feed forward signal path through the
compensating capacitor.

Fig 4: Circuit Diagram Of Two Stage Op-Amp

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Himanshu Shekhar et al./ International Journal of Engineering & Science Research

The following specification have been used for design of the two stage OPAMP
 Vdd = Vss = ±1.27
 Av = 5000 V/V = 73.97 dB
 GBW ≥ 99 MHz
 Slew Rate ≥ 32 V/µs; ICMR = ±0.7 V CL = 4pF
0
For 60 phase Margin, CC>0.24 CL
CC=1.5pF So the tail current I5= Slew Rate*CC = 30 x 1.5 = 45 µA For the aspect ratio of M3

For the desired GB


gm1 = GB .Cc = ( 99µ ). 2π . 1.5 *10-12 = 933 µ mho

Design for S5 from the minimum input voltage; First calculate VDS5(sat) & then S5

VDS5(sat) == 0.2932v

for M9 50*9µ = 78.4* 10-6 * W/L * [1.5- 0.9 -0.4021]2 =

Find the S6 and I6 by letting the 2nd pole be equal to 2.4 times GB gm6 = 1.2 gm2 (CL/ Cc)
= 7.3 gm2 = 6104 µ mho
Calculate gm4

Let Vsg4 = Vsg6 , which gives

S6 = 622/1
The output current I6 is given by

The aspect ratio S7 is given by S7 = S5. ( I6 / I5 ) = 265 / 1


Table 5.3: MOS Sizes for Operational Amplifier

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Himanshu Shekhar et al./ International Journal of Engineering & Science Research

Index of MOS W/L


M1, M2 248.30/1
M3, M4 10.6/1
M5 7.32/1
M6 725/1
M7 265/1
M8 7.32/1
M9 2.1/5
Operational amplifier dual low noise high precision op-amp The OP37 provides the same high performance as
the OP27, but the design is optimized for circuits with gains greater than five. This design change increases slew
rate to 17 V/ms and gain-bandwidth product to 63 MHz adding the input resistor Rin limits the differentiators
increase in gain at a ratio of Rƒ/Rin. The circuit now acts like a differentiator amplifier at low frequencies and
an amplifier with resistive feedback at high frequencies giving much better noise rejection

Fig 5: Operational amplifier dual low noise high precision op-amps

SIMULATION RESULT

Fig 6: Operational amplifier dual low noise high precision op-amp


To begin this discussion on spectral analysis, let us begin by considering the question of trying to detect an
underlying sinusoidal signal component that is buried in noise.

Fig 7: FFT Response Of Input Output noise

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Himanshu Shekhar et al./ International Journal of Engineering & Science Research

This simulation result show the gain margin and phase margin of two stage op-amp

CONCLUSION
The amplifier presented in this paper operates at weak and moderate inversion and regulates its bias current.
When a signal is applied the current in the amplifier increases so that these amplifiers have very high driving
current This paper presents the full custom design of a two stage fully differential amplifier with active load and
single ended output where biasing is done by perfectly matched current mirror circuit; slew rate to 17 V/ms and
gain-bandwidth product to 63 MHz gain margin 80db phase margin 77 db The circuit characteristics have been
verified by using 0.18µm technology In addition, the open loop amplifier also has a considerably high gain with
very low power consumption at the instant of full swing operation

REFERENCES
[1] Liang S-Q, Yin Y-S; Deng H-H; Song Y-K. A low power consumption, high speed Op-amp for a 10-bit
100MSPS parallel pipeline ADC. IEEE Asia Pacific Conference 2008.
[2] A systematic design procedure for high-speed op-amp performance optimization Perenzoni,
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Circuit Theory and Design, 2011. Proceedings of the 2005 European Conference on (Volume:3 ) 28 Aug.-2
Sept. 2011 .
[3] Saxena V. Indirect Compensation Techniques for Multi-Stage Operational Amplifiers, M.S. Thesis, ECE
Dept., Boise State University, Oct 2007.
[4] Waltari M, Halonenn KAI. 1-V 9-bit pipelined switched-op-amp ADC. Solid-state Circuits. IEEE Journal
2001; 36(1): 129–134.
[5] Crols J, Steyaert M. Switched-Op-Amp: An Approach to Realize Full CMOS Switched- Capacitor Filters at
Very Low Voltages. IEEE J. Solid-State Circuits 2008; 29: 936-942.

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