THE TURBO-PC PARALLEL PORT

INTRODUCTION

T

he Turbo-PC supports parallel printer connections from the system board. The PRT interface connection offers 8-bit parallel data words and nine I/O control lines that can be connected to an IBM-Centronics compatible, 25-pin female D-shell connector at the rear of the system unit.

THE TURBO-PC PARALLEL PORT
The Turbo-PC, and most other IBM compatible systems, use a modified 25-pin Centronics printer interface. Like the other I/O sections in the Turbo-PC, this function is integrated into the EIOC chip on the system board. The Turbo-PC’s parallel port circuitry is depicted in Figure 1.

Figure 1: Turbo-PC’s Parallel Port Circuitry

THE TURBO-PC PARALLEL PORT 1

Figure 2 depicts a block diagram of the Standard Parallel Port (SPP) function of the EIOC. This includes a port address decoder, data latching register, data bus buffer, control-line latching register, status-line buffer, and open collector control-line drivers. In operation, the adapter performs five I/O instructions that correspond to three different port addresses and the condition of the system’s IOR line. The port supports a two-way handshaking scheme, using the Strobe, Acknowledge, and Busy lines.

Figure 2: Block Diagram of the 5113’s Printer Interface
The printer adapter sections of the M5113 are enabled by port addresses 378h through 37Fh. When the system wishes to send a byte of data to the printer, it must place the data byte on the data bus, set its IOR line high (this is the equivalent of IOW being active), and apply an address of 378h to the adapter. This action causes the adapter’s Data Latch to accept the data from the data bus, and latch it. Next, the computer must read the adapter’s Status Buffer to check the condition of the printer’s Busy line. In order to read the printer’s status bits, the computer must make its IOR line low and apply an address of 379h to the adapter. This places the (ERROR, SLCT, PE, INIT, and BUSY), status bits on the adapter’s data bus. If the Busy line is low, indicating that the printer can accept data, the system pulses the Strobe line low to tell the printer that a valid data byte is present on the data lines from the port. Actually, the system software writes a complete 6-bit control word into the Control Latch by placing the word on the data bus, making the IOR line high, and applying an address of 37Ah to the port. This places the control word in the latch, which, in turn, applies the individual bits to the printer’s input control lines.

THE TURBO-PC PARALLEL PORT 2

Two other instructions allow the system to read the contents of the two latches. In order to read the current contents of the Data Latching register, the microprocessor must make the IOR line low and apply an address of 378h to the interface. This action enables the Data Bus Buffer and places the outputs of the Data Latch register on the M5113’s data bus. When the system unit reads the status of the printer, it makes the IOR line low and applies an address of 37Ah to the adapter. This allows the system unit to read the printer’s (SLCT-IN, ACK, STROBE, and AUTO-FD) status lines as well as the port’s IRQ line. If the printer is not driving these pins, the system will read the last control word written into the Control Latch register. In the event that the printer is driving these pins, the status bits from the printer will be logically ORed with the bits of the Control Latch and placed on the port’s data bus. In addition to the primary handshaking lines (STROBE, ACK, BUSY), the parallel printer interface provides secondary control lines for PE, SLCT and ERROR input signals from the printer, and AUTO-FD, INIT, and SLCT-IN outputs to the printer. The interrupt level of the printer port section may be set at a number of different levels by changing its configuration jumpers. The interrupt from the printer is actually obtained through the Initialize Printer (INIT) line. This signal is gated to the adapter’s interrupt line by the Interrupt Enable (INT EN) bit of the control word stored in the Control Latch. The status of this bit determines whether the printer adapter can interrupt the system unit. In this manner, the printer can use the printer port’s Init input to cause an interrupt to occur, provided the system unit has not masked the interrupt through the interrupt enable bit of the control word. Figure 3 illustrates the connection of the Turbo-PC’s Enhanced Centronics printer port. The printer cable connects to the DB25F 25-pin connector at the rear of the system unit. A ribbon cable from the 25-pin D-shell connector plugs into the 26-pin BERG block at PRT1 on the system board. This connector communicates directly with the M5113 EIOC. All of the signals transmitted between the port and the printer are at standard TTL voltage levels. This means that the signals can deteriorate quickly with long lengths of cable. The cable length used for the parallel printer should be kept to under 10 feet. If longer lengths are needed, the cable should have a low capacitance value. The cable should also be shielded so as to minimize interference.

Figure 3: Turbo-PC’s Enhanced Centronics Printer Port

THE TURBO-PC PARALLEL PORT 3

The figure also shows the signals from the system buses that are associated with the operation of the parallel printer port. These signals are used in the selection and operation of the printer port. The Data Port resides at port address 378h. The Status Port has a port address of 379h. The Control Port has a port address of hex 37A. These addresses are for the first (LPT1:) printer port installed in the computer. The logical address of the printer port can be changed to respond as LPT1 (378h-37Ah), LPT2 (278h-27Ah), or LPT3 (3BCh-3BEh), depending on the setting of options in the Integrated Peripherals area of the Award BIOS Setup utility. The printer port can also be disabled completely through this utility. The interrupt level for the printer port is normally set to IRQ5 or IRQ7. The signals transmitted from the system to the printer (STROBE, AUTO FEED, INIT, and SLCT-IN) pass through the interface’s Control Port. The signals transmitted from the printer to the system (ACK, BUSY, PAPER END, SELECT, and ERROR) are received through the Status Port.

Enhanced Parallel Port Operations
The parallel port has been improved a few times since the days of the PC, PC-XT and PC-AT. In those computers, the parallel port was basically a one-way port designed to send information to a printer. This type of parallel port is referred to as a Standard Parallel Port (SPP). However, in modern PCs, the parallel port is used for a variety of applications other than parallel printers. These applications include plug-in network adapters, scanners, and data storage devices. As mentioned earlier in this chapter, the Turbo-PC’s parallel port circuitry supports advanced EPP and ECP functions. These modes are enabled in the Integrated Peripherals section of the BIOS CMOS Setup utility. In these modes, the names and definitions of the pins in the DB25 connector change. Table 1 describes the pin changes for the parallel port’s three operating modes. When the ECP mode is selected, a DMA channel should be established for the port in the same part of the Setup utility.

Table 1: Parallel Port Pin Definitions

THE TURBO-PC PARALLEL PORT 4

EPP Mode
When EPP mode is selected in the port’s configuration register, the standard and bi-direction modes are enabled. The functions of the port’s pins are redefined under the EPP specification. Table 2 provides the EPP pin definitions.

Table 2: EPP Pin Definitions

The EPP mode port supports the Data Port, Status Port, and Control Port registers addressed by the standard parallel port. However, it introduces an additional EPP Address register and four EPP Data Port registers. These registers reside at addresses specified as Base Address + 003h, 004h, 005h, 006h, and 007h. In a typical 378h-based LPT1 port, these addresses translate to 37Bh, 37Ch, 37Dh, 37Eh, and 37Fh. Data can be moved to and from the port’s data pins using the standard port register or any of the four additional data registers. When the EPP mode is enabled, the port can operate either as a standard, bi-directional parallel port, or as a bi-directional EPP port. The software controlling the port will specify which type of operation is required. If no EPP read, write, or address cycle is being executed, the port and its control signals function as an SPP port. However, when the software calls for an EPP read, write, or address cycle, all of the port’s registers are enabled and the signal lines take on the functions defined by the selected EPP standard.

THE TURBO-PC PARALLEL PORT 5

The EPP Address Port register resides at Base Address + 003h. During an EPP write operation to this address, the contents of the Data register are buffered and applied to the port’s data pins on the leading edge of the active IOW signal. The leading edge of the signal also initiates an EPP Address Write cycle. The trailing edge of the IOW signal causes the data to be latched in the register for the duration of the write cycle. During an EPP read operation to this address, the contents of the port’s data pins are read into the data register on the leading edge of the IOR signal. The leading edge of this signal also initiates an EPP address read cycle that causes the data to be output to the host microprocessor. The data is latched into the data register for the duration of the IOR cycle when the port’s ADDSTRB signal becomes inactive. The EPP Data Port registers reside at Base Address + 004h, 005h, 006h, and 007h. During an EPP write operation to any of these addresses, the contents of the selected register are buffered and applied to the port’s data pins on the leading edge of the active IOW signal. The leading edge of the signal also initiates an EPP Data Write cycle. The trailing edge of the IOW signal causes the data to be latched in the register for the duration of the write cycle. During an EPP read operation to any of these addresses, the contents of the port’s data pins are read into the selected data register on the leading edge of the IOR signal. The leading edge of this signal also initiates an EPP Data Read cycle that causes the data to be output to the host microprocessor. The data is latched into the data register for the duration of the IOR cycle when the port’s DATASTRB signal becomes inactive. There are actually two EPP specifications - EPP 1.7 and EPP 1.9. The EPP port type should be selected in the Integrated Peripherals section of the BIOS’ CMOS Setup utility. Figure 4 is a timing diagram that illustrates the signal activities associated with Data and Address write operations under the EPP1.7 standard.

Figure 4: Timing Diagram
The steps of the EPP 1.7 write operation are summarized as: 1. The host writes a byte to the data/address port and the WR line goes low to drive data to PD0-PD7. 2. The EPP pulls WRITE low to indicate an EPP Write Cycle is in progress.

THE TURBO-PC PARALLEL PORT 6

3. The EPP pulls DSTRB or ASTRB low to signal that data is valid. 4. If WAIT goes low during the cycle, IOCHRDY is pulled low. 5. When WAIT goes high, it pulls IOCHRDY high and WR will go high. 6. When WR goes high, it pulls WRITE and DSTRB/ASTRB high, and then the EPP can change PD0-PD7. Figure 5 is a timing diagram that illustrates the signal activities associated with Data and Address read operations under the EPP1.7 standard.

Figure 5: Timing Diagram
The steps of the EPP 1.7 read operation are summarized as: 1. The host reads a byte from the data/address port and the RD line goes low to input data from PD0-PD7. 2. The EPP keeps WRITE high to indicate an EPP Read Cycle is in progress. 3. The EPP pulls DSTRB or ASTRB low to signal that the peripheral should start sending data. 4. If WAIT is low during the cycle, IOCHRDY is pulled low. 5. When WAIT goes high, it pulls IOCHRDY high and RD will go high. 6. When RD goes high, it pulls WRITE and DSTRB/ASTRB high, and then the peripheral can place the PD0-PD7 lines in a high impedance state.

THE TURBO-PC PARALLEL PORT 7

Figure 6 is a timing diagram that illustrates the signal activities associated with Data and Address write operations under the EPP1.9 standard.

Figure 6: Timing Diagram
The steps of the EPP 1.9 write operation are summarized as: 1. The host writes a byte to the data/address port and the WR line goes low to drive data to PD0-PD7. 2. IOCHRDY goes low and waits for WAIT to go low. 3. If WAIT goes low, or is already low, the EPP pulls WRITE low to show that a Write cycle is in progress. 4. The EPP pulls DSTRB or ASTRB low to indicate that data is ready and waits for WAIT to go high. 5. When WAIT goes high, it pulls IOCHRDY and DSTRB/ASTRB high, and then WR will go high to turn off this cycle.

Figure 7 is a timing diagram that illustrates the signal activities associated with Data and Address read operations under the EPP1.9 standard.

Figure 7: Timing Diagram

THE TURBO-PC PARALLEL PORT 8

The steps of the EPP 1.9 read operation are summarized as: 1. The host reads a byte from the data/address port and the RD line goes low to input data from PD0-PD7. 2. IOCHRDY goes low and waits for WAIT to go low. 3. If WAIT goes low, or is already low, the EPP pulls WRITE high to show that a Read cycle is in progress. 4. The EPP pulls DSTRB or ASTRB low to signal that the peripheral should start sending data and waits for WAIT to go high. 5. When WAIT goes high, it pulls IOCHRDY and DSTRB/ASTRB high, and then RD will go high to turn off this cycle.

ECP Mode
The Extended Capabilities Port (ECP) mode provides a number of advantages over the SPP and EPP modes. The ECP mode offers higher performance than either of the other modes. As with the EPP mode, the pins of the interface are redefined when ECP mode is selected in the system’s BIOS. ECP definitions for the port’s pins are listed in Table 3.

Table 3: ECP Definitions

THE TURBO-PC PARALLEL PORT 9

In ECP mode, the parallel port operates in Forward (host-to-peripheral) and Reverse (peripheral-to-host) directions. It employs interlocked handshaking for reliable, half-duplex transfers through the port. The capabilities of the ECP port enables it to be used in peer-topeer applications. The M5113 contains a number of additional registers that become enabled when ECP mode is selected. As with the EPP port, these additional registers are specified at addresses offset from the base port address. The operation and availability of some registers depends on the ECP mode selected. Table 4 summarizes these registers.

Table 4: ECP Modes

The ECP port is compatible with the standard LPT port and is used in the same manner when no ECP read or write operations are called for. However, it also supports high-throughput DMA operations for both forward and reverse direction transfers. To synchronize timing of data moving through the port, the ECP format uses small FIFO register stacks. These stacks are 16 bytes deep. Table 5 defines the register bits of the IEEE 1284 ECP protocol specification.

Table 5: IEEE 1284 ECP Protocol Specification Register Bits

THE TURBO-PC PARALLEL PORT 10

The ECP mode is selected in the M5113’s Extended Control Register at offset 402h. The M5113’s ECP modes are described in Table 6.

Table 6: M5113’s ECP Modes

ECP Transfers
Prior to ECP operation, the system examines the peripheral device attached to the port to determine that it is capable of performing ECP operations. This operation is carried out in SPP mode. Afterward, the system initializes the port’s registers for operation. In particular, the system sets the direction bit to enable the ECP drivers, sets the operation of the Strobe and AutoFd bits so that they default to the inactive state, and finally, sets the mode to ECP. The host may switch the direction of the port’s operation by changing the mode value to 001 and then negotiating for the forward/reverse channel setting. Afterward, the mode is set back to ECP. During normal operation, commands and data may be passed through the port. In the forward direction, the port uses the HostAck pin to differentiate between data and command transfers. When HostAck is high, data is being transferred through the port. Commands are being transferred through the port when HostAck is low. Data transfers in the reverse direction use the PeriphAck signal in a similar manner. When PeriphAck is high, a data transfer is underway. When PeriphAck is low, an 8-bit command is being passed through the port. ECP transfers may be conducted in DMA or Programmed I/O modes. DMA transfers use standard PC DMA services and are always conducted to or from the ecpDFifo registers. To use this method, the host must set the port direction and program its DMA controller with the desired byte count and memory address information. The ECP port requests DMA services from the system by activating the PDRQ line. The DMA operation will empty or fill the FIFO buffer using the specified direction and mode information. When the terminal count is reached in the DMA controller, an interrupt is generated at the PINTR pin, and the DMA operation is disabled.

THE TURBO-PC PARALLEL PORT 11

The ECP FIFOs may be operated in an interrupt-driven, Programmed I/O mode. Software carries out these operations to the ecpDFifo at 400h and ecpAFifo at 000h. Transfers from the port are conducted from the ecpDFifo at 400h, or the tFifo at 400h, depending on the mode selected.

ECP Data Compression
The M5113 supports Run Length Encoded (RLE) data decompression in hardware and can transfer compressed data through the port. However, the EIOC hardware does not support RLE compression. This function must be performed by software. To transfer compressed data in ECP mode, the compression count is written into the ecpAfifo register and the data byte is written to the ecpDfifo register. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simple reads the RLE byte and repeats the designated byte the number of times specified by the RLE byte. When an RLE count is received from a peripheral device, the next byte is replicated as directed. An RLE count of 154 indicates that the following byte should be replicated 153 times. Conversely, an RLE count of zero indicates a single-byte transfer.

THE TURBO-PC PARALLEL PORT 12

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