La C341P PDF

A B C D E
Compal Confidential
Model Name : A4WAB
File Name : LA-C341P
1 1
Compal Confidential
2 2
M/B Schematics Document

Intel Broadwell ULT (Broadwell + Wildcat point)
Nvidia N16S-GT / N16V-GM
3 2015-03-18 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/09/16 Deciphered Date 2014/05/24 Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize DocumentNumber Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAB M/B LA-C341P 0.2
Date: Wednesday, March 18, 2015 Sheet 1 of 56

A B C D E
A B C D E
VGA eDP
Fan Control
page 40
1
page 31 1
page 28
Memory BUS 204pin DDR3L-SO-DIMM X1
BANK 0, 1, 2, 3 page 17
HDMI Conn. Dual Channel
DP to VGA
RTD2168 eDP
Intel Broadwell ULT 1.35V DDR3L 1333/1600
page 30 204pin DDR3L-SO-DIMM X1
BANK 4, 5, 6, 7 page 18
page 29 Broadwell ULT
DP x 2 lanes HDMI x 4 lanes DDI
Processor USB 3.0 USB 2.0
conn x2 conn x1 CMOS
NGFF Card OPI USB port 0, 1 USB/B (port 2) Camera
WLAN Nvidia N16S-GT / N16V-GM USB port 6
USB port 4 with DDR3 x4 or 8
page 34 page 19~27
Touch
PCIe 2.0 PCIe 2.0 x4 Screen
2
5GT/s 5GT/s 2
Wildcat point I2C (PORT0)

port 4 port 5 Flexible IO USB (port 5)
USBx8 page 37 page 37 Page 28 page 28
PCH
PCIe 2.0 48MHz
5GT/s
port 3
port 0 port 1 HD Audio 3.3V 24MHz
SATA HDD SATA CDROM

LAN(GbE)/ Card Reader
Conn. Conn. HDA Codec
Realtek 8411B 1168pin BGA
page 29 ALC255
page 06~16
SPI page 35
Card Reader RJ45 conn.

2 in 1 (SD) LPC BUS
page 36 page 36 SPI ROM x1
3
CLK=24MHz Int. Speaker Int. MIC Universal Jack 3
page 7
USB/B
page 33 page 35 page 35 page 36
ENE
page 33 KB9022 page 38
RTC CKT. Sub Board

page 8
Touch Pad Int.KBD
LS-C341P PS2 / I2C
USB/B
Power On/Off CKT. page 37
page 39
page 39 page 39
DC/DC Interface CKT.

page 41
4 4
Power Circuit DC/DC

page 42~53
Block Diagrams

A B C D E
A B C D E
SIGNAL
Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5 Full ON HIGH HIGH HIGH HIGH ON ON ON ON

VIN Adapter power supply (19V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
BATT+ Battery power supply (12.6V) N/A N/A N/A
+19VB AC or battery power rail for power circuit. N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1
+VGA_CORE Core voltage for GPU ON OFF OFF 1
+0.675VS +0.675VS power rail for DDR3L terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS_VTT +1.05V power rail for CPU ON OFF OFF
Board ID / SKU ID Table for AD channel
+1.05VSDGPU +1.05VSDGPU switched power rail for GPU ON OFF OFF
Vcc 3.3V +/- 5%
+1.35V +1.35V power rail for DDR3L ON ON OFF
Ra/Rc/Re 100K +/- 5%
+1.5VSDGPU +1.5VSDGPU power rail for GPU ON OFF OFF
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5VS +1.5V power rail for CPU ON OFF OFF
0 0 0 V 0 V 0 V
+3VALW +3VALW always on power rail ON ON ON*
1 12K +/- 5% 0.347 V 0.354 V 0.360 V
+3VLP B+ to +3VLP power rail for suspend power ON ON ON
2 15K +/- 5% 0.423 V 0.430 V 0.438 V
+3VS +3VALW to +3VS power rail ON OFF OFF
3 20K +/- 5% 0.541 V 0.550 V 0.559 V
+3VSDGPU +3VS to +3VSDGPU power rail for GPU ON OFF OFF
4 27K +/- 5% 0.691 V 0.702 V 0.713 V
+5VALW +5VALWP to +5VALW power rail ON ON ON*
5 33K +/- 5% 0.807 V 0.819 V 0.831 V
+5VS +5VALW to +5VS power rail ON OFF OFF
6 43K +/- 5% 0.978 V 0.992 V 1.006 V
+RTCVCC RTC power ON ON ON
7 56K +/- 5% 1.169 V 1.185 V 1.200 V
8 75K +/- 5% 1.398 V 1.414 V 1.430 V
9 100K +/- 5% 1.634 V 1.650 V 1.667 V
2 2
10 130K +/- 5% 1.849 V 1.865 V 1.881 V
11 160K +/- 5% 2.015 V 2.031 V 2.046 V
12 200K +/- 5% 2.185 V 2.200 V 2.215 V
13 240K +/- 5% 2.316 V 2.329 V 2.343 V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
USB Port Table BTO Option Table

3 External BTO Item BOM Structure
USB 2.0 Port USB Port Unpop @
0 USB Port (3.0 left front) Connector CONN@
1 USB Port (3.0 left back) UMA Component UMA@
2 USB Port(Right 2.0) GPU VGA@
3 On Board HDD HDD1@
EHCI1
4 Mini Card (WLAN+BT) Wire HDD HDD2@
5 Touch Screen EMI Component EMI@
6 Camera EMI Reserve XEMI@
3 7 ESD Component ESD@ 3
USB 3.0 Port ESD Reserve XESD@

0 USB Port (3.0 left front) TPM Module TPM@
1 USB Port (3.0 Left back) VRAM Selection X76@
XHCI
2 DGPU_IDEN VGL@, VGM@, SGT@
3 CPU_IDEN HW@, BW@

GC6 2.0 GC6@
BOARD ID Table non GC6 NGC6@
EA40 1DMIC@
Board ID PCB Revision VA50 2DMIC@
0 0.1 Power BTN for debug DB@
1 0.2 For 15" V3 series V3@
2 0.3 G-Sensor GSEN@
3 0.4
4 0.5
5 1.0
4 6 4

Notes List

A B C D E
A B C D E
2.2K
+3VS
1 2.2K 1
F2 PCH_I2C0_SDA 0 ohm
0 ohm Touch Screen
F3 PCH_I2C0_SCL
2.2K 2.2K
+3VS 2.2K +3V_PTP

2.2K
G4 PCH_I2C1_SDA D_CK_SDAT A
F1 PCH_I2C1_SCL
DMN63D8LDW D_CK_SCLK PTP
Dual channel NMOS
2.2K 2.2K
+3VALW_PCH 2.2K +3VS

SOC AH1 PCH_SMB_DAT A
2.2K
D_CK_SDAT A
2 2
PCH_SMBCLK SODIMM
AP2 DMN63D8LDW D_CK_SCLK
Dual channel NMOS

G-sensor
2.2K
+3VALW_PCH
2.2K
AK1 SOC_SML0DAT A
AN1 SOC_SML0CLK
2.2K 2.2K
2.2K
+3VALW_PCH 2.2K
+HDMI_5V_OUT
@ 0 ohm
BH10 SOC_SML1CLK EC_SMB_CK2
@ 0 ohm DP to CRT CRT
BG12 SOC_SML1DAT A
DMN63D8LDW
3 EC_SMB_DA2 3
Dual channel NMOS

2.2K
2.2K
+3VALW_EC
EC SM Bus1 address EC SM Bus2 address
77 EC_SMB_CK1 100 ohm 7
SCL1 BATTERY
KBC SDA1
78 EC_SMB_DA1 100 ohm 6
CONN
Device Address Device Address
Smart Battery 0x16 On Board Thermal Senser 0x96
VGA Internal Thermal Senser 0x9E
KB9022 2.2K 2.2K
SCL2
2.2K +3VS 2.2K +3VSDGPU_AON PCH SM Bus address
79
EC_SMB_CK2 Device Address
SDA2
ChannelA DIMM 0 1010 0000 JDIMM 1
80
EC_SMB_DA2 ChannelB DIMM 1 1010 0010 JDIMM 2
4 4
VGA
DMN63D8LDW
Dual channel NMOS

SMB/I2C

A B C D E
A B C D E
VR_ON ISL95813HRZ-T 12000mA

+CPU_CORE
(PU801)
1
+3VSDGPU_MAIN_EN RT8813AGQW 1
+VGA_CORE
(PU1201)
+1.5VS_DGPU_PW R_EN SY8208DQNC

+1.5VSDGPU
ADAPTER (PU101)
SUSP# SY8208DQNC
+1.05VSP
(PU601)
BATTERY +19VB
SYSON
+1.35VP
RT8207MZQW
SUSP#
(PU501)
+0.675VP
2 R-Short 2
CHARGER +5VS_HDD
(R126)
SPOK SY8208DQNC SUSP# JUMP
+5VALWP +5VS +5VS_ODD
(PU402) (J8)
TPS22966DPUR
U11 PCH_ENVDD
+3VLP
+3VS +LCDVDD
(U8)
SPOK SY8208DQNC R-Short

+3VALWP +3V_SPI
(PU401) (R126)
JUMP
+3VALW_PCH
(J8)
LAN_PW R_EN
+3V_LAN
U2504 or R2551
3 3
WLAN_ON
+3V_WLAN
U9 or R
4 4
www.vinafix.vn Issued Date 2013/04/12 Deciphered Date 2014/04/12 Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize DocumentNumber
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Power Rail
A4WAB M/B LA-C341P

Wednesday, March 18, 2015 Sheet 5 of 56
Rev
0.2
A B C D E
5 4 3 2 1
D D
U1A BDW_ULT_DDR3L(Interleaved)
eDP reserve to support 4K2K
C54 C45
<30> SOC_DP1_N0 C55 DDI1_TXN0 EDP_TXN0 B46 EDP_TXN0 <28>
<30> SOC_DP1_P0 B58 DDI1_TXP0 EDP_TXP0 A47 EDP_TXP0<28>
<30> SOC_DP1_N1 C58 DDI1_TXN1 EDP_TXN1 B47 EDP_TXN1 <28>
DP to CRT <30> SOC_DP1_P1 B55 DDI1_TXP1 EDP_TXP1 EDP_TXP1<28>
A55 DDI1_TXN2
DDI1_TXP2 EDP_TXN2
C47
EDP_TXN2 <28>
eDP Panel
A57 C46
B57 DDI1_TXN3 EDP_TXP2 A49 EDP_TXP2<28>
DDI1_TXP3 DDI EDP EDP_TXN3 B49 EDP_TXN3 <28>
C51 EDP_TXP3 EDP_TXP3<28>
<29> CPU_DP2_N0 DDI2_TXN0
C50 A45
<29> CPU_DP2_P0 DDI2_TXP0 EDP_AUXN EDP_AUXN <28>
C53 B45
<29> CPU_DP2_N1 DDI2_TXN1 EDP_AUXP EDP_AUXP <28>
B54
HDMI <29> CPU_DP2_P1
<29> CPU_DP2_N2
C49 DDI2_TXP1
DDI2_TXN2 EDP_RCOMP
D20 EDP_COMP R1 1 2 24.9_0402_1%
+VCCIOA_OUT
B50 A43
<29> CPU_DP2_P2 A53 DDI2_TXP2 EDP_DISP_UTIL
<29> CPU_DP2_N3 B53 DDI2_TXN3 Trace width=20 mils,Spacing=25mil,Max length=100mils
<29> CPU_DP2_P3 DDI2_TXP3
C C
1 OF 19
BDW-ULT-DDR3L-IL_BGA1168
@
+1.35V
+1.05VS_VTT U1B BDW_ULT_DDR3L(Interleaved)

1
2
T20 @ D61
R184 T2 @ K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY#_R
470_0603_5% R68 @ T157
<38> H_PECI PECI PRDY K62
62_0402_5% XDP_PREQ#_R @ T158
R8 PREQ E60 XDP_TCK_R @ T159
PROC_TCK
2
1
56_0402_5% E61 XDP_TMS_R @ T160
DIMM_DRAMRST# <17,18> 1 2 H_PROCHOT#_R K63 PROC_TMS E59
JTAG XDP_TRST#_R @ T161
<19,38> H_PROCHOT# PROCHOT PROC_TRST
1 THERMAL F63 XDP_TDI_R @ T162
ESD@ C95 1 2 .1U_0402_16V7K PROC_TDI F62 XDP_TDO_R @ T163
C96 PROC_TDO
.1U_0402_16V7K R6 1 2 10K_0402_5% H_CPUPWRGD C61
2 PROCPWRGD
ESD@ PW R
ESD@ C60 1 2 .1U_0402_16V7K J60 XDP_BPM#0_R @ T164
BPM#0 H60 XDP_BPM#1_R @ T165
BPM#1 H61 @ T148
Close to AV15 BPM#2 H62 @ T149
R11 1 2 200_0402_1% SM_RCOMP0 AU60 BPM#3 K59 @ T150
DDR3 Compensation Signals R13 1 2 120_0402_1% SM_RCOMP1 AV60 SM_RCOMP0 DDR3L BPM#4 H63 @ T151
Trace width=12~15 mil, Spcing=20 mils 1 2 100_0402_1% SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60
R41 @ T152
Max trace length= 500 mil DIMM_DRAMRST#AV15 SM_RCOMP2 BPM#6 J61 @ T153
B DDR_PG_CTRL AV61 SM_DRAMRST BPM#7 B
<17> DDR_PG_CTRL SM_PG_CNTL1
2 OF 19
@
U1 U1 U1
ZZZ
CPU_Boardwell intel QH18 i3 2.0G CPU_Boardwell intel QH17 i5 2.0G CPU_Boardwell intel QH15 i7 2.2G
PCB A4WAB LA-C341P LS-C341P QH18@ QH17@ QH15@
DAZ1C700100 SA000083D40 SA000083C10 SA000083A10
U1 U1 U1
A CPU_Boardwell intel SR244 i3 2.0G CPU_Boardwell intel SR23Yi5 2.2G CPU_Boardwell intel SR23W i7 2.4G A
SR244@ SR23Y@ SR23W@
SA000083EB0 SA000089960 SA000089A70

BDW MCP(1/11) DDI,MSIC,XDP

5 4 3 2 1
5 4 3 2 1
D DDR interleave routing DDR interleave routing D
U1D BDW_ULT_DDR3L(Interleaved)
U1C BDW_ULT_DDR3L(Interleaved)
<17> DDR_A_D[0..15] DDR_A_D0 AH63 AU37 SA_CLK_DDR#0 <18> DDR_B_D[0..15] DDR_B_D0 AP58 AM38 SB_CLK_DDR#0
SA_DQ0 SA_CLK#0 SA_CLK_DDR#0 <17> SB_DQ0 SB_CK#0 SB_CLK_DDR#0 <18>
DDR_A_D1 AH62 AV37 SA_CLK_DDR0 DDR_B_D1 AR58 AN38 SB_CLK_DDR0
SA_DQ1 SA_CLK0 SA_CLK_DDR0 <17> SB_DQ1 SB_CK0 SB_CLK_DDR0 <18>
DDR_A_D2 AK63 AW36 SA_CLK_DDR#1 DDR_B_D2 AM57 AK38 SB_CLK_DDR#1
SA_DQ2 SA_CLK#1 SA_CLK_DDR#1 <17> SB_DQ2 SB_CK#1 SB_CLK_DDR#1 <18>
DDR_A_D3 AK62 AY36 SA_CLK_DDR1 DDR_B_D3 AK57 AL38 SB_CLK_DDR1
SA_DQ3 SA_CLK1 SA_CLK_DDR1 <17> SB_DQ3 SB_CK1 SB_CLK_DDR1 <18>
DDR_A_D4 AH61 DDR_B_D4 AL58
DDR_A_D5 AH60 SA_DQ4 AU43 DDRA_CKE0_DIMMA DDR_B_D5 AK58 SB_DQ4 AY49 DDRB_CKE0_DIMMB
SA_DQ5 SA_CKE0 DDRA_CKE0_DIMMA <17> SB_DQ5 SB_CKE0 DDRB_CKE0_DIMMB <18>
DDR_A_D6 AK61 AW43 DDRA_CKE1_DIMMA DDR_B_D6 AR57 AU50 DDRB_CKE1_DIMMB
SA_DQ6 SA_CKE1 DDRA_CKE1_DIMMA <17> SB_DQ6 SB_CKE1 DDRB_CKE1_DIMMB <18>
DDR_A_D7 AK60 AY42 DDR_B_D7 AN57 AW49
SA_DQ7 SA_CKE2 @ T0501 SB_DQ7 SB_CKE2 @ T0504
DDR_A_D8 AM63 AY43 DDR_B_D8 AP55 AV50
SA_DQ8 SA_CKE3 @ T0502 SB_DQ8 SB_CKE3 @ T0505
DDR_A_D9 AM62 DDR_B_D9 AR55
DDR_A_D10 AP63 SA_DQ9 AP33 DDRA_CS0_DIMMA# DDR_B_D10 AM54 SB_DQ9 AM32 DDRB_CS0_DIMMB#
SA_DQ10 SA_CS#0 DDRA_CS0_DIMMA# <17> SB_DQ10 SB_CS#0 DDRB_CS0_DIMMB# <18>
DDR_A_D11 AP62 AR32 DDRA_CS1_DIMMA# DDR_B_D11 AK54 AK32 DDRB_CS1_DIMMB#
SA_DQ11 SA_CS#1 DDRA_CS1_DIMMA# <17> SB_DQ11 SB_CS#1 DDRB_CS1_DIMMB# <18>
DDR_A_D12 AM61 DDR_B_D12 AL55
DDR_A_D13 AM60 SA_DQ12 AP32 DDR_B_D13 AK55 SB_DQ12 AL32
SA_DQ13 SA_ODT0 @ T0503 SB_DQ13 SB_ODT0 @ T0506
DDR_A_D14 AP61 DDR_B_D14 AR54
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_A_RAS# DDR_B_D15 AN54 SB_DQ14 AM35 DDR_B_RAS#
<17> DDR_A_D[16..31] SA_DQ15 SA_RAS DDR_A_RAS# <17> <18> DDR_B_D[16..31] SB_DQ15 SB_RAS DDR_B_RAS# <18>
DDR_A_D16 AY58 AW34 DDR_A_WE# DDR_B_D16 AK40 AK35 DDR_B_WE#
SA_DQ16 SA_WE DDR_A_WE# <17> SB_DQ16 SB_WE DDR_B_WE# <18>
DDR_A_D17 AW58 AU34 DDR_A_CAS# DDR_B_D17 AK42 AM33 DDR_B_CAS#
SA_DQ17 SA_CAS DDR_A_CAS# <17> SB_DQ17 SB_CAS DDR_B_CAS# <18>
DDR_A_D18 AY56 DDR_B_D18 AM43
DDR_A_D19 AW56 SA_DQ18 AU35 DDR_A_BS0 DDR_B_D19 AM45 SB_DQ18 AL35 DDR_B_BS0
SA_DQ19 SA_BA0 DDR_A_BS0 <17> SB_DQ19 SB_BA0 DDR_B_BS0 <18>
DDR_A_D20 AV58 AV35 DDR_A_BS1 DDR_B_D20 AK45 AM36 DDR_B_BS1
DDR_A_D21 AU58 AY41 DDR_A_BS2 DDR_B_D21 AK43 AU49 DDR_B_BS2
DDR_A_D22 AV56 DDR_B_D22 AM40
SA_DQ22 DDR_A_MA[0..15] <17> SB_DQ22 DDR_B_MA[0..15] <18>
DDR_A_D23 AU56 AU36 DDR_A_MA0 DDR_B_D23 AM42 AP40 DDR_B_MA0
DDR_A_D24 AY54 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D24 AM46 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D25 AW54 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D25 AK46 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
C DDR_A_D26 AY52 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D26 AM49 SB_DQ25 SB_MA2 AR42 DDR_B_MA3 C
DDR_A_D27 AW52 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D27 AK49 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D28 AV54 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D28 AM48 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D29 AU54 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D29 AK48 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_A_D30 AV52 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D30 AM51 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D31 AU52 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDR_A_MA8 DDR_B_D31 AK51 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
<17> DDR_A_D[32..47] DDR_A_D32 AY31 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 <18> DDR_B_D[32..47] DDR_B_D32 AM29 SB_DQ31 DDR CHANNEL B SB_MA8 AU46 DDR_B_MA9
DDR_A_D33 AW31 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D33 AK29 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D34 AY29 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D34 AL28 SB_DQ33 SB_MA10 AV47 DDR_B_MA11
DDR_A_D35 AW29 SA_DQ34 SA_MA11 AU41 DDR_A_MA12 DDR_B_D35 AK28 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D36 AV31 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D36 AR29 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D37 AU31 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D37 AN29 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D38 AV29 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D38 AR28 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
DDR_A_D39 AU29 SA_DQ38 SA_MA15 DDR_B_D39 AP28 SB_DQ38 SB_MA15
SA_DQ39 DDR_A_DQS#[0..1] <17> SB_DQ39 DDR_B_DQS#[0..1] <18>
DDR_A_D40 AY27 AJ61 DDR_A_DQS#0 DDR_B_D40 AN26 AM58 DDR_B_DQS#0
DDR_A_D41 AW27 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_B_D41 AR26 SB_DQ40 SB_DQSN0 AM55 DDR_B_DQS#1
SA_DQ41 SA_DQSN1 DDR_A_DQS#[2..3] <17> SB_DQ41 SB_DQSN1 DDR_B_DQS#[2..3] <18>
DDR_A_D42 AY25 AV57 DDR_A_DQS#2 DDR_B_D42 AR25 AL43 DDR_B_DQS#2
DDR_A_D43 AW25 SA_DQ42 SA_DQSN2 AV53 DDR_A_DQS#3 DDR_B_D43 AP25 SB_DQ42 SB_DQSN2 AL48 DDR_B_DQS#3
DDR_A_D44 AV27 AW30 DDR_A_DQS#4 DDR_B_D44 AK26 AN28 DDR_B_DQS#4
DDR_A_D45 AU27 SA_DQ44 SA_DQSN4 AV26 DDR_A_DQS#5 DDR_B_D45 AM26 SB_DQ44 SB_DQSN4 AN25 DDR_B_DQS#5
DDR_A_D46 AV25 AW22 DDR_A_DQS#6 DDR_B_D46 AK25 AN21 DDR_B_DQS#6
DDR_A_D47 AU25 SA_DQ46 SA_DQSN6 AV18 DDR_A_DQS#7 DDR_B_D47 AL25 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
<17> DDR_A_D[48..63] DDR_A_D48 AY23 SA_DQ47 SA_DQSN7 <18> DDR_B_D[48..63] DDR_B_D48 AR21 SB_DQ47 SB_DQSN7
SA_DQ48 DDR_A_DQS[0..1] <17> SB_DQ48 DDR_B_DQS[0..1] <18>
DDR_A_D49 AW23 AJ62 DDR_A_DQS0 DDR_B_D49 AR22 AN58 DDR_B_DQS0
DDR_A_D50 AY21 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AN55 DDR_B_DQS1
SA_DQ50 SA_DQSP1 DDR_A_DQS[2..3] <17> SB_DQ50 SB_DQSP1 DDR_B_DQS[2..3] <18>
DDR_A_D51 AW21 AW57 DDR_A_DQS2 DDR_B_D51 AM22 AL42 DDR_B_DQS2
DDR_A_D52 AV23 SA_DQ51 SA_DQSP2 AW53 DDR_A_DQS3 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AL49 DDR_B_DQS3
DDR_A_D53 AU23 AV30 DDR_A_DQS4 DDR_B_D53 AP21 AM28 DDR_B_DQS4
DDR_A_D54 AV21 SA_DQ53 SA_DQSP4 AW26 DDR_A_DQS5 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AM25 DDR_B_DQS5
DDR_A_D55 AU21 AV22 DDR_A_DQS6 DDR_B_D55 AK22 AM21 DDR_B_DQS6
DDR_A_D56 AY19 SA_DQ55 SA_DQSP6 AW18 DDR_A_DQS7 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_A_D57 AW19 SA_DQ56 SA_DQSP7 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
B DDR_A_D58 AY17 SA_DQ57 AP49 SM_DIMM_VREFCA DDR_B_D58 AK18 SB_DQ57 B
SA_DQ58 SM_VREF_CA SM_DIMM_VREFCA <17> SB_DQ58
DDR_A_D59 AW17 AR51 SA_DIMM_VREFDQ DDR_B_D59 AL18
SA_DQ59 SM_VREF_DQ0 SA_DIMM_VREFDQ <17> SB_DQ59
DDR_A_D60 AV19 AP51 SB_DIMM_VREFDQ DDR_B_D60 AK20
SA_DQ60 SM_VREF_DQ1 SB_DIMM_VREFDQ <18> SB_DQ60
DDR_A_D61 AU19 DDR_B_D61 AM20
DDR_A_D62 AV17 SA_DQ61 Trace width >= 10mils DDR_B_D62 AR18 SB_DQ61
DDR_A_D63 AU17 SA_DQ62 DDR_B_D63 AP18 SB_DQ62
SA_DQ63 SB_DQ63
4 OF 19
3 OF 19 BDW-ULT-DDR3L-IL_BGA1168
BDW-ULT-DDR3L-IL_BGA1168 @
@
A A

BDW MCP(2/11) DDRIII

5 4 3 2 1
5 4 3 2 1
PCH_RTCX1
RTC X'tal
1 2 PCH_RTCX2
R101 10M_0402_5%
Y1
2 1
32.768KHZ_12.5PF_9H03200042
1 1
C153 C154
15P_0402_50V8J 18P_0402_50V8J
D 2 2 D
For BDW,
Crystal change to SJ10000LV00 (ESR=50k Ohm)
RTC Reset
1
+RTCVCC
C149
R69 1U_0402_6.3V6K
20K_0402_1% 2
1 2 PCH_SRTCRST#
1 2 PCH_RTCRST#
R70
1
20K_0402_1% 1
C150 @ @
1U_0402_6.3V6K JCMOS1 JCMOS2
0_0603_5% 0_0603_5% U1E BDW_ULT_DDR3L(Interleaved)
2
2
+RTCVCC
R72 PCH_RTCX1 AW5
1M_0402_5% PCH_RTCX2 AY5 RTCX1
JCMOS1 close RAM door 1 2 SM_INTRUDER# AU6 RTCX2 J5
INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0<36>
PCH_INTVRMEN AV7 H5
PCH_SRTCRST# AV6 INTVRMEN
SRTCRST
RTC
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
B15
SATA_PRX_DTX_P0<36>
SATA_PTX_DRX_N0<36>
HDD
PCH_RTCRST# AU7 A15
C RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0<36> C
D
1
J8
INTVRMEN +RTCVCC
<38> EC_RTCRST#
2 Q52 SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
H8
SATA_PRX_DTX_N1<36>
SATA_PRX_DTX_P1<36>
G @ L2N7002LT1G_SOT23-3 A17
S
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
B17 SATA_PTX_DRX_N1<36>
SATA_PTX_DRX_P1<36>
ODD
3
PCH_INTVRMEN R73 1 2 330K_0402_5%
R74 1 @ 2 330K_0402_5% HDA_BIT_CLK AW8 J6
HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
HDA_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14
* HL：：Integrated
Integrated VRM enable
VRM disable
<35> HDA_SDIN0
T6
HDA_SDIN0
@
AY10
AU12
HDA_RST/I2S_MCLK
HDA_SDI0/I2S0_RXD
AUDIO SATA SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
C15
HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5

T7 @ AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5
T8 @ AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17
AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17
T9 @
I2S1_SCLK SATA_TP3/PETP6_L0
HDA for AUDIO
ME Debug SATA0GP/GPIO34
V1 PCH_GPIO34
PCH_GPIO34 <11>
<38> HDA_SDO R122 1 @ 2 0_0402_5% U1 PCH_GPIO35
SATA1GP/GPIO35 V6 PCH_GPIO36 PCH_GPIO35 <11> +1.05VS_ASATA3PLL
SATA2GP/GPIO36 AC1 PCH_GPIO37 PCH_GPIO36 <11>
RP14 EMI@
1 8 HDA_RST# PCH_JTAG_RST# AU62 SATA3GP/GPIO37 PCH_GPIO37 <11>
<35> HDA_RST_AUDIO# T95 @
2 7 HDA_BIT_CLK T110 @ PCH_JTAG_TCK AE62 PCH_TRST A12 SATA_IREF R75 1 @ 2 0_0603_5%
<35> HDA_BITCLK_AUDIO PCH_TCK SATA_IREF
3 6 HDA_SDOUT T21 @ PCH_JTAG_TDI AD61 L11 @ T13
<35> HDA_SDOUT_AUDIO PCH_TDI RSVD
4 5 HDA_SYNC T19 @ PCH_JTAG_TDO AE61 K10 @ T14
<35> HDA_SYNC_AUDIO PCH_TDO RSVD
T15 @ PCH_JTAG_TMS AD62 JTAG C12 SATA_RCOMP R2 1 2 3.01K_0402_1%
33_0804_8P4R_5% T10 @ AL11 PCH_TMS SATA_RCOMP U3 R10 1 2
RSVD SATALED +3VS
T11 @ AC4 10K_0402_5%
T22 @ PCH_TCK_JTAGX AE63 RSVD
JTAGX SA TA_RCOMP, IREF
T12 @ AV2 Trace width=12~15 mil, Spcing=12 mils
RSVD
Max trace length= 500 mil
B B
RTC Battery
5 OF 19
W =20mils trace width 10mil W =20mils @
+RTCBATT +CHGRTC +RTCVCC

D23
2
BAS40-04_SOT23-3 1
C151
.1U_0402_16V7K
2
A A

BDW MCP(3/11) RTC,SATA,XDP

5 4 3 2 1
5 4 3 2 1
U1F BDW_ULT_DDR3L(Interleaved)
C43 A25 XTAL24_IN

C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT
PCH_GPIO18 U2 CLKOUT_PCIE_P0 XTAL24_OUT
<11> PCH_GPIO18 PCIECLKRQ0/GPIO18 K21 @ T16
B41 RSVD M21 @ T17
A41 CLKOUT_PCIE_N1 RSVD C26 XCLK_BIASREF 1 2 3.01K_0402_1%
R78 +1.05VS_AXCK_LCPLL
D XTAL24_IN PCH_GPIO19 Y5 CLKOUT_PCIE_P1 DIFFCLK_BIASREF D
<11> PCH_GPIO19 PCIECLKRQ1/GPIO19 C35 1 2
R140 10K_0402_5%
2 1 XTAL24_OUT CLK_PCIE_LAN# C41 CLOCK TESTLOW_C35 C34 1 2
R141 10K_0402_5%
1M_0402_5% R48 PCIE LAN <32> CLK_PCIE_LAN#
<32> CLK_PCIE_LAN
CLK_PCIE_LAN B42 CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
TESTLOW_C34
TESTLOW_AK8
AK8 R142 1 2 10K_0402_5%
+3VS R52 1 2 10K_0402_5% AD1 SIGNALS AL8 R148 1 2 10K_0402_5%
Y2 PCIECLKRQ2/GPIO20 TESTLOW_AL8
<32> LAN_CLKREQ#
24MHZ_12PF_X3G024000DC1H CLK_PCIE_MINI1# B38 AN15 CLKOUT_LPC0 R390 2 EMI@ 1 22_0402_5%
1 3 <34> CLK_PCIE_MINI1# CLK_PCIE_MINI1 C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLKOUT_LPC1 2 TPM@ 1 22_0402_5% CLK_PCI_LPC <38>
R395
2 4 WLAN <34> CLK_PCIE_MINI1
<10,34> MINI1_CLKREQ#
MINI1_CLKREQ# N1 CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
CLKOUT_LPC_1 CLK_PCI_TPM <39>
B35 CLK_BCLK_ITP# @ T184
CLKOUT_ITPXDP
1
1
CLK_PEG_VGA# A39 A35 CLK_BCLK_ITP @ T183
<19> CLK_PEG_VGA# B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
C2 C3 CLK_PEG_VGA
15P_0402_50V8J 15P_0402_50V8J VGA <19> CLK_PEG_VGA VGA_CLKREQ# U5 CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
2
B37
A37 CLKOUT_PCIE_N5
PCH_GPIO23 T2 CLKOUT_PCIE_P5
<11> PCH_GPIO23 PCIECLKRQ5/GPIO23
6 OF 19
@
U1G BDW_ULT_DDR3L(Interleaved)
LPC_AD0 AU14 AN2 PCH_GPIO11

<38,39> LPC_AD0 LPC_AD1 AW12 LAD0 SMBALERT/GPIO11 AP2 PCH_SMBCLK PCH_GPIO11 <11>
<38,39> LPC_AD1 AY12 LAD1 SMBCLK AH1
LPC_AD2 LPC PCH_SMBDATA
<38,39> LPC_AD2 AW11 LAD2 SMBDATA AL2
LPC_AD3 SMBUS PCH_GPIO60
<38,39> LPC_AD3 LPC_FRAME# AV12 LAD3 SML0ALERT/GPIO60 AN1 SOC_SML0CLK PCH_GPIO60 <11>
C +3VS <38,39> LPC_FRAME# LFRAME SML0CLK AK1 C
SOC_SML0DATA
SML0DATA AU4 PCH_GPIO73
SML1ALERT/PCHHOT/GPIO73 AU3 PCH_GPIO73 <11>
SOC_SML1CLK
<19,41,52> VGA_PWROK SML1CLK/GPIO75
1
AH3 SOC_SML1DATA
R115 PCH_SPI_CLK AA3 SML1DATA/GPIO74
VGA@ 10K_0402_5% PCH_SPI_CS0# Y7 SPI_CLK AF2 @ T23
SPI_CS0 CL_CLK
2
Y4 AD2
G
L2N7002LT1G_SOT23-3 Q2 @ T24
AC2 SPI_CS1 SPI C-LINK
CL_DATA AF4 @ T25
Pull high @ VGA side SPI_CS2 CL_RST
2
3 1 VGA_CLKREQ# PCH_SPI_MOSI AA2

<19> PEG_CLKREQ# PCH_SPI_MISO AA4 SPI_MOSI
S
SPI_MISO
1
PCH_SPI_WP1# Y6
R107 R112 PCH_SPI_HOLD1# AF1 SPI_IO2
2.2K_0402_5% 2.2K_0402_5% SPI_IO3
@ @
7 OF 19
2
@
+3VALW_PCH
SPI ROM SMBUS +3VS RP8
B SOC_SML0CLK 1 8 B
+3VS PCH_SMBCLK 2 7
PCH_SMBDATA 3 6
for Share EC ROM, +3VS
2
SOC_SML0DATA 4 5
+3V_SPI Q7A R116 R119
change to +3VALW
2
L2N7002DW1T1G_SC88-6 4.7K_0402_5% 4.7K_0402_5% 2.2K_0804_8P4R_5%
R105 1 2 1K_0402_5% PCH_SPI_IO2_1
R106 1 2 1K_0402_5% PCH_SPI_IO3_1 +3VALW +3V_SPI SOC_SML1CLK R114 1 2 2.2K_0402_5%
1
PCH_SMBDATA 6 1 D_CK_SDATA SOC_SML1DATA R113 1 2 2.2K_0402_5%
D_CK_SDATA <17,18,40>
R126 2 @ 1 0_0402_5%
5
+3V_SPI
R108
DDR , G-Sensor
15_0402_5% PCH_SMBCLK 3 4D_CK_SCLK
SPI ROM ( 8MByte ) C66 1 2 PCH_SPI_IO2_1 1 2 PCH_SPI_WP1#
D_CK_SCLK <17,18,40>
U6 Q7B
PCH_SPI_CS0# 1 8 .1U_0402_16V7K RP19 L2N7002DW1T1G_SC88-6
PCH_SPI_MISO_1 2 /CS VCC 7 PCH_SPI_IO3_1 PCH_SPI_IO3_1 1 8 PCH_SPI_HOLD1#
PCH_SPI_IO2_1 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_1 PCH_SPI_CLK_1 2 7 PCH_SPI_CLK SPI ROM +3VS
4 /WP(IO2) CLK 5 PCH_SPI_MOSI_1 PCH_SPI_MOSI_1 3 6 PCH_SPI_MOSI
GND DI(IO0) PCH_SPI_MISO_1 4 5 PCH_SPI_MISO
W25Q64FVSSIQ_SO8 EMI@
2
15_0804_8P4R_5% Q8A
L2N7002DW1T1G_SC88-6
PU 2.2K at EC side (+3VS)
Reserve for EMI(Near SPI ROM) PCH_SPI_MOSI_1 R498 1 @ 2 0_0402_5% SOC_SML1CLK 6 1 EC_SMB_CK2 <19,30,38>
EC_SPI_SO <38>
C152 PCH_SPI_CLK_1 R500 1 @ 2 0_0402_5% From EC
EC_SPI_CLK <38> (For share ROM)
10P_0402_50V8J PCH_SPI_MISO_1 R502 1 @ 2 0_0402_5%
EC_SPI_SI <38>
5
1 2 2 1 PCH_SPI_CLK_1 PCH_SPI_CS0# R505 1 @ 2 0_0402_5% EC_SPI_CS# <38>
R104 33_0402_5% VGA, EC
XEMI@ XEMI@
A SOC_SML1DATA 3 4 EC_SMB_DA2 <19,30,38>
A
10/20: 2015 project not implement auto load,

change R498, R500, R502, R502 to non-pop. Q8B

BDW MCP(4/11) CLK,SPI,SMBUS

5 4 3 2 1
5 4 3 2 1
System Power
Management
PCH_RSMRST# R117 1 2 10K_0402_5%
D D
+3VALW_PCH
1
R245
100K_0402_5%
@ D21 Note: Deep Sx need use EC GPIO for

2
1 2 PCH_ACIN ACPRESENT function DSW ODVREN - On Die DSW VR Enable

<38,44> ACIN
RB751V-40SOD-323
* HL：：Disable
Enable(DEFAULT)
+RTCVCC
U1H BDW_ULT_DDR3L(Interleaved)
@ R65 R124 1 2 330K_0402_5%
0_0402_5% SYSTEM POWER MANAGEMENT R125 1 @ 2 330K_0402_5%
SYS_PWROK 1 2 PCH_PWROK
SUSWARN# R206 1 @ 2 0_0402_5% SUSACK# AK2 AW7 DSWODVREN
R227 1 2 10K_0402_5% SYS_RESET# AC3 SUSACK DSWVRMEN AV5 PCH_RSMRST#_R
+3VS SYS_RESET DPWROK
1
SYS_PWROK R61 1 @ 2 0_0402_5% SYS_PWROK_R AG2 AJ5 PCH_PCIE_WAKE#

1 2 AY7 SYS_PWROK WAKE
R207 <38> PCH_PWROK R62 @ 0_0402_5% PCH_PWROK_R R120 1 2 1K_0402_5%
+3VALW_PCH
1 2 AB5 PCH_PWROK
10K_0402_5% <13,38> VCCST_PG_EC R63 @ 0_0402_5% PM_APWROK R157 1 2 8.2K_0402_5%
+3VS
AG7 APWROK V5 CLKRUN#
PLTRST CLKRUN/GPIO32 CLKRUN# <39>
PCH_PWROK_R R64 1 @ 2 0_0402_5% AG4
SUS_STAT/GPIO61
2
PLT_RST# AE6 SUSCLK

<19,38,39> PLT_RST# SUSCLK/GPIO62 AP5 PM_SLP_S5# SUSCLK <34>
1 2 0_0402_5% PCH_RSMRST#_R AW6 SLP_S5/GPIO63 PM_SLP_S5# <38>
<38> PCH_RSMRST# R79 @ @ T27
SUSWARN# AV4 RSMRST
@ T28 @ T29
<11> SUSWARN# SUSWARN/SUSPWRDNACK/GPIO30
<38> PBTN_OUT# R110 1 @ 2 0_0402_5% PBTN_OUT#_R AL7 AJ6 PM_SLP_S4#
C AJ8 PWRBTN SLP_S4 AT4 PM_SLP_S4# <38> C
PCH_ACIN PM_SLP_S3#
ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# <38>
R2634 +3VALW_PCH R156 1 2 8.2K_0402_5%PCH_BATLOW# AN4 AL5 @ T30
0_0402_5% T31 @ AF3 BATLOW/GPIO72 SLP_A AP4 @ T96
1 2 AM5 SLP_S0 SLP_SUS AJ7 PM_SLP_LAN# R118 1 @ 2
SLP_WLAN/GPIO29 SLP_LAN +3VALW_PCH
10K_0402_5%
+3VS
not support Deep S4,S5 can NC
8 OF 19
5
PLT_RST# 2 @
P
B 4
1 Y PLT_RST_BUF# <32,34>
A
G
R416
3
U30 @ 100K_0402_5%
MC74VHC1G08DFT2G_SC70-5
2
U1I BDW_ULT_DDR3L(Interleaved)
+3VS
B8 B9
<28> PCH_INV_PWM EDP_BKLCTL DDPB_CTRLCLK
A9 C9 R271 1 2 2.2K_0402_5%
<38> ENBKL C6 EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA D9 DDI2_CTRL_CK
<28> PCH_ENVDD EDP_VDDEN DDPC_CTRLCLK D11 DDI2_CTRL_DATA DDI2_CTRL_CK <29>
DDPC_CTRLDATA DDI2_CTRL_DATA <29>
R2057
+3VS 10/15 : RP27 pin 8 remove G_SEN_INT# pull high. 0_0402_5%
2 GC6@ 1 PCH_GPIO77 U6
<19> GC6_FB_EN PIRQA/GPIO77
B DGPU_PWR_EN P4 C5 SOC_DP1_AUXN B
<11,41,52> DGPU_PWR_EN PIRQB/GPIO78 DDPB_AUXN SOC_DP1_AUXN <30>
RP27 1 8 DGPU_HOLD_RST# N4 B6
2 7 PCH_GPIO80 <19> DGPU_HOLD_RST# PCH_GPIO80 N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5 SOC_DP1_AUXP
3 6 MINI1_CLKREQ# AD4 PIRQD/GPIO80 DDPB_AUXP A6 SOC_DP1_AUXP <30>
@ T26
MINI1_CLKREQ# <9,34> PME DDPC_AUXP
4 5 DEVSLP0 D22 1 2 RB751V-40_SOD323-2 PCIE
DEVSLP0 <11> <38,39> EC_TP_INT#
10K_0804_8P4R_5% TP_INT# U7
<11> TP_INT# GPIO55
R210 G_SEN_INT L1
+3VS <40> G_SEN_INT GPIO52
Project_ID1 L3 C8
GPIO54 DDPB_HPD SOC_DP1_HPD <30>
PCH_GPIO51 R5 A8
<11> PCH_GPIO51 GPIO51 DDPC_HPD CPU_HDMI_HPD <29>
Project_ID0 L4 D6
GPIO53 EDP_HPD CPU_EDP_HPD <28>
R210 1 NGC6@ 2 PCH_GPIO77
10K_0402_5% 10K_0402_5%
UMA@ DDPB_CTRLDATA: Port B Detected
R2629 1 VGA@ 2 DGPU_HOLD_RST# SD028100280 9 OF 19
DDPC_CTRLDATA: P ort C Detected
10K_0402_5% @
*
1: Port B or C is detected
0: Port B or C is not detected
(Have internal PD)

+3VS +3VS
1
@ R205 @ R204
10K_0402_5% 10K_0402_5% Project_ID1 Project_ID0
Project ID
GPIO54 GPIO53
2
A Project_ID1 Project_ID0 A
* A4WAB 0 0
2
R214 R215 Reserved 0 1

10K_0402_5% 10K_0402_5%
Reserved 1 0
Reserved 1 1
1

BDW MCP(5/11) PM,GPIO,DDI

5 4 3 2 1
5 4 3 2 1
+3VS
RP23 1 8 PCH_GPIO87
2 7 PCH_GPIO51 +1.05VS_VTT
PCH_GPIO51 <10>
3 6
4 5 PCH_GPIO83
1
10K_0804_8P4R_5% U1J BDW_ULT_DDR3L(Interleaved)
RP24 1 8 PCH_GPIO68 R144
D 2 7 PCH_GPIO69 1K_0402_5%
D
3 6
4 5 change to I2C0 for TS use
2
10K_0804_8P4R_5% PCH_GPIO76 P1 D60 H_THERMTRIP#
RP25 1 8 PCH_GPIO1 PCH_GPIO8 AU2 BMBUSY/GPIO76 THRMTRIP V4
2 7 AM7 GPIO8 RCIN/GPIO82 T4 EC_KBRST# <38>
PCH_GPIO94 SERIRQ
LAN_PHY_PWR_CTRL/GPIO12 SERIRQ SERIRQ <38,39>
3 6 PCH_GPIO93 EC_LID_OUT# AD6 CPU/ AW15 PCH_OPIRCOMP 1 2 R145
<38> EC_LID_OUT# GPIO15 PCH_OPI_RCOMP
4 5 PCH_GPIO2 PCH_GPIO16 Y1 MISC AF20 @ T106 49.9_0402_1%
PCH_GPIO17 T3 GPIO16 RSVD AB21
10K_0804_8P4R_5% @ T32
GPIO17 RSVD
RP26 1 8 PCH_GPIO24 AD5
2 7 PCH_GPIO0 CPU_IDEN AN5 GPIO24
3 6 PCH_GPIO90 PCH_GPIO28 AD7 GPIO27
4 5 PCH_GPIO38 DGPU_IDEN AN3 GPIO28
10K_0804_8P4R_5% GPIO26 R6 PCH_GPIO83
RP16 1 8 PCH_GPIO19 PCH_GPIO56 AG6 GSPI0_CS/GPIO83 L6 PCH_GPIO84
PCH_GPIO19 <9> GPIO56 GSPI0_CLK/GPIO84
2 7 PCH_GPIO36 PCH_GPIO57 AP1 N6 PCH_GPIO85
PCH_GPIO36 <8> GPIO57 GSPI0_MISO/GPIO85
3 6 TP_INT# PCH_GPIO58 AL4 L8 PCH_GPIO86
TP_INT# <10> GPIO58 GSPI0_MOSI/GPIO86
4 5 SERIRQ PCH_GPIO59 AT5 R7 PCH_GPIO87
PCH_GPIO44 AK4 GPIO59 GPIO GSPI1_CS/GPIO87 L5 PCH_GPIO88
10K_0804_8P4R_5% R71
RP28 1 8 PCH_GPIO18 0_0402_5% PCH_GPIO47 AB6 GPIO44 GSPI1_CLK/GPIO88 N7 PCH_GPIO89
PCH_GPIO18 <9> GPIO47 GSPI1_MISO/GPIO89
2 7 PCH_GPIO35 1 @ 2 PCH_GPU_ACIN U4 K2 PCH_GPIO90
PCH_GPIO35 <8> <19,38> DGPU_AC_DETECT GPIO48 GSPI_MOSI/GPIO90
3 6 PCH_GPU_ACIN DGPU_PRSNT# Y3 J1 UART_0_CRXD_DTXD
GPIO49 UART0_RXD/GPIO91 UART_0_CRXD_DTXD <34>
4 5 PCH_GPIO34 I2C_TS_INT# P3 K3 UART_0_CTXD_DRXD
PCH_GPIO34 <8> <28> I2C_TS_INT# GPIO50 UART0_TXD/GPIO92 UART_0_CTXD_DRXD <34>
10K_0804_8P4R_5% PCH_GPIO71 Y2 J2 PCH_GPIO93
HSIOPC/GPIO71 UART0_RTS/GPIO93
RP29 1 8 PCH_GPIO71 PCH_GPIO13 AT3 SERIAL IO G1 PCH_GPIO94
2 7 PCH_GPIO16 PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0
3 6 EC_KBRST# PCH_GPIO25 AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1
4 5 PCH_GPIO37 PCH_GPIO45 AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2
PCH_GPIO37 <8> GPIO45 UART1_RST/GPIO2
10K_0804_8P4R_5% PCH_GPIO46 AG3 J4 PCH_GPIO3
GPIO46 UART1_CTS/GPIO3 F2 PCH_I2C0_SDA
I2C0_SDA/GPIO4 PCH_I2C0_SDA <28>
RP30 8 1 PCH_GPIO67 PCH_GPIO9 AM3 F3 PCH_I2C0_SCL
Touch Screen
7 2 PCH_GPIO65 PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 PCH_I2C1_SDA PCH_I2C0_SCL <28>
C 6 3 P2 GPIO10 I2C1_SDA/GPIO6 F1 PCH_I2C1_SDA <39> C
DEVSLP0 PCH_I2C1_SCL Touch Pad
5 4 <10> DEVSLP0 2 1 C4 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 E3 PCH_I2C1_SCL <39>
PCH_GPIO64 PCH_GPIO70 PCH_GPIO64
<19> GPU_EVENT# L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4
10K_0804_8P4R_5% R2058 GC6@ 0_0402_5% PCH_GPIO38 PCH_GPIO65
RP31 8 1 EC_SMI#_SCI# N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66
<38> EC_SMI#_SCI# DEVSLP2/GPIO39 SDIO_D0/GPIO66
7 2 PCH_GPIO3 PCH_SPKR V2 E4 PCH_GPIO67
6 3 PCH_GPIO89 <35> PCH_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 C3 PCH_GPIO68
5 4 PCH_GPIO84 SDIO_D2/GPIO68 E2 PCH_GPIO69
R216
10K_0804_8P4R_5% SDIO_D3/GPIO69
RP32 8 1 PCH_GPIO23 10 OF 19 +3VS
PCH_GPIO23 <9>
7 2 PCH_GPIO17 BDW-ULT-DDR3L-IL_BGA1168
6 3 PCH_GPIO76 @ PCH_I2C0_SDA R277 1 2 2.2K_0402_5%
5 4
10K_0804_8P4R_5% 10K_0402_5% PCH_I2C0_SCL R276 1 2 2.2K_0402_5%
UMA@
R216 1 NGC6@ 2 PCH_GPIO70 SD028100280 PCH_I2C1_SDA R275 1 2 2.2K_0402_5%
10K_0402_5%
R217 1 2 DGPU_PWR_EN PCH_I2C1_SCL R274 1 2 2.2K_0402_5%
DGPU_PWR_EN <10,41,52>
10K_0402_5%
Pre MP modify 03/10
RP36 1 8 EC_SMI#_SCI# solve VGA sequence error issue
2 7 PCH_GPIO85
3 6
4 5 PCH_GPIO88
10K_0804_8P4R_5%
R615 1 2 100K_0402_5% I2C_TS_INT#
R2616 1 2 UART_0_CRXD_DTXD
10K_0402_5%
R2617 1 2 UART_0_CTXD_DRXD
10K_0402_5%
B +3VS +3VS B
+3VALW_PCH +3VALW_PCH
+3VALW_PCH PCH_GPIO86 R272 1 @ 2 1K_0402_5% R269 1 @ 2 1K_0402_5% PCH_SPKR
1
1
R273 1 2 1K_0402_5%
R311 R2608
RP34 1 8 PCH_GPIO10 10K_0402_5% 10K_0402_5%
2 7 PCH_GPIO11
3 6 PCH_GPIO57 PCH_GPIO11 <9>
VGM@
GPIO26 SR@
GPIO28 GSPI0_MOSI / GPIO86 : Boot BIOS Strap SPKR / GPIO81 : NO REBOOT
2
2
4 5 PCH_GPIO13 VGA INFO CPU INFO
10K_0804_8P4R_5% DGPU_IDEN PCH_GPIO28 1: ENABLED 1: ENABLED
1 8 USB_OC1#
RP35
USB_OC1# <12,37> N15V-GM 1 Single Rank 1
2
2 7 PCH_GPIO8 2
* *
0: SPI ROM (Have internal PD) 0: DISABLED (Have internal PD)
3 6 PCH_GPIO73
4 5 SUSWARN# PCH_GPIO73 <9>
R220
10K_0402_5%
N15V-GL 0 R2609
10K_0402_5%
Dual Rank 0
SUSWARN# <10>
10K_0804_8P4R_5% VGL@ DR@
RP37 1 8 PCH_GPIO46
1
2 7 PCH_GPIO42
PCH_GPIO42 <12>
3 6 PCH_GPIO14
4 5 PCH_GPIO56 +3VALW_PCH
10K_0804_8P4R_5%
RP38 1 8 +3VALW_PCH +3VS
2 7 PCH_GPIO47 R247 1 @ 2 10K_0402_5% EC_LID_OUT# PCH_GPIO66 R270 1 @ 2 1K_0402_5%
1
3 6 PCH_GPIO45
4 5 PCH_GPIO24 R312 R306
10K_0804_8P4R_5% 10K_0402_5% 10K_0402_5% GPIO15 : TLS Confidentiality
RP39 1 8 PCH_GPIO43
2 7 PCH_GPIO59
PCH_GPIO43 <12>
BW@
GPIO27 UMA@
GPIO49 SDIO_D0 / GPIO66 : Top-Block Swap Override
2
3 6 PCH_GPIO25 CPU INFO DGPU_PRSNT# 1: Intel ME TLS with confidentiality

4 5 PCH_GPIO58 CPU_IDEN DGPU_PRSNT#
Boradwell 1 UMA 1
*
10K_0804_8P4R_5% 0: Intel ME TLS with no confidentiality 1: ENABLED
2
RP40 1 8 PCH_GPIO44
2 7 PCH_GPIO60
Haswell 0 DIS,Optimus 0
*
PCH_GPIO60 <9> R221 R219 (Have internal PD) 0: DISABLED (Have internal PD)
A 3 6 USB_OC0# 10K_0402_5% 10K_0402_5% A
4 5 PCH_GPIO9 USB_OC0# <12,37>
HW@ VGA@
10K_0804_8P4R_5%
1

BDW MCP(6/11) GPIO,LPIO

5 4 3 2 1
5 4 3 2 1
D D
PEG_HRX_C_GTX_N[0..3] <19>
PEG_HRX_C_GTX_P[0..3] <19>
PEG_HTX_C_GRX_N[0..3] <19>
PEG_HTX_C_GRX_P[0..3] <19>
U1K BDW_ULT_DDR3L(Interleaved)
PEG_HRX_C_GTX_N0 C76 1 2 VGA@ 0.22U_0402_16V7K PEG_HRX_GTX_N0 F10 AN8 USB20_N0

PEG_HRX_C_GTX_P0 C77 1 2 VGA@ 0.22U_0402_16V7K PEG_HRX_GTX_P0 E10 PERN5_L0
PERP5_L0
USB2N0
USB2P0
AM8 USB20_P0 USB20_N0 <37>
USB20_P0 <37>
USB2 Port 0 (USB3.0 P1)
PEG_HTX_C_GRX_N0 C78 1 2 VGA@ 0.22U_0402_16V7K PEG_HTX_GRX_N0 C23 AR7 USB20_N1
PEG_HTX_C_GRX_P0 C79 1 2 VGA@ 0.22U_0402_16V7K PEG_HTX_GRX_P0 C22 PETN5_L0
PETP5_L0
USB2N1
USB2P1
AT7 USB20_P1
USB20_N1 <37>
USB20_P1 <37>
USB2 Port 1 (USB3.0 P2)
PEG_HRX_C_GTX_N1 C80 1 2 VGA@ 0.22U_0402_16V7K PEG_HRX_GTX_N1 F8 AR8 USB20_N2
PEG_HRX_C_GTX_P1 C81 1 2 VGA@ 0.22U_0402_16V7K PEG_HRX_GTX_P1 E8 PERN5_L1
PERP5_L1
USB2N2
USB2P2
AP8 USB20_P2 USB20_N2 <37>
USB20_P2 <37>
USB2 Port 2 ( USB/B)
PEG_HTX_C_GRX_N1 C82 1 2 VGA@ 0.22U_0402_16V7K PEG_HTX_GRX_N1 B23 AR10
PEG_HTX_C_GRX_P1 C83 1 2 VGA@ 0.22U_0402_16V7K PEG_HTX_GRX_P1 A23 PETN5_L1 USB2N3 AT10
VGA PETP5_L1 USB2P3
C PEG_HRX_C_GTX_N2 C84 1 2 VGA@ 0.22U_0402_16V7K PEG_HRX_GTX_N2 H10 AM15 USB20_N4 C
PEG_HRX_C_GTX_P2 C85 1 2 VGA@ 0.22U_0402_16V7K PEG_HRX_GTX_P2 G10 PERN5_L2
PERP5_L2
USB2N4
USB2P4
AL15 USB20_P4
USB20_N4 <34>
USB20_P4 <34>
Mini Card(WLAN+BT)
PEG_HTX_C_GRX_N2 C86 1 2 VGA@ 0.22U_0402_16V7K PEG_HTX_GRX_N2 B21 AM13 USB20_N5
PEG_HTX_C_GRX_P2 C87 1 2 VGA@ 0.22U_0402_16V7K PEG_HTX_GRX_P2 C21 PETN5_L2
PETP5_L2
USB2N5
USB2P5
AN13 USB20_P5 USB20_N5 <28>
USB20_P5 <28>
Touch Screen
PEG_HRX_C_GTX_N3 C88 1 2 VGA@ 0.22U_0402_16V7K PEG_HRX_GTX_N3 E6 AP11 USB20_N6
PEG_HRX_C_GTX_P3 C89 1 2 VGA@ 0.22U_0402_16V7K PEG_HRX_GTX_P3 F6 PERN5_L3
PERP5_L3
USB2N6
USB2P6
AN11 USB20_P6
USB20_N6 <28>
USB20_P6 <28>
Camera
PEG_HTX_C_GRX_N3 C90 1 2 VGA@ 0.22U_0402_16V7K PEG_HTX_GRX_N3 B22 AR13
PEG_HTX_C_GRX_P3 C91 1 2 VGA@ 0.22U_0402_16V7K PEG_HTX_GRX_P3 A21 PETN5_L3 USB2N7 AP13
PETP5_L3 USB2P7
PCIE_PRX_DTX_N3 G11
<32> PCIE_PRX_DTX_N3 PERN3
PCIE_PRX_DTX_P3 F11 G20
<32> PCIE_PRX_DTX_P3 PERP3 USB3RN1 PCH_USB3_RX1_N <37>
H20
PCIE LAN C155 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N3 C29 USB3.0 P1 USB3RP1 PCH_USB3_RX1_P <37>
<32> PCIE_PTX_C_DRX_N3
<32> PCIE_PTX_C_DRX_P3
C160 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P3 B30 PETN3
PETP3
PCIE USB
USB3TN1
C33
PCH_USB3_TX1_N <37>
USB3 Port 1 (MB side)
B34
F13 USB3TP1 PCH_USB3_TX1_P <37>
PCIE_PRX_DTX_N4
<34> PCIE_PRX_DTX_N4 PERN4
PCIE_PRX_DTX_P4 G13 E18
<34> PCIE_PRX_DTX_P4 PERP4 USB3RN2 PCH_USB3_RX2_N <37>
F18
WLAN C156 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N4 B29 USB3.0 P2 USB3RP2 PCH_USB3_RX2_P <37>
<34> PCIE_PTX_C_DRX_N4
<34> PCIE_PTX_C_DRX_P4
C157 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P4 A29 PETN4
PETP4 USB3TN2
B33
PCH_USB3_TX2_N <37>
USB3 Port 2 (MB side)
A33
G17 USB3TP2 PCH_USB3_TX2_P <37>
F17 PERN1/USB3RN3
PERP1/USB3RP3
C30 USB3.0 P3 / PCIE P1
C31 PETN1/USB3TN3 AJ10 USBRBIAS R154 1 2 22.6_0402_1%
PETP1/USB3TP3 USBRBIAS CAD note:
AJ11 Route single-end 50-ohms and max 450-mils length.
F15 USBRBIAS AN10 @ T35 Recommended minimum spacing to other signal traces is 15 mils
G15 PERN2/USB3RN4 RSVD AM10 @ T36
B PERP2/USB3RP4 USB3.0 P4 / PCIE P2 RSVD B
B31
A31 PETN2/USB3TN4
PETP2/USB3TP4 AL3 USB_OC0#
OC0/GPIO40 AT1 USB_OC1# USB_OC0# <11,37>
+1.05VS_AUSB3PLL OC1/GPIO41 AH2 PCH_GPIO42 USB_OC1# <11,37>
OC2/GPIO42 PCH_GPIO42 <11>
T33 @ E15 AV3 PCH_GPIO43
RSVD OC3/GPIO43 PCH_GPIO43 <11>
T34 @ E13
1 2 3.01K_0402_1% PCIE_RCOMP A27 RSVD
R232
1 2 0_0603_5% PCIE_IREF B27 PCIE_RCOMP
R155 @
PCIE_IREF
Trace width=12~15 mil, Spcing=12 mils
Max trace length= 500 mil 11 OF 19
@
A A

BDW MCP(7/11) PCIE,USB

5 4 3 2 1
5 4 3 2 1
+1.05VS_VTT
Place the CPU
resistors close to CPU
SVID ALERT
1
R171
75_0402_1%
R172
43_0402_1% +CPU_CORE
2
D 2 1 H_CPU_SVIDALRT# U1L BDW_ULT_DDR3L(Interleaved) D
<49> VR_ALERT#
T37 @ L59 C36
+1.05VS_VTT +1.35V +1.35V_CPU +1.35V_CPU T38 @ J58 RSVD VCC C40
RSVD VCC C44
Place the CPU
SVID DATA resistors close to CPU @ J6 AH26
VDDQ
VCC
VCC
C48
1
1 2 AJ31 C52
AJ33 VDDQ VCC C56
R173
AJ37 VDDQ VCC E23
130_0402_1% JUMP_43X118
AN33 VDDQ VCC E25
R174
0_0402_5% AP43 VDDQ VCC E27
Shark Bay ULT have internal gate for VDDQ VDDQ VCC
2
2 @ 1 VIDSOUT AR48 E29
<49> VR_SVID_DATA AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
AY44 VDDQ VCC E35
AY50 VDDQ VCC E37
+CPU_CORE
VDDQ VCC E39
F59 VCC E41
N58 VCC VCC E43
T39 @
T40 @ AC58 RSVD VCC E45
+1.05VS_VTT +1.05VS_VTT +VCCIO_OUT RSVD VCC E47
@ R164 VCC_SENSE_R E63 VCC E49
0_0603_5% T41 @ AB23 VCC_SENSE VCC E51
RSVD VCC
2
2 1 A59 E53
E20 VCCIO_OUT VCC E55
R169 +VCCIOA_OUT
150_0402_1% T42 @ AD23 VCCIOA_OUT VCC E57
@ T43 @ AA23 RSVD VCC F24
T44 @ AE59 RSVD VCC F28
RSVD VCC
1
CPU_PWR_DEBUG F32
H_CPU_SVIDALRT# L62 VCC F36
VIDALERT VCC
2
0_0402_5% 1 @ 2 R165 H_CPU_SVIDCLK N63 HSW ULT POWER F40

<49> VR_SVID_CLK VIDSOUT L63 VIDSCLK VCC F44
R170
C VCCST_PG_EC_R B59 VIDSOUT VCC F48 C
10K_0402_5% VCCST_PWRGD VCC
0_0402_5% 1 @ 2 R167 PCH_VR_EN F60 F52
@ <49> VR_ON VR_EN VCC
0_0402_5% 1 @ 2 R168 VR_READY C59 F56
<49> VGATE VR_READY VCC
1
G23
1 2 C167 D63 VCC G25
Reserved Only @ CPU_PWR_DEBUG H59 VSS VCC G27
P62 PWR_DEBUG VCC G29
.1U_0402_16V7K
T45 @ P60 VSS VCC G31
P61 RSVD_TP VCC G33
T46 @
N59 RSVD_TP VCC G35
T47 @
N61 RSVD_TP VCC G37
T48 @
+CPU_CORE T98 @ T59 RSVD_TP VCC G39
T142 @ AD60 RSVD VCC G41
RSVD VCC
1
T143 @ AD59 G43

AA59 RSVD VCC G45
R177 T144 @
AE60 RSVD VCC G47
100_0402_1% Note: 0 ohm PLACED CLOSE TO CPU T141 @
T140 @ AC59 RSVD VCC G49
AG58 RSVD VCC G51
T147 @
RSVD VCC
2
VCC_SENSE_R 2 @ 1 R178 +1.05VS_VTT T145 @ U59 G53

VCC_SENSE <49> V59 RSVD VCC G55
0_0402_5% T146 @
RSVD VCC G57
2 @ 1 R235 AC22 VCC H23
<15> VSS_SENSE_R VSS_SENSE <49> VCCST VCC
0_0402_5% +CPU_CORE AE22 J23
VCCST VCC
1
AE23 K23
VCCST VCC K57
R233
AB57 VCC L22
100_0402_1% VCC VCC
AD57 M23
AG57 VCC VCC M57
VCC VCC
2
C24 P57
C28 VCC VCC U57
C32 VCC VCC W57
VCC VCC
B 12 OF 19 B
Intel DG request @
@
C163 1 2 .1U_0402_16V7K VCCST_PG_EC_R
+1.05VS_VTT +1.35V_CPU
VDDQ DECOUPLING
@ EMI@ EMI@
22U_0603_6.3V6M
1U_0402_6.3V6K
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C6
C7
1 1 1 1 1 1 1 @ 1 1 1 @ 1 1 @
+
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
@ @ C18
+3VS 330U_D2_2V_Y
+1.05VS_VTT
2 2 2 2 2 2 2 2 2 2 2 2 2
SGA00009S00
1
+3VALW_PCH
330U 2V H1.9
1
R422
100K_0402_5% U16 R309 9mohm POLY
@ 1 5 10K_0402_5%
NC VCC
R166
2
2 0_0402_5%
<10,38> VCCST_PG_EC A
2
4 VCCST_PG_EC_R 1 @ 2
3 Y VCCST_PWRGD <38,47>
GND +1.35V : 470UF/2V/7343 *2
74AUP1G07GW_TSSOP5
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4
A A

BDW MCP(8/11) Power

5 4 3 2 1
5 4 3 2 1
D D
+1.05VS_VTT
+1.05VS_VTT U1M BDW_ULT_DDR3L(Interleaved)

+RTCVCC
K9 +3VALW_PCH
1 SF000006R00 L10 VCCHSIO
1U_0402_6.3V6K
+ 220U 6.3V OSCON M9 VCCHSIO C30 1 2 1U_0402_6.3V6K
1U_0402_6.3V6K
C408
VCCHSIO
ESR 17mohm@100Khz N8
VCC1_05
HSIO RTC
VCCSUS3_3
AH11
P9 AG10
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
220U_6.3V_M 1 1 +RTCVCC 1 1 1
2 B18 VCC1_05 VCCRTC AE7 +VCCRTCEXT 1 2
+1.05VS_AUSB3PLL VCCUSB3PLL DCPRTC
B11 .1U_0402_16V7K
C52
C51
C50
C21
C20
+1.05VS_ASATA3PLL C54
VCCSATA3PLL +3V_SPI
2 2 2 2 @ 2 @
Near PJ601 Y20 SPI Y8 2 1
RSVD VCCSPI
+1.05VS_APLLOPI
AA21 OPI C58 @ .1U_0402_16V7K
W21 VCCAPLL
Near K9 Near L10 VCCAPLL AG14
VCCASW +1.05VS_VTT
AG13
+3VALW_PCH VCCASW
+1.05VS_VTT
T105 @ J13 USB3 @
DCPSUS3 J11 1 2 10U_0603_6.3V6M
HDA --> 3.3V or 1.5V C27 C2567 0.47U_0402_6.3V6K
+1.05VS_VTT +1.05VS_AUSB3PLL VCC1_05 H11 C33 1 2 1U_0402_6.3V6K 1 2
VCC1_05 +3VALW_PCH
C Near B18 2 1 C38 AH14 HDA H15 C
1 2 1U_0402_6.3V6K VCCHDA VCC1_05 AE8
C42 1U_0402_6.3V6K
L1 1 2 C32 1 2 100U_1206_6.3V6M VCC1_05 AF22 1U_0402_6.3V6K
2.2UH_LQM2MPN2R2NG0L_30% T116 @ AH13 VRM VCC1_05 AG19 +PCH_VCCDSW 1 @ 2 +PCH_VCCDSW_R C41 1 2
Idc 1.2A Rdc 0.11ohm +/-30% DCPSUS2 CORE DCPSUSBYP AG20 R209 0_0402_5%
+3VALW_PCH DCPSUSBYP AE9
+1.05VS_ASATA3PLL VCCASW +1.05VS_VTT
AF9 C36 1 2 22U_0603_6.3V6M
2 1 22U_0603_6.3V6M AC9 VCCASW AG8 C37 1 2 1U_0402_6.3V6K
Near AC9 C28 Br oadwell only
AA9 VCCSUS3_3 VCCASW AD10 2 1U_0402_6.3V6K
Near B11 GPIO/LPC C43 @1 Intel recommends a 0.47uF boot strap
1 2 1U_0402_6.3V6K 2 1 .1U_0402_16V7K AH10 VCCSUS3_3 DCPSUS1 AD8
C46 Near AH10 @ C59 capacitor to be placed between V3.3DSW
1 2 1 2 100U_1206_6.3V6M V8 VCCDSW3_3 DCPSUS1
L2 C61 and DcpSUSByp power r ail
2.2UH_LQM2MPN2R2NG0L_30% 2 1 22U_0603_6.3V6M W9 VCC3_3
Near V8 C29
Idc 1.2A Rdc 0.11ohm +/-30% VCC3_3 J15 to support in-rush current.
+3VS VCCTS1_5 +1.5VS
THERMAL SENSOR K14
+1.05VS_APLLOPI VCC3_3 +3VS
K16 C55 1 2 .1U_0402_16V7K
VCC3_3
Near AA21
C47 1 2 1U_0402_6.3V6K J18
+1.05VS_AXCK_DCB VCCCLK
L3 1 2 C22 1 2 100U_1206_6.3V6M K19 SERIAL IO U8
VCCCLK VCCSDIO +3VS
2.2UH_LQM2MPN2R2NG0L_30% A20 T9 C44 1 2 1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL VCCACLKPLL VCCSDIO
Idc 1.2A Rdc 0.11ohm +/-30% J17
+1.05VS_VTT VCCCLK
C57 R21
2 1 1U_0402_6.3V6K T21 VCCCLK LPT LP POWER 2 1U_0402_6.3V6K
Near J17 C53 @1
VCCCLK
C56 T100 @ K18 SUS OSCILLATOR AB8 C25 @1 2 100U_1206_6.3V6M
+1.05VS_VTT +1.05VS_AXCK_DCB 2 1 1U_0402_6.3V6K T101 RSVD DCPSUS4
Near R21 @ M20
RSVD
T102 @ V21
AE20 RSVD AC20
Near J18 +3VALW_PCH @ T103
C48 1 2 1U_0402_6.3V6K AE21 VCCSUS3_3 RSVD AG16
VCCSUS3_3 VCC1_05 +1.05VS_VTT
L4 1 2 C23 1 2 100U_1206_6.3V6M USB2 AG17
2.2UH_LQM2MPN2R2NG0L_30% VCC1_05 C45 1 2 1U_0402_6.3V6K
Idc 1.2A Rdc 0.11ohm +/-30%
B +1.05VS_AXCK_LCPLL 13 OF 19 B
Near A20 BDW-ULT-DDR3L-IL_BGA1168
C49 1 2 1U_0402_6.3V6K @
L5 1 2 C24 1 2 100U_1206_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%
+3VALW TO +3VALW(PCH AUX Power)

Short J8 for PCH VCCSUS3.3
+3VALW J8 @ +3VALW_PCH
JUMP_43X39
1 2
1 2
A A

BDW MCP(9/11) Power

5 4 3 2 1
5 4 3 2 1
D D
U1N BDW_ULT_DDR3L(Interleaved) U1O BDW_ULT_DDR3L(Interleaved) U1P BDW_ULT_DDR3L(Interleaved)

H17
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
C AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63 C
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62
AH24 VSS VSS AN23 AU33 VSS VSS C11 VSS VSS_SENSE AH16 VSS_SENSE_R <13>
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 VSS
AH30 VSS VSS AN32 AU53 VSS VSS C18 BDW-ULT-DDR3L-IL_BGA1168
AH32 VSS VSS AN35 AU55 VSS VSS C20 @
AH34 VSS VSS AN36 AU57 VSS VSS C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
B AH42 VSS VSS AN43 AV20 VSS VSS C57 B
AH44 VSS VSS AN45 AV24 VSS VSS D12
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ25 VSS VSS AP10 AV49 VSS VSS D29
VSS VSS VSS 15 OF 19 VSS
@
14 OF 19
@
A A

HSW MCP(10/11) GND

5 4 3 2 1
5 4 3 2 1
D D
U1Q BDW_ULT_DDR3L(Interleaved)
U1R BDW_ULT_DDR3L(Interleaved)
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 N23
@ T58 @ T64
T49 @ AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 RSVD R23 @ T65
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 @ T59 T51 @ RSVD T23 @ T66
DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 AT2 RSVD
DC_TEST_AY62_AW62 AY62 A61 DC_TEST_A61_B61 T52 @ RSVD U10 @ T67
DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 AU44 RSVD
T50 @ B2 A62 @ T60 T53 @ RSVD
DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV44
DC_TEST_A3_B3 B3 AV1 @ T61 T54 @ RSVD
DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 D15
DC_TEST_A61_B61 B61 AW1 @ T62 RSVD AL1 @ T68
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 RSVD AM11 @ T69
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3 RSVD AP7
T55 @ F22 @ T70
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61 RSVD AU10
T56 @ H22 RSVD @ T71
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62 T57 @ RSVD AU15 @ T72
J21 RSVD
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 @ T63 RSVD AW14 @ T73
RSVD
17 OF 19 DAISY_CHAIN_NCTF_AW63 RSVD AY14 @ T74
BDW-ULT-DDR3L-IL_BGA1168 RSVD
@
18 OF 19
@
C C
U1S BDW_ULT_DDR3L(Interleaved)
T104 @ CFG0 AC60 AV63 @ T75

T107 @ CFG1 AC62
AC63
CFG0
CFG1
RSVD_TP
RSVD_TP
AU63 @ T76 CFG Straps for Processor
T108 @ CFG2
T166 @ CFG3 AA63 CFG2 CFG3
T167 @ CFG4 AA60 CFG3 C63 @ T77
CFG4 RSVD_TP Physical Debug Enable (DFX Privacy)
1
T168 @ CFG5 Y62 C62 @ T78
CFG6 Y61 CFG5 RSVD_TP B43
T169 @ @ T79 R224
T170 @ CFG7 Y60 CFG6 RSVD 1K_0402_5%
CFG8 V62 CFG7 A51
1: DISABLED
T171 @ @ T80 @ CFG3
T172 @ CFG9 V61 CFG8 RSVD_TP B51 @ T81
CFG9 RSVD_TP 0: ENABLED; SET DFX ENABLED BIT
2
T182 @ CFG10 V60
T181 @ CFG11 U60 CFG10 L60 @ T82 IN DEBUG INTERFACE MSR
T180 @ CFG12 T63 CFG11 RSVD_TP
T179 @ CFG13 T62 CFG12 RESERVED N60 @ T83
CFG14 T61 CFG13 RSVD
T178 @
CFG15 T60 CFG14 W23
T177 @ @ T84
CFG15 RSVD Y22 @ T85
T176 @ CFG16 AA62 RSVD AY15 OPI_COMP
T175 @ CFG18 U63 CFG16 PROC_OPI_RCOMP
T174 @ CFG17 AA61 CFG18 AV62 @ T86
T173 @ CFG19 U62 CFG17 RSVD D58 @ T87 CFG4
CFG19 RSVD
Display Port Presence Strap
1
CFG_RCOMP V63 P22
B CFG_RCOMP VSS N21 B
R225
A5 VSS
T90 @ 1K_0402_5% 1 : Disabled; No Physical Display Port
RSVD P20 @ T88
T91 @ E1 RSVD R20 @ T89 attached to Embedded Display Port
RSVD RSVD
2
T92 @ D1
T93 @ J20 RSVD CFG4
T94 @ H18 RSVD 0 : Enabled; An external Display Port device is
TD_IREF B12 RSVD connected to the Embedded Display Port
TD_IREF
19 OF 19
@
2 1 CFG_RCOMP
R222 49.9_0402_1%
2 1 OPI_COMP
R223 49.9_0402_1%
2 1 TD_IREF
R226 8.2K_0402_5%
A A

BDW MCP(11/11) RSVD

5 4 3 2 1
A B C D E
+1.35V
Channel A +1.35V
JDIMM2
+1.35V
1
+V_DDR_REFA 1 2
DIMM_1 H:4mm STD R54 DDR_A_D0
3
5
VREF_DQ
VSS2
VSS1
DQ4
4
6
DDR_A_D4
DDR_A_D5
R293 DDR_A_D1 7 DQ0 DQ5 8
1.8K_0402_1%
DQ1 VSS3 DDR_A_DQS#[0..7] <7>
2_0402_1% 9 10 DDR_A_DQS#0
VSS4 DQS#0
2
1 2 11 12 DDR_A_DQS0
<7> SA_DIMM_VREFDQ DM0 DQS0 DDR_A_DQS[0..7] <7>
1 13 14
VSS5 VSS6
1
@ DDR_A_D2 15 16 DDR_A_D6
17 DQ2 DQ6 18 DDR_A_D[0..63] <7>
2.2U_0402_6.3V6M
.1U_0402_16V7K
C158 DDR_A_D3 DDR_A_D7
19 DQ3 DQ7 20
C105
C106
0.022U_0402_25V7K R185 1 1
1 2 21 VSS7 VSS8 22 DDR_A_MA[0..15] <7> +1.35V 1
1.8K_0402_1% @ DDR_A_D8 DDR_A_D12
DQ8 DQ12
1
DDR_A_D9 23 24 DDR_A_D13
DQ9 DQ13
2
25 26
R176 2 2 DDR_A_DQS#1 27 VSS9 VSS10 28 +5VALW +5VS
24.9_0402_1% DDR_A_DQS1 29 DQS#1 DM1 30 DIMM_DRAMRST#
DQS1 RESET# DIMM_DRAMRST# <6,18> 1
@ 31 32
VSS11 VSS12
2
DDR_A_D10 33 34 DDR_A_D14 @ C34
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15 .1U_0402_16V7K
37 DQ11 DQ15 38 2 +1.35V R187 1 2 SA_ODT0
VSS13 VSS14
2
DDR_A_D16 39 40 DDR_A_D20 66.5_0402_1%
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21 R186 R191
43 DQ17 DQ21 44 U45 100K_0402_5% 100K_0402_5%
DDR_A_DQS#2 45 VSS15 VSS16 46 1 5 @ R188 1 2 SA_ODT1
DDR_A_DQS2 47 DQS#2 DM2 48 NC VCC 66.5_0402_1%
DQS2 VSS17
1
D
1
49 50 DDR_A_D22 2
VSS18 DQ22 <6> DDR_PG_CTRL A
DDR_A_D18 51 52 DDR_A_D23 4 2
DDR_A_D19 53 DQ18 DQ23 54 3 Y G R189 1 2 SB_ODT0
Layout Note: DQ19 VSS19 GND SB_ODT0 <18>
Place near JDIMM1 All VREF traces should 55 56 DDR_A_D28 Q18 S 66.5_0402_1%
VSS20 DQ28
3
DDR_A_D24 57 58 DDR_A_D29 74AUP1G07GW_TSSOP5 LBSS138LT1G_SOT-23-3
+1.35V have 10 mil trace width DDR_A_D25 59 DQ24 DQ29 60
A5WAH PVT: ESD request add 61 DQ25 VSS21 62 DDR_A_DQS#3 +1.35V M_A_B_DIMM_ODT R190 1 2 SB_ODT1
63 VSS22 DQS#3 64 DDR_A_DQS3 SB_ODT1 <18>
66.5_0402_1%
65 DM3 DQS3 66
VSS23 VSS24
2
67 68
1U_0402_6.3V6K
C107
1U_0402_6.3V6K
C108
1U_0402_6.3V6K
C109 ESD@
1U_0402_6.3V6K
C110
DDR_A_D26 DDR_A_D30
G
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
1 1 1 1 DQ27 DQ31
@ 71 72 3 1
VSS25 VSS26 DDR_VTT_PG_CTRL <46>
D
2 2 2 2 @ Q2007
DDRA_CKE0_DIMMA 73 74 DDRA_CKE1_DIMMA MESS138W-G_SOT323-3
<7> DDRA_CKE0_DIMMA CKE0 CKE1 DDRA_CKE1_DIMMA <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
2 DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14 2
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
+1.35V 85 A12/BC# A11 86
Reserve for cost test.
DDR_A_MA9 DDR_A_MA7
87 A9 A7 88
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
10U_0603_6.3V6M
C111
10U_0603_6.3V6M
C112
10U_0603_6.3V6M
C113
10U_0603_6.3V6M
C114

1 1 1 1 A3 A2
DDR_A_MA1 97 98 DDR_A_MA0
99 A1 A0 100
@
SA_CLK_DDR0 101 VDD9 VDD10 102 SA_CLK_DDR1
2 2 2 2 <7> SA_CLK_DDR0 CK0 CK1 SA_CLK_DDR1 <7>
SA_CLK_DDR#0 103 104 SA_CLK_DDR#1
<7> SA_CLK_DDR#0 CK0# CK1# SA_CLK_DDR#1 <7>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <7> +1.35V
DDR_A_BS0 109 110 DDR_A_RAS#
<7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7>
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDRA_CS0_DIMMA#
<7> DDR_A_WE# WE# S0# DDRA_CS0_DIMMA# <7>
1
DDR_A_CAS# 115 116 SA_ODT0
<7> DDR_A_CAS# CAS# ODT0
117 118 R56
+1.35V DDR_A_MA13 119 VDD15 VDD16 120 SA_ODT1 1.8K_0402_1%
DDRA_CS1_DIMMA# 121 A13 ODT1 122
<7> DDRA_CS1_DIMMA# S1# NC2
123 124 R296
VDD17 VDD18
2
125 126 +VREF_CA 1 2
NCTEST VREF_CA SM_DIMM_VREFCA <7>
127 128
10U_0603_6.3V6M
C115
10U_0603_6.3V6M
C116
10U_0603_6.3V6M
C117
10U_0603_6.3V6M
C161
1 2_0402_1% 1
VSS27 VSS28
1
1 1 1 1 DDR_A_D32 129 130 DDR_A_D36 @
+ 131 DQ32 DQ36 132
2.2U_0402_6.3V6M
.1U_0402_16V7K
@ C118 DDR_A_D33 DDR_A_D37 C162
330U_D2_2V_Y 133 DQ33 DQ37 134 R295 0.022U_0402_25V7K
VSS29 VSS30 1 1 2
DDR_A_DQS#4 135 136
C119
C120
@ 1.8K_0402_1%
2 2 2 2 2 DQS#4 DM4
1
DDR_A_DQS4 137 138
DQS4 VSS31
2
139 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2 2 @ R294
3 DDR_A_D35 143 DQ34 DQ39 144 3
24.9_0402_1%
145 DQ35 VSS33 146 DDR_A_D44
VSS34 DQ44
2
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150 +VREF_CA <18>
SGA00009S00 151 DQ41 VSS35 152 DDR_A_DQS#5
330U 2V H1.9 153 VSS36 DQS#5 154 DDR_A_DQS5
DM5 DQS5
9mohm POLY 155
VSS37 VSS38
156
+0.675VS DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
165 DQ48 DQ52 166
C121
C122
C123
C124
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_D49 DDR_A_D53
167 DQ49 DQ53 168
1 1 1 1 VSS41 VSS42
@ @ DDR_A_DQS#6 169 170
DDR_A_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_A_D54
2 2 2 2 DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190
Layout Note: VSS49 VSS50
Place near JDIMM1.203,204 DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196
197 VSS51 VSS52 198
199 SA0 EVENT# 200 D_CK_SDATA
+3VS VDDSPD SDA D_CK_SDATA <9,18,40>
201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK <9,18,40>
203 204
+0.675VS VTT1 VTT2 +0.675VS
4 205 206 4
.1U_0402_16V7K
G1 G2
2
Channel A
1
C125
R211
R212
0_0402_5%
0_0402_5%
LCN_DAN06-K4406-0100
@ @ CONN@
2 SP07000N300
1
<Address: SA1:SA0=00>
DDRIII DIMMA

A B C D E
A B C D E
+1.35V
+1.35V +1.35V
Channel B JDIMM1
DDR_B_DQS#[0..7] <7>
1
+V_DDR_REFB 1 2
3 VREF_DQ VSS1 4 DDR_B_D22
DDR_B_D23 5 VSS2 DQ4 6 DDR_B_D16 DDR_B_DQS[0..7] <7>
R57
DIMM_2 H:4mm R297
2_0402_1%
1.8K_0402_1% DDR_B_D17 7
9
DQ0
DQ1
DQ5
VSS3
8
10 DDR_B_DQS#2
DDR_B_D[0..63] <7>
Reverse VSS4 DQS#0
2
1 2 11 12 DDR_B_DQS2
<7> SB_DIMM_VREFDQ DM0 DQS0 DDR_B_MA[0..15] <7>
1 13 14
VSS5 VSS6
1
DDR_B_D21 15 16 DDR_B_D19
2.2U_0402_6.3V6M
.1U_0402_16V7K
@ C159 R213 DDR_B_D18 17 DQ2 DQ6 18 DDR_B_D20
1 1 DQ3 DQ7
19 20
C127
C128
0.022U_0402_25V7K 1.8K_0402_1% @
2 DDR_B_D3 21 VSS7 VSS8 22 DDR_B_D4
DQ8 DQ12
1
1 DDR_B_D2 23 24 DDR_B_D5 1
DQ9 DQ13
2
2 2 25 26
DDR_B_DQS#0 27 VSS9 VSS10 28
@ R179
24.9_0402_1% DDR_B_DQS0 29 DQS#1 DM1 30 DIMM_DRAMRST#
DQS1 RESET# DIMM_DRAMRST# <6,17>
31 32
VSS11 VSS12
2
DDR_B_D0 33 34 DDR_B_D6
DDR_B_D1 35 DQ10 DQ14 36 DDR_B_D7
DQ11 DQ15 1
37 38
DDR_B_D12 39 VSS13 VSS14 40 DDR_B_D13 C2611 XESD@
DDR_B_D8 41 DQ16 DQ20 42 DDR_B_D9 .1U_0402_16V7K
43 DQ17 DQ21 44 2
DDR_B_DQS1 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D11
DDR_B_D14 51 VSS18 DQ22 52 DDR_B_D10
DDR_B_D15 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D30
Layout Note: All VREF traces should VSS20 DQ28
Place near JDIMM2 have 10 mil trace width DDR_B_D31 57 58 DDR_B_D26
DDR_B_D25 59 DQ24 DQ29 60
+1.35V 61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D27 67 VSS23 VSS24 68 DDR_B_D29
69 DQ26 DQ30 70
1U_0402_6.3V6K
C129
1U_0402_6.3V6K
C130
1U_0402_6.3V6K
C131
1U_0402_6.3V6K
C132
DDR_B_D24 DDR_B_D28
71 DQ27 DQ31 72
1 1 1 1 VSS25 VSS26
@ @
2 2 2 2 DDRB_CKE0_DIMMB 73 74 DDRB_CKE1_DIMMB
<7> DDRB_CKE0_DIMMB CKE0 CKE1 DDRB_CKE1_DIMMB <7>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<7> DDR_B_BS2 BA2 A14
2 81 82 2
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
+1.35V 87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
95 VDD7 VDD8 96
10U_0603_6.3V6M
C133
10U_0603_6.3V6M
C134
10U_0603_6.3V6M
C135
10U_0603_6.3V6M
C136
DDR_B_MA3 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
1 1 1 1 A1 A0
99 100
SB_CLK_DDR0 101 VDD9 VDD10 102 SB_CLK_DDR1
<7> SB_CLK_DDR0 CK0 CK1 SB_CLK_DDR1 <7>
SB_CLK_DDR#0 103 104 SB_CLK_DDR#1
2 2 2 2 <7> SB_CLK_DDR#0 CK0# CK1# SB_CLK_DDR#1 <7>
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7>
DDR_B_BS0 109 110 DDR_B_RAS#
<7> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <7>
111 112
DDR_B_WE# 113 VDD13 VDD14 114 DDRB_CS0_DIMMB#
<7> DDR_B_WE# WE# S0# DDRB_CS0_DIMMB# <7>
DDR_B_CAS# 115 116 SB_ODT0
<7> DDR_B_CAS# CAS# ODT0 SB_ODT0 <17>
117 118
DDR_B_MA13 119 VDD15 VDD16 120 SB_ODT1
+1.35V A13 ODT1 SB_ODT1 <17>
DDRB_CS1_DIMMB# 121 122
<7> DDRB_CS1_DIMMB# S1# NC2
123 124
125 VDD17 VDD18 126 +VREF_CA
NCTEST VREF_CA +VREF_CA <17>
127 128
10U_0603_6.3V6M
C137
10U_0603_6.3V6M
C138
10U_0603_6.3V6M
C139
DDR_B_D35 131 DQ32 DQ36 132 DDR_B_D34
2.2U_0402_6.3V6M
.1U_0402_16V7K
1 1 1 DQ33 DQ37
133 134 1 1
C141
C142
@
@ DDR_B_DQS4 137 DQS#4 DM4 138
2 2 2 139 DQS4 VSS31 140 DDR_B_D39
DDR_B_D36 141 VSS32 DQ38 142 DDR_B_D37 2 2
DDR_B_D38 143 DQ34 DQ39 144
3 145 DQ35 VSS33 146 DDR_B_D44 3
DDR_B_D45 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
155 DM5 DQS5 156
+0.675VS DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D46
161 DQ43 DQ47 162
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D55
167 DQ49 DQ53 168
C143
C144
C145
C146
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K

1 1 1 1 DQS#6 DM6
@ @ DDR_B_DQS6 171 172
173 DQS6 VSS43 174 DDR_B_D48
2 2 2 2 DDR_B_D53 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D56
+3VS DDR_B_D62 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_B_DQS#7
DM7 DQS7
2
189 190
Layout Note: R229
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D61
Place near JDIMM2.203,204 10K_0402_5%
195 DQ59 DQ63 196
197 VSS51 VSS52 198
SA0 EVENT#
1
199 200 D_CK_SDATA

+3VS VDDSPD SDA D_CK_SDATA <9,17,40>
201 202 D_CK_SCLK
203 SA1 SCL 204 D_CK_SCLK <9,17,40>
+0.675VS VTT1 VTT2 +0.675VS
205 206
.1U_0402_16V7K
G1 G2
2
4 4
Channel B
1
C147
R231
0_0402_5%
@ CONN@
LCN_DAN06-K4406-0101 <Address: SA1:SA0=10>
2
SP07000PT00
1

DDRIII DIMMB

A B C D E
A B C D E
UGPU1A
+3VSDGPU_AON
GPIO I/O USAGE
Part 1 of 6 RP2000
AG6 C6 GC6_FB_EN GC6_FB_EN <10> 10K_0804_8P4R_5%
<12> PEG_HTX_C_GRX_P0 AG7 PEX_RX0 GPIO0 B2 8 1
GPIO8_OVERT GPIO0 I GC6_FB_EN
<12> PEG_HTX_C_GRX_N0 AF7 PEX_RX0_N GPIO1 D6 GPIO9_ALERT 7 2
<12> PEG_HTX_C_GRX_P1 AE7 PEX_RX1 GPIO2 C7 6 3
<12> PEG_HTX_C_GRX_N1 AE9 PEX_RX1_N GPIO3 F9 ACIN_BUF 5 4
<12> PEG_HTX_C_GRX_P2 AF9 PEX_RX2 GPIO4 A3 3VSDGPU_MAIN_EN <41,52>
GPIO1 O MEM_VDD_CTL
3VSDGPU_MAIN_EN
<12> PEG_HTX_C_GRX_N2 PEX_RX2_N GPIO5
AG9 A4 GPU_EVENT#_R VGA@
<12> PEG_HTX_C_GRX_P3 PEX_RX3 GPIO6 +3VSDGPU_AON
AG10 B6 GPIO2 O LCD_BL_PW M
<12> PEG_HTX_C_GRX_N3 AF10 PEX_RX3_N GPIO7 A6 GPIO8_OVERT N14x for GPIO8 RP2001
AE10 NC OVERT F8 GPIO9_ALERT 10K_0804_8P4R_5%
NC GPIO9 N15x, N16x for O VERT
AE12 C5 GPU_EVENT#_R 8 1 GPIO3 O LCD_VCC
AF12 NC GPIO10 E7 DGPU_VID 3VSDGPU_MAIN_EN 7 2
1 AG12 NC GPIO11 D7 ACIN_BUF DGPU_VID <52> GPU_PEX_RST_HOLD# 6 3 1
AG13 NC GPIO12 B4 PSI GC6_FB_EN 5 4 GPIO4 O LCD_BL_EN
GPIO
AF13 NC GPIO13 B3 PSI <52>
AE13 NC GPIO14 C3 GC6@
AE15 NC GPIO15 D5 ACIN_BUF 2 1
AF15 NC GPIO16 D4 DGPU_AC_DETECT <11,38> +3VSDGPU_AON
GPIO5 O 3V3_MAIN_EN
D2000
AG15 NC GPIO17 C2 RB751V-40_SOD323-2 @ R2056
AG16 NC GPIO18 F7 SYS_PEX_RST_MON# 2 1 10K_0402_5%
VGA@ GPIO6 I GPU_EVENT#
AF16 NC GPIO19 E6
AE16 NC GPIO20 C4 GPU_PEX_RST_HOLD# VGA@ R2000
AE18 NC GPIO21 GPU_EVENT#_R2 1 I2CS_SDA 1 2 1.8K_0402_5%
AF18 NC AB6 GPU_EVENT# <11> GPIO7 O 3D Vision
D2011
AG18 NC PEX_WAKE_NC RB751V-40_SOD323-2 VGA@ R2001
AG19 NC GC6@ I2CS_SCL 1 2 1.8K_0402_5%
AF19 NC GPIO8 I SYS_PEX_RST_MON#
AE19 NC
VGA@ R2052
AE21 NC AG3 PSI 2 1 10K_0402_5%
AF21 NC NC AF4
GPIO9 I/O ALERT
AG21 NC NC AF3 +1.05VS_VTT
AG22 NC NC
NC GPIO10 O MEM_VREF_CTL
U17
1 5 PLTRST_VGA#
AC9 AE3 NC VCC
<12> PEG_HRX_C_GTX_P0 PEX_TX0 NC
DACs
AB9 AE4 2 Q2000A VGA@ GPIO11 O
<12> PEG_HRX_C_GTX_N0
AB10 PEX_TX0_N NC <6,38> H_PROCHOT# A 4 ACIN_BUF
PW M_VID
<12> PEG_HRX_C_GTX_P1 L2N7002DW1T1G_SC88-6
PEX_TX1 Y
2
AC10 3
<12> PEG_HRX_C_GTX_N1 PEX_TX1_N GND
AD11
PCI EXPRESS
<12> PEG_HRX_C_GTX_P2 PEX_TX2
AC11 W5 74AUP1G07GW_TSSOP5 GPIO12 I PWR_LEVEL
<12> PEG_HRX_C_GTX_N2 PEX_TX2_N NC
AC12 AE2 @ GPIO8_OVERT 1 6
<12> PEG_HRX_C_GTX_P3 PEX_TX3 TSEN_VREF GPU_OVERT <38>
AB12 AF2
<12> PEG_HRX_C_GTX_N3 PEX_TX3_N NC
AB13
AC13 NC GPIO13 O PSI
2 AD14 NC 2
AC14 NC PLTRST_VGA#
AC15 NC GPIO14 I HPD_A
Q2000B VGA@
AB15 NC L2N7002DW1T1G_SC88-6
NC
5
AB16 B7 R2003 1 VGA@ 2 1.8K_0402_5%
AC16 NC I2CA_SCL A7 1 VGA@ 2 1.8K_0402_5%
GPIO15 I HPD_C
R2004
AD17 NC I2CA_SDA
AC17 NC C9 R2005 1 VGA@ 2 1.8K_0402_5% GPIO9_ALERT 4 3
NC I2CB_SCL GPU_ALERT <38> GPIO16 RESER VED
AC18 C8 R2006 1 VGA@ 2 1.8K_0402_5%
NC I2CB_SDA
I2C
AB18
AB19 NC A9 1 VGA@ 2 1.8K_0402_5%
R2007 GPIO17 I HPD_D
AC19 NC I2CC_SCL B9 R2008 1 VGA@ 2 1.8K_0402_5%
AD20 NC I2CC_SDA
AC20 NC D9 I2CS_SCL PLTRST_VGA#
AC21 NC I2CS_SCL D8 I2CS_SDA
GPIO18 I HPD_E
AB21 NC I2CS_SDA
Q2001A VGA@
NC
2
AD23 Place Under L6 L2N7002DW1T1G_SC88-6 GPIO19 I HPD_F or HPD_B
AE23 NC
AF24 NC
AE24 NC L6 +PLLVDD 1 2 VGA@ I2CS_SCL 1 6
AG24 NC PLLVDD M6 .1U_0402_16V7K EC_SMB_CK2 <9,30,38> GPIO20 Reserved
C2000
AG25 NC SP_PLLVDD
NC N6
NC GPIO21 O GPU_PEX_RST_HOLD#
R2009 VGA@ +GPU_PLLVDD 1 2 VGA@
10K_0402_5% C2001 .1U_0402_16V7K
1 2 AE8 GPIO22
+3VSDGPU_AON <9> CLK_PEG_VGA PEX_REFCLK
AD8
<9> CLK_PEG_VGA# AC6 PEX_REFCLK_N
PEG_CLKREQ# Place Under M6 PLTRST_VGA#
<9> PEG_CLKREQ# PEX_CLKREQ_N Q2001B VGA@ GPIO23
PEX_TSTCLK_OUT+ AF22 L2N7002DW1T1G_SC88-6
CLK
PEX_TSTCLK_OUT
5
2 @ 1 PEX_TSTCLK_OUT- AE22 C11 XTALIN
R2010 200_0402_1% PEX_TSTCLK_OUT_N XTAL_IN B10 XTALOUT
3 XTAL_OUT GPIO24 3
PLTRST_VGA# AC7 A10 XTAL_SSIN R2012 1 VGA@ 2 10K_0402_5% I2CS_SDA 4 3
2 VGA@ 1 PEX_TREMP AF25 PEX_RST_N XTAL_SSIN C10 XTAL_OUTBUFF R2013 1 VGA@ 2 EC_SMB_DA2 <9,30,38>
10K_0402_5%
R2011 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF
GM108-ES-S-A1_FCBGA595
@
SM01000I200 3000ma 33ohm@100mhz DCR 0.05

D2001 38mA, 16mils
GC6_FB_EN 2 +1.05VSDGPU
1 1.5VS_DGPU_PWR_EN VGA@
GC6 2.0 function 3
1.5VS_DGPU_PWR_EN <41,51>
+PLLVDD 1 2
L2000 CHILISIN PBY160808T-330Y-N
1
BAV70W_SOT323-3 GC6@ 1
GC6@ R2014 PLL_VDD C2003
200K_0402_5% 0.1Ux1, 22Ux1 VGA@
R2016 33ohm(ESR0.05)x1 22U_0603_6.3V6M
1 NGC6@ 2 2 27MHZ_10PF_7V27000023
<9,41,52> VGA_PWROK
2
Near GPU
0_0402_5% XTALOUT 3 1 XTALIN
3 1
SM01000AG00 2A 300ohm@100mhz DCR 0.1 GND GND
+3VSDGPU_AON
10P_0402_50V8J
10P_0402_50V8J
17mA, 16mils 1 1
VGA@ VGA@ X2000 VGA@
4 2
5
U2001 VGA@ VGA@

2 +GPU_PLLVDD 1 2 C2004 C2005
P
<10,38,39> PLT_RST# B 4 2 2
L2001 HCB1608KF-301T20_2P
1 Y SYS_PEX_RST_MON# <21>
<10> DGPU_HOLD_RST# A SP_PLLVDD+VID_PLLVDD 1
G
0.1Ux2, 4.7Ux1,22Ux1 C2006 C2007

+3VSDGPU_AON R2019 R2017 VGA@ VGA@ Crystals must have a max ESR of 80 ohm
180ohm(ESR0.2)x1
3
MC74VHC1G08DFT2G_SC70-5 0_0402_5% 10K_0402_5% 10U_0603_6.3V6M 47U_0805_6.3V6M

2
4 NGC6@ VGA@ +3VSDGPU_AON 2 4

1
Near GPU DVT modify 11/27

1
R2055 TXC recommend from 18P change to 10P

5
D2002 U2002 GC6@ X2000 from SJ100009700 change to SJ10000G300

10K_0402_5%
SYS_PEX_RST_MON# 2 SYS_PEX_RST_MON# 2
@
P
B 4 PLTRST_VGA#
Y
2
1 PLTRST_VGA# GPU_PEX_RST_HOLD# 1
A
G
GC6@
GPU_PEX_RST_HOLD# 3 DVT modify 11/20 MC74VHC1G08DFT2G_SC70-5 R2628
3
use diode need to pull high 10K_0402_5% 2013/10/01 2014/05/24 Title

use AND gate need to pull down Issued Date Deciphered Date
BAT54A-7-F_SOT23-3
@
N16X PEG & GPIO 1/9
2
By NV request. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom

A B C D E
A B C D E
VRAM Interface +1.5VSDGPU

+1.5VSDGPU
UGPU1
RP33 2
CMDA23 1 8
A5MUB exchange 2 7 C2083 @
CMDA21 3 6 .1U_0402_16V7K
4 5 1
N16S-GT UGPU1B
SGT@ 100_0804_8P4R_5%
1
SA000087F10 +1.5VSDGPU 1
VGA@
RP42
Part 2 of 6 CMDA24 1 8
R3 P/N: MDA[15..0] CMDA[31..0] <24,25,26,27> A5MUB exchange 2 7
2
<24,25> MDA[15..0] E18 C27 3 6
MDA0 CMDA0 CMDA26 C2084 @
UGPU1 MDA[31..16] MDA1 F18 FBA_D00 FBA_CMD0 C26 CMDA1 4 5 .1U_0402_16V7K
<24,25> MDA[31..16] MDA2 E16 FBA_D01 FBA_CMD1 E24 CMDA2 1
MDA[47..32] MDA3 F17 FBA_D02 FBA_CMD2 F24 CMDA3 100_0804_8P4R_5%
<26,27> MDA[47..32] D20 FBA_D03 FBA_CMD3 D27
MDA4 CMDA4 VGA@
MDA[63..48] MDA5 D21 FBA_D04 FBA_CMD4 D26 CMDA5 +1.5VSDGPU
RP43
<26,27> MDA[63..48] F20 FBA_D05 FBA_CMD5 F25 1 8
MDA6 CMDA6 CMDA10
N16V-GM MDA7 E21 FBA_D06 FBA_CMD6 F26 CMDA7 A5MUB exchange 2 7
FBA_D07 FBA_CMD7 2
VGM@ MDA8 E15 F23 CMDA8 CMDA22 3 6
MDA9 D15 FBA_D08 FBA_CMD8 G22 CMDA9 4 5 C2085 @
SA000088R20 FBA_D09 FBA_CMD9
MDA10 F15 G23 CMDA10 .1U_0402_16V7K
MDA11 F13 FBA_D10 FBA_CMD10 G24 CMDA11 1
R3 P/N: 100_0804_8P4R_5%
MDA12 C13 FBA_D11 FBA_CMD11 F27 CMDA12
FBA_D12 FBA_CMD12 VGA@
MDA13 B13 G25 CMDA13 RP44
MDA14 E13 FBA_D13 FBA_CMD13 G27 CMDA14 CMDA4 1 8 +1.5VSDGPU
MDA15 D13 FBA_D14 FBA_CMD14 G26 CMDA15 A5MUB exchange 2 7
MDA16 B15 FBA_D15 FBA_CMD15 M24 CMDA16 CMDA12 3 6
FBA_D16 FBA_CMD16 2
MDA17 C16 M23 CMDA17 4 5
MDA18 A13 FBA_D17 FBA_CMD17 K24 CMDA18 C2086 @
MDA19 A15 FBA_D18 FBA_CMD18 K23 CMDA19 .1U_0402_16V7K
100_0804_8P4R_5%
MDA20 B18 FBA_D19 FBA_CMD19 M27 CMDA20 1
FBA_D20 FBA_CMD20 VGA@
MDA21 A18 M26 CMDA21 RP45
MDA22 A19 FBA_D21 FBA_CMD21 M25 CMDA22 CMDA8 1 8
MDA23 C19 FBA_D22 FBA_CMD22 K26 CMDA23 A5MUB exchange 2 7 +1.5VSDGPU
MDA24 B24 FBA_D23 FBA_CMD23 K22 CMDA24 CMDA14 3 6
MDA25 C23 FBA_D24 FBA_CMD24 J23 CMDA25 4 5
FBA_D25 FBA_CMD25 2
MDA26 A25 J25 CMDA26
MDA27 A24 FBA_D26 FBA_CMD26 J24 CMDA27 100_0804_8P4R_5% C2087 @
2 MDA28 A21 FBA_D27 FBA_CMD27 K27 CMDA28 PVT modify 01/13 .1U_0402_16V7K 2
FBA_D28 FBA_CMD28 VGA@ 1
MDA29 B21 K25 CMDA29 DQSA, DQSA# reverse RP46
MDA30 C20 FBA_D29 FBA_CMD29 J27 CMDA30 CMDA9 1 8
MDA31 C21 FBA_D30 FBA_CMD30 J26 CMDA31 2 7
MDA32 R22 FBA_D31 FBA_CMD31 A5MUB exchange CMDA29 3 6 +1.5VSDGPU
MDA33 R24 FBA_D32 D19 DQMA0 DQMA[3..0] <24,25> 4 5
FBA_D33 FBA_DQM0
INTERFACE A
MDA34 T22 D14 DQMA1 2
MDA35 R23 FBA_D34 FBA_DQM1 C17 DQMA2 100_0804_8P4R_5%
MDA36 N25 FBA_D35 FBA_DQM2 C22 DQMA3 VGA@ C2088 @
MDA37 N26 FBA_D36 FBA_DQM3 P24 DQMA4 DQMA[7..4] <26,27> .1U_0402_16V7K
RP47
MEMORY
MDA38 N23 FBA_D37 FBA_DQM4 W24 DQMA5 CMDA5 1 8 1
MDA39 N24 FBA_D38 FBA_DQM5 AA25 DQMA6 A5MUB exchange 2 7
MDA40 V23 FBA_D39 FBA_DQM6 U25 DQMA7 CMDA13 3 6
NV 15x DG-06803-V03 MDA41
MDA42
V22
T23
FBA_D40
FBA_D41
FBA_DQM7
F19 DQSA#0 DQSA#[3..0] <24,25>
4 5
NV 16x DG-07158-V04 MDA43

MDA44
U22
Y24
FBA_D42
FBA_D43
FBA_DQS_RN0
FBA_DQS_RN1
C14
A16
DQSA#1
DQSA#2
100_0804_8P4R_5% +1.5VSDGPU
FBA_D44 FBA_DQS_RN2 VGA@

MDA45 AA24 A22 DQSA#3 RP48 2
Y22 FBA_D45 FBA_DQS_RN3 P25 DQSA#[7..4] <26,27> 1 8
MDA46 DQSA#4 CMDA6
MDA47 AA23 FBA_D46 FBA_DQS_RN4 W22 DQSA#5 A5MUB exchange 2 7 C2090 @
MDA48 AD27 FBA_D47 FBA_DQS_RN5 AB27 DQSA#6 CMDA7 3 6 .1U_0402_16V7K
MDA49 AB25 FBA_D48 FBA_DQS_RN6 T27 DQSA#7 4 5 1
MDA50 AD26 FBA_D49 FBA_DQS_RN7
FBA_D50 DQSA[3..0] <24,25>
MDA51 AC25 E19 DQSA0 100_0804_8P4R_5%
MDA52 AA27 FBA_D51 FBA_DQS_WP0 C15 DQSA1 +1.5VSDGPU
FBA_D52 FBA_DQS_WP1 VGA@
MDA53 AA26 B16 DQSA2 RP49
MDA54 W26 FBA_D53 FBA_DQS_WP2 B22 DQSA3 CMDA27 1 8
FBA_D54 FBA_DQS_WP3 DQSA[7..4] <26,27> 2
SM01000I200 3000ma 33ohm@100mhz DCR 0.05 MDA55 Y25 R25 DQSA4 2 7
MDA56 R26 FBA_D55 FBA_DQS_WP4 W23 DQSA5 CMDA30 3 6 C2091 @
MDA57 T25 FBA_D56 FBA_DQS_WP5 AB26 DQSA6 4 5 .1U_0402_16V7K
MDA58 N27 FBA_D57 FBA_DQS_WP6 T26 DQSA7 1
+1.05VSDGPU MDA59 R27 FBA_D58 FBA_DQS_WP7 100_0804_8P4R_5%
3 MDA60 V26 FBA_D59 3
15+55mA V27 FBA_D60 VGA@
+1.5VSDGPU
VGA@ MDA61 RP50
2 1 L2002 +FB_PLLAVDD MDA62 W27 FBA_D61 CMDA28 1 8
CHILISIN PBY160808T-330Y-N MDA63 W25 FBA_D62 A5MUB exchange 2 7
FBA_D63 2
D24 CMDA25 3 6
F16 FBA_CLK0 D25 CLKA0 <24,25> 4 5
C2008 VGA@
C2011
C2010 VGA@
C2009 VGA@
22U_0603_6.3V6M
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1 2 2 2 C2093 @
FB_PLLAVDD_1 FBA_CLK0_N CLKA0# <24,25> .1U_0402_16V7K
P22
FB_PLLAVDD_2 N22 1
100_0804_8P4R_5%
FBA_CLK1 CLKA1 <26,27>
T97 @ D23 M22 VGA@
2 1 1 1 FB_VREF_PROBE FBA_CLK1_N CLKA1# <26,27>
VGA@
RP51
D18 CMDA15 1 8 +1.5VSDGPU
H22 FBA_WCK01 C18 A5MUB exchange 2 7
FB_DLLAVDD FBA_WCK01_N D17 CMDA11 3 6
Place Near GPU Place Under F16 P22 H22 1 VGA@ 2 FB_CLAMP F3 FBA_WCK23 D16 4 5
2
10K_0402_5% R2028 FB_CLAMP FBA_WCK23_N T24 C2089 @
FBA_WCK45 U24 .1U_0402_16V7K
100_0804_8P4R_5%
1 2 F22 FBA_WCK45_N V24 1
60.4_0402_1% @ R2020FBA_CMD34 VGA@
60.4_0402_1% 1 @ 2 R2022FBA_CMD35 J22 FBA_CMD34 FBA_WCK67 V25
+1.5VSDGPU FBA_CMD35 FBA_WCK67_N
+1.5VSDGPU
2
@ C2092 @
.1U_0402_16V7K
1
4 4

N16X VRAM 2/9

A B C D E
A B C D E
UGPU1C
Part 3 of 6
NC
F11 MULTI LEVEL STRAPS
AC3 AD10
AC4 NC NC AD7
Y4 NC NC B19 +3VSDGPU_AON +3VSDGPU_MAIN
Y3 NC FBA_CMD32 V5
AA3 NC NC V6 strap0 strap1 strap2 strap3 strap4
AA2 NC NC G1
NC NC
1
AB1 G2
NC NC
NC
1 AA1 G3 R2029 R2030 R2031 R2032 R2033 R2035 R2036 R2037 1
AA4 NC NC G4 SGT@ @ VGM@ @ @ @ VGM@ VGM@
AA5 NC NC G5 49.9K_0402_1% 4.99K_0402_1% 10K_0402_1% 4.99K_0402_1% 10K_0402_1% 30K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
NC NC G6
NC
2
G7
AB5 NC V1
AB4 NC NC V2 STRAP0
AB3 NC NC W1 STRAP1 ROM_SI
AB2 NC NC W2 STRAP2 ROM_SO
AD3 NC NC W3 STRAP3 ROM_SCLK
AD2 NC NC W4 STRAP4
AE1 NC NC
NC For GC62.0 use
AD1 @ R2050 N14x for CEC ,NC
NC
1
AD4 10K_0402_5%
NC N15x, N16x for GPIO8
AD5 D11 1 2 R2038 R2039 R2040 R2041 R2042 R2044 R2045 R2046
NC BUFRST_N
@ VGM@ @ VGM@ VGM@ X76@ SGT@ SGT@
D10 4.99K_0402_1% 45.3K_0402_1% 15K_0402_1% 4.99K_0402_1% 45.3K_0402_1% 10K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
T2 NC
NC
2
T3 E9 SYS_PEX_RST_MON#
T1 NC GPIO8 SYS_PEX_RST_MON# <19>
R1 NC E10
R2 NC NC
GENERAL
NC
LVDS/TMDS
R3 F10
N2 NC NC
N3 NC
NC D1 STRAP0
STRAP0 D2 STRAP1
V3 STRAP1 E4 STRAP2
NC STRAP2
N16V -GM Option Component
V4 E3 STRAP3
U3 NC STRAP3 D3 STRAP4
U4 NC STRAP4 C1 STRAP0 ---> R2029 2 VGM@1 45.3K_0402_1% SD034453280
T4 NC NC VGA@ R2051
2 T5 NC 2
40.2K_0402_1%
R4 NC F6 MULTI_STRAP_REF0_GND 1 2
R5 NC MULTI_STRAP_REF0_GND F4
NC NC F5
NC
N1
M1 NC
M2 NC F12
M3 NC THERMDP
K2 NC E12
For N16S-GT Binary strap table Decive ID : 0x1347
K3 NC THERMDN
GPU VRAM RANK X76 Freq Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
K1 NC Voltage
J1 NC
NC X76614BOL05 0x0 (SA00006E840) Hynix H5TC4G63AFR-11C PD 4.99K
1GHz 256Mx16x8
M4 F2 VCCSENSE_VGA +1.5V Dual
X76614BOL04 4G 0x1 (SA000077K20) Micron MT41J256M16HA-093G:E PD 10K
M5 NC VDD_SENSE VCCSENSE_VGA <52>
L3 NC X76614BOL06 0x2 (SA000076P20) Samsung K4W4G1646D-BC1A PD 15K
L4 NC
NC N16S-GT X76614BOL14
K4 0xC (SA00008DN10) Hynix H5TC4G63CFR-N0C PU 49.9K NC NC NC NC PU 24.9K PD 4.99K PD 4.99K
NC
K5 X76614BOL11 0x0 (SA00006E840) Hynix H5TC4G63AFR-11C PD 4.99K
J4 NC F1 VSSSENSE_VGA 1GHz 256Mx16x4
NC GND_SENSE VSSSENSE_VGA <52>
+1.5V Single
X76614BOL10 2G 0x1 (SA000077K20) Micron MT41J256M16HA-093G:E PD 10K
X76614BOL12 0x2 (SA000076P20) Samsung K4W4G1646D-BC1A PD 15K
J5
N4 NC X76614BOL16 0x5 (SA00008DN10) Hynix H5TC4G63CFR-N0C PD 30.1K
N5 NC TEST VGA@ R2054
NC 10K_0402_5%
P3 AD9 TESTMODE 1 2
P4 NC TESTMODE AE5 JTAG_TCK PAD @ T18
3 NC JTAG_TCK AE6 JTAG_TDI 3
PAD @ T1
JTAG_TDI AF6 JTAG_TDO PAD @ T186
J2 JTAG_TDO AD6 JTAG_TMS
J3 NC JTAG_TMS AG4 JTAG_RST 1
PAD @
2
T3
For N16V-GM Binary strap table Decive ID : 0x1299
NC JTAG_TRST_N GPU VRAM RANK X76 Freq Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
VGA@ R2053 Voltage
H3 10K_0402_5%
H4 NC X76614BOL08 0xE (SA00006E840) Hynix H5TC4G63AFR-11C PU 34.8K
NC SERIAL
D12 +1.35V Dual
X76614BOL07 900MHz 256Mx16x8 0xD (SA000077K20) Micron MT41J256M16HA-093G:E PU 30.1K
ROM_CS_N B12 ROM_SI 4G
ROM_SI A12 ROM_SO X76614BOL09 0xC (SA000076P20) Samsung K4W4G1646D-BC1A PU 24.9K
ROM_SO C12 ROM_SCLK
ROM_SCLK N16V-GM X76614BOL15 0xA (SA00008DN10) Hynix H5TC4G63CFR-N0C PU 45.3K PD 45.3K PU 10K PD 4.99K PD 45.3K PU 15K PU 4.99K PU 4.99K
X76614BOL02 0x2 (SA00006E840) Hynix H5TC4G63AFR-11C PD 15K
+1.5V Single
X76614BOL01 1GHz 256Mx16x4 0x1 (SA000077K20) Micron MT41J256M16HA-093G:E PD 10K
@
2G
X76614BOL03 0x4 (SA000076P20) Samsung K4W4G1646D-BC1A PD 24.9K
X76614BOL13 0x9 (SA00008DN10) Hynix H5TC4G63CFR-N0C PU 10K
4 4

N16X STRAPS 3/9
Size DocumentNumber
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
A4WAB M/B LA-C341P 0.2

A B C D E
A B C D E
NV 15x DG-06803-V03
NV 16x DG-07158-V04
1 1
UGPU1D +1.05VSDGPU
+1.5VSDGPU 3.24A 1.275A
Part 4 of 6
B26 AA10
.1U_0402_16V7K
.1U_0402_16V7K
4.7U_0603_6.3V6K
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12
10U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
E23 FBVDDQ_02 PEX_IOVDDQ_2 AA13

VGA@ C2039
VGA@ C2040
VGA@ C2032
VGA@ C2033
VGA@ C2021
VGA@ C2022
VGA@ C2013
VGA@ C2014
VGA@ C2016
VGA@ C2017
1 1 1 1 2 2 FBVDDQ_03 PEX_IOVDDQ_3 1 1 1 1
E26 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
2 2 2 2 1 1 G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20 2 2 2 2
G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21
G15 FBVDDQ_08 PEX_IOVDDQ_8 AB22
Under GPU G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25
10U_0603_6.3V6M
FBVDDQ_12 PEX_IOVDDQ_12 Under GPU Near GPU

G20 AF26
22U_0603_6.3V6M
VGA@ C2045
VGA@ C2047
1 1 FBVDDQ_13 PEX_IOVDDQ_13 Midway GPU & Power supply

G21 AF27
H24 FBVDDQ_14 PEX_IOVDDQ_14
H26 FBVDDQ_AON
2 2 J21 FBVDDQ_AON AA22
K21 FBVDDQ_AON PEX_IOVDD_1 AB23
L22 FBVDDQ_AON PEX_IOVDD_2 AC24
L24 FBVDDQ_19 PEX_IOVDD_3 AD25
Near GPU
POWER
L26 FBVDDQ_20 PEX_IOVDD_4 AE26
2 M21 FBVDDQ_21 PEX_IOVDD_5 AE27 2
N21 FBVDDQ_22 PEX_IOVDD_6
R21 FBVDDQ_23
T21 FBVDDQ_24
V21 FBVDDQ_25 +3VSDGPU_AON
W21 FBVDDQ_26
FBVDDQ_27 G10
3V3_AON G12
.1U_0402_16V7K
1U_0402_6.3V6K
56mA
4.7U_0603_6.3V6K
3V3_AON G8
VGA@ C2048
VGA@ C2049
VGA@ C2050
VDD33_3 2 1 1
G9
VDD33_4
V7 1 2 2
W7 NC +1.5VSDGPU
AA6 NC
W6 NC D22 FB_CAL_PD_VDDQ 1 VGA@ 2
NC FB_CAL_PD_VDDQ Under GPU Near GPU
Y6 40.2_0402_1% R2078 +3VSDGPU_MAIN
NC
C24 FB_CAL_PU_GND 1 VGA@ 2
FB_CAL_PU_GND 42.2_0402_1% R2079
.1U_0402_16V7K
.1U_0402_16V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
M7 B25 FB_CAL_TERM_GND1 VGA@ 2
VGA@ C2051
VGA@ C2052
VGA@ C2053
VGA@ C2054
NC FB_CAL_TERM_GND 2 2 1 1
N7 51.1_0402_1% R2080
T6 NC
P6 NC
NC 1 1 2 2
T7 Under GPU Near GPU

R7 IFPD_PLLVDD_2 +3VSDGPU_AON
U6 NC
R6 IFPD_RSET AA8
286mA
3 NC PEX_PLL_HVDD_1 AA9 3
PEX_PLL_HVDD_2
.1U_0402_16V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
AB8
VGA@ C2034
VGA@ C2035
VGA@ C2036
PEX_SVDD_3V3 2 1 1
J7
K7 NC 1 2 2
K6 NC AA14
H6 NC PEX_PLLVDD_1 AA15
J6 NC PEX_PLLVDD_2
NC Near GPU
R2075 @ +1.05VSDGPU
130mA 0_0603_5%
+PEX_PLLVDD 1 2
VGA@ C2041
VGA@ C2042
VGA@ C2043
.1U_0402_16V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
2 1 1
@ 1 2 2
Under GPU Near GPU
4 4

N16X POWER & GND 4/9

A B C D E
A B C D E
NV 15x DG-06803-V03
UGPU1E
NV 16x DG-07158-V04
1 1
A2 Part 5 of 6 K11
A26 GND_001 GND_057 K13
AB11 GND_002 GND_058 K15
AB14 GND_003 GND_059 K17
AB17 GND_004 GND_060 L10
AB20 GND_005 GND_061 L12
AB24 GND_006 GND_062 L14
AC2 GND_007 GND_063 L16
AC22 GND_008 GND_064 L18
AC26 GND_009 GND_065 L2
AC5 GND_010 GND_066 L23
AC8 GND_011 GND_067 L25 UGPU1F
AD12 GND_012 GND_068 L5 +VGA_CORE +VGA_CORE
AD13 GND_013 GND_069 M11 Part 6 of 6
AD15 GND_014 GND_070 M13
AD16 GND_015 GND_071 M15 K10 V18
AD18
AD19
GND_016
GND_017
GND_072
GND_073
M17
N10
K12
K14
VDD_001
VDD_002
VDD_041
VDD_040
V16
V14
DA-07312-V02
AD21 GND_018 GND_074 N12 K16 VDD_003 VDD_039 V12
AD22 GND_019 GND_075 N14 K18 VDD_004 VDD_038 V10
AE11 GND_020 GND_076 N16 L11 VDD_005 VDD_037 U17
GND_021 GND_077 VDD_006 VDD_036
POWER
AE14 N18 L13 U15
AE17 GND_022 GND_078 P11 L15 VDD_007 VDD_035 U13
AE20 GND_023 GND_079 P13 L17 VDD_008 VDD_034 U11
AF1 GND_024 GND_080 P15 M10 VDD_009 VDD_033 T18
GND

2 AF20 GND_028 GND_084 P26 M18 VDD_013 VDD_029 T10 2
AF23 GND_029 GND_085 P5 N11 VDD_014 VDD_028 R17
AF5 GND_030 GND_086 R10 N13 VDD_015 VDD_027 R15
AF8 GND_031 GND_087 R12 N15 VDD_016 VDD_026 R13
AG2 GND_032 GND_088 R14 N17 VDD_017 VDD_025 R11
AG26 GND_033 GND_089 R16 P10 VDD_018 VDD_024 P18
B1 GND_034 GND_090 R18 P12 VDD_019 VDD_023 P16
B11 GND_035 GND_091 T11 VDD_020 VDD_022 P14
B14 GND_036 GND_092 T13 VDD_021
B17 GND_037 GND_093 T15
B20 GND_038 GND_094 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12
B5 GND_041 GND_097 U14
B8 GND_042 GND_098 U16
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23 GM108-ES-S-A1_FCBGA595
E2 GND_046 GND_102 U26 @
E20 GND_047 GND_103 U5
E22 GND_048 GND_104 V11
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15
E8 GND_051 GND_107 V17
H2 GND_052 GND_108 Y2
H23
H25
GND_053
GND_054
GND_109
GND_110
Y23
Y26
DA-07314-V02
H5 GND_055 GND_111 Y5
GND_056 GND_112
3 3
AA7
GND AB7
GND
@
4 4

N16X POWER & GND 5/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAB M/B LA-C341P
A B C D E
A B C D E
VRAM DDR3 chips <20,25,26,27> DQSA[7..0]

DQSA[7..0]
DQSA#[7..0]
<20,25,26,27> DQSA#[7..0]
DQMA[7..0]
<20,25,26,27> DQMA[7..0]
MDA[63..0]
<20,25,26,27> MDA[63..0]
CMDA[30..0]
<20,25,26,27> CMDA[30..0]
Lower Rank 0 BOT SIDE
1 1
Rank0 Rank1
VRAM P/N: SA00006E840 Mode E
Address 0..31 32..63 0..31 32..63
U2004 X76@ CMD0 ODT ODT
+MEM_VREFCA0 M8 E3 MDA20 U2005 X76@ CMD1 CS1*
+MEM_VREFDQ0 H1 VREFCA DQL0 F7 MDA16
VREFDQ DQL1 F2 MDA21 +MEM_VREFCA0 M8 E3 MDA25
DQL2 VREFCA DQL0 CMD2 CS0*
CMDA7 N3 F8 MDA19 +MEM_VREFDQ0 H1 F7 MDA30
P7 A0 DQL3 H3 VREFDQ DQL1 F2
CMDA10
A1 DQL4
MDA23 Group2
DQL2
MDA24 CMD3 CKE CKE
CMDA24 P3 H8 MDA18 CMDA7 N3 F8 MDA28
CMDA6 N2 A2 DQL5 G2 MDA22 CMDA10 P7 A0 DQL3 H3 MDA27 Group3
A3 DQL6 A1 DQL4
CMD4 A9 A9 A11 A11
CMDA22 P8 H7 MDA17 CMDA24 P3 H8 MDA31
CMDA26 P2 A4 DQL7 CMDA6 N2 A2 DQL5 G2 MDA26
A5 A3 DQL6 CMD5 A6 A6 A7 A7
CMDA5 R8 CMDA22 P8 H7 MDA29
CMDA21 R2 A6 D7 MDA12 CMDA26 P2 A4 DQL7
A7 DQU0 A5 CMD6 A3 A3 BA1 BA1
CMDA8 T8 C3 MDA9 CMDA5 R8
R3 A8 DQU1 C8 R2 A6 D7
CMDA4
A9 DQU2
MDA14 CMDA21
A7 DQU0
MDA6 CMD7 A0 A0 A12 A12
CMDA25 L7 C2 MDA11 CMDA8 T8 C3 MDA1
CMDA23 R7 A10/AP DQU3 A7 MDA13 Group1 CMDA4 R3 A8 DQU1 C8 MDA4
A11 DQU4 A9 DQU2
CMD8 A8 A8 A8 A8
CMDA9 N7 A2 MDA10 CMDA25 L7 C2 MDA2
CMDA12 T3 A12 DQU5 B8 MDA15 CMDA23 R7 A10/AP DQU3 A7 MDA5 Group0
A13 DQU6 A11 DQU4 CMD9 A12 A12 A0 A0
CMDA14 T7 A3 MDA8 CMDA9 N7 A2 MDA0
M7 A14 DQU7 CMDA12 T3 A12 DQU5 B8 MDA7
A15/BA3 A13 DQU6 CMD10 A1 A1 A2 A2
+1.5VSDGPU CMDA14 T7 A3 MDA3
M7 A14 DQU7
A15/BA3 CMD11 RAS* RAS* RAS* RAS*
CMDA29 M2 B2 +1.5VSDGPU
CMDA13 N8 BA0 VDD D9
BA1 VDD
CMD12 A13 A13 A14 A14
CMDA27 M3 G7 CMDA29 M2 B2
BA2 VDD K2 CMDA13 N8 BA0 VDD D9
VDD BA1 VDD CMD13 BA1 BA1 A3 A3
K8 CMDA27 M3 G7
2 VDD N1 BA2 VDD K2 2
VDD VDD CMD14 A14 A14 A13 A13
CLKA0 J7 N9 K8
K7 CK VDD R1 VDD N1
CLKA0#
CK VDD VDD
CMD15 CAS* CAS* CAS* CAS*
CMDA3 K9 R9 CLKA0 J7 N9
CKE/CKE0 VDD +1.5VSDGPU CLKA0# K7 CK VDD R1
CK VDD CMD16 ODT ODT
CMDA3 K9 R9
CMDA0 K1 A1 CKE/CKE0 VDD +1.5VSDGPU
ODT/ODT0 VDDQ CMD17 CS1*
CMDA2 L2 A8
CMDA11 J3 CS/CS0 VDDQ C1 CMDA0 K1 A1
RAS VDDQ ODT/ODT0 VDDQ CMD18 CS0*
CMDA15 K3 C9 CMDA2 L2 A8
L3 CAS VDDQ D2 J3 CS/CS0 VDDQ C1
CMDA28
WE VDDQ
CMDA11
RAS VDDQ
CMD19 CKE CKE
E9 CMDA15 K3 C9
310mAVDDQ F1 CMDA28 L3 CAS VDDQ D2
VDDQ WE VDDQ
CMD20 RST RST RST RST
DQSA2 F3 H2 E9
DQSA1 C7 DQSL VDDQ H9 VDDQ F1
DQSU VDDQ 310mAVDDQ CMD21 A7 A7 A6 A6
DQSA3 F3 H2
DQSA0 C7 DQSL VDDQ H9
DQSU VDDQ CMD22 A4 A4 A5 A5
DQMA2 E7 A9
D3 DML VSS B3
DQMA1
DMU VSS CMD23 A11 A11 A9 A9
E1 DQMA3 E7 A9
VSS G8 DQMA0 D3 DML VSS B3
VSS DMU VSS CMD24 A2 A2 A1 A1
DQSA#2 G3 J2 E1
DQSA#1 B7 DQSL VSS J8 VSS G8
DQSU VSS VSS CMD25 A10 A10 WE* WE*
M1 DQSA#3 G3 J2
VSS M9 DQSA#0 B7 DQSL VSS J8
VSS DQSU VSS CMD26 A5 A5 A4 A4
P1 M1
T2 VSS P9 VSS M9
CMDA20
RESET VSS VSS
CMD27 BA2 BA2
T1 P1
ZQ0 L8 VSS T9 CMDA20 T2 VSS P9
ZQ/ZQ0 VSS RESET VSS
CMD28 WE* WE* A10 A10
T1
VSS
1
ZQ1 L8 T9 CMD29 BA0 BA0 BA0 BA0

J1 B1 ZQ/ZQ0 VSS
NC/ODT1 VSSQ
1
3 R2081 VGA@ L1 B9 CMD30 BA2 BA2 3
J9 NC/CS1 VSSQ D1 J1 B1
243_0402_1%
L9 NC/CE1 VSSQ D8 R2082 VGA@ L1 NC/ODT1 VSSQ B9
NCZQ1 VSSQ NC/CS1 VSSQ Not Available
2
E2 243_0402_1% J9 D1
VSSQ E8 L9 NC/CE1 VSSQ D8
VSSQ NCZQ1 VSSQ
2
F9 E2
VSSQ G1 VSSQ E8
VSSQ VSSQ Command Bit Default Pull-down
G9 F9
VSSQ VSSQ G1 ODTx 10k
VSSQ G9
96-BALL
SDRAM DDR3 VSSQ DDR3 CKEx 10k
H5TQ2G63BFR-11C_FBGA96 96-BALL RST 10k
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 CS* No Termination
CLKA0
<20,25> CLKA0
+1.5VSDGPU +1.5VSDGPU
1
VGA@
1
R2087
162_0402_1% R2085 R2086
VGA@ VGA@
2
CLKA0# 1.33K_0402_1% 1.33K_0402_1%

<20,25> CLKA0#
2
+MEM_VREFCA0 +MEM_VREFCA0 <25> +MEM_VREFDQ0 +MEM_VREFDQ0 <25>
1
CMDA0 R2093 1 VGA@ 2 10K_0402_5% 1 1
+1.5VSDGPU CMDA3 R2094 1 VGA@ 2 10K_0402_5% R2091 R2092
CMDA16 R2095 1 VGA@ 2 10K_0402_5% VGA@ C2055 VGA@ VGA@ C2056 VGA@
4 CMDA19 R2098 1 VGA@ 2 10K_0402_5% 1.33K_0402_1% .1U_0402_16V7K 1.33K_0402_1% .1U_0402_16V7K 4
CMDA20 R2099 1 VGA@ 2 10K_0402_5% 2 2
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
VGA@ C2071
VGA@ C2072
VGA@ C2073
VGA@ C2074
VGA@ C2075
VGA@ C2076
VGA@ C2077
VGA@ C2078
VGA@ C2079
VGA@ C2080
VGA@ C2081
VGA@ C2082
1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2
N16X Upper Rank0 6/9
Size DocumentNumber
Custom

A B C D E
A B C D E

DQSA[7..0]
DQSA#[7..0]
<20,24,26,27> DQSA#[7..0]
DQMA[7..0]
<20,24,26,27> DQMA[7..0]
MDA[63..0]
<20,24,26,27> MDA[63..0]
CMDA[30..0]
<20,24,26,27> CMDA[30..0]
1 1
Lower Rank 1 TOP SIDE Mode E

Address 0..31
Rank0
32..63 0..31
Rank1
32..63
CMD0 ODT ODT
U2007 X76@
U2006 X76@ CMD1 CS1*
+MEM_VREFCA0M8 E3 MDA30
+MEM_VREFCA0 M8 E3 MDA16 +MEM_VREFDQ0H1 VREFCA DQL0 F7 MDA25
<24> +MEM_VREFCA0 VREFCA DQL0 VREFDQ DQL1 CMD2 CS0*
+MEM_VREFDQ0 H1 F7 MDA20 F2 MDA28
<24> +MEM_VREFDQ0 VREFDQ DQL1 F2 N3 DQL2 F8
MDA19 CMDA9 MDA24 CMD3 CKE CKE
CMDA9 N3 DQL2 F8 MDA21 CMDA24 P7 A0 DQL3 H3 MDA29 Group3
CMDA24 P7 A0 DQL3 H3 MDA17 Group2 CMDA10 P3 A1 DQL4 H8 MDA26
A1 DQL4 A2 DQL5
CMD4 A9 A9 A11 A11
CMDA10 P3 H8 MDA22 CMDA13 N2 G2 MDA31
CMDA13 N2 A2 DQL5 G2 MDA18 CMDA26 P8 A3 DQL6 H7 MDA27
A3 DQL6 A4 DQL7 CMD5 A6 A6 A7 A7
CMDA26 P8 H7 MDA23 CMDA22 P2
CMDA22 P2 A4 DQL7 CMDA21 R8 A5
A5 A6 CMD6 A3 A3 BA1 BA1
CMDA21 R8 CMDA5 R2 D7 MDA1
CMDA5 R2 A6 D7 MDA9 CMDA8 T8 A7 DQU0 C3 MDA6
A7 DQU0 A8 DQU1
CMD7 A0 A0 A12 A12
CMDA8 T8 C3 MDA12 CMDA23 R3 C8 MDA2
CMDA23 R3 A8 DQU1 C8 MDA11 CMDA28 L7 A9 DQU2 C2 MDA4
A9 DQU2 A10/AP DQU3 CMD8 A8 A8 A8 A8
CMDA28 L7 C2 MDA14 CMDA4 R7 A7 MDA3 Group0
CMDA4 R7 A10/AP DQU3 A7 MDA8 Group1 CMDA7 N7 A11 DQU4 A2 MDA7
CMDA7 N7 A2 MDA15 CMDA14 T3 B8 MDA0
T3 A12 DQU5 B8 T7 A13 DQU6 A3
CMDA14
A13 DQU6
MDA10 CMDA12
A14 DQU7
CMDA12 T7 A3 MDA13 M7
M7 A14 DQU7 A15/BA3 +1.5VSDGPU
A15/BA3
CMD11 RAS* RAS* RAS* RAS*
+1.5VSDGPU
CMDA29 M2 B2 CMD12 A13 A13 A14 A14
CMDA29 M2 B2 CMDA6 N8 BA0 VDD D9
CMDA6 N8 BA0 VDD D9 CMDA30 M3 BA1 VDD G7
BA1 VDD BA2 VDD CMD13 BA1 BA1 A3 A3
2 CMDA30 M3 G7 K2 2
BA2 VDD K2 VDD K8
VDD VDD
CMD14 A14 A14 A13 A13
K8 N1
VDD N1 CLKA0 J7 VDD N9
VDD CK VDD
CMD15 CAS* CAS* CAS* CAS*
CLKA0 J7 N9 CLKA0# K7 R1
<20,24> CLKA0 CLKA0# K7 CK VDD R1 CMDA3 K9 CK VDD R9
<20,24> CLKA0# CK VDD CKE/CKE0 VDD CMD16 ODT ODT
CMDA3 K9 R9 +1.5VSDGPU
CKE/CKE0 VDD +1.5VSDGPU CMD17 CS1*
CMDA0 K1 A1
CMDA0 K1 A1 CMDA1 L2 ODT/ODT0 VDDQ A8
ODT/ODT0 VDDQ CS/CS0 VDDQ CMD18 CS0*
CMDA1 L2 A8 CMDA11 J3 C1
CMDA11 J3 CS/CS0 VDDQ C1 CMDA15 K3 RAS VDDQ C9
RAS VDDQ CAS VDDQ
CMD19 CKE CKE
CMDA15 K3 C9 CMDA25 L3 D2
CMDA25 L3 CAS VDDQ D2 WE VDDQ E9
WE VDDQ 310mAVDDQ CMD20 RST RST RST RST
E9 F1
310mAVDDQ F1 DQSA3 F3 VDDQ H2
VDDQ DQSL VDDQ CMD21 A7 A7 A6 A6
DQSA2 F3 H2 DQSA0 C7 H9
C7 DQSL VDDQ H9 DQSU VDDQ
DQSA1
DQSU VDDQ CMD22 A4 A4 A5 A5
DQMA3 E7 A9 CMD23 A11 A11 A9 A9
DQMA2 E7 A9 DQMA0 D3 DML VSS B3
DQMA1 D3 DML VSS B3 DMU VSS E1
DMU VSS VSS CMD24 A2 A2 A1 A1
E1 G8
VSS G8 DQSA#3 G3 VSS J2
VSS DQSL VSS CMD25 A10 A10 WE* WE*
DQSA#2 G3 J2 DQSA#0 B7 J8
B7 DQSL VSS J8 DQSU VSS M1
DQSA#1
DQSU VSS VSS
CMD26 A5 A5 A4 A4
M1 M9
VSS M9 VSS P1
VSS VSS CMD27 BA2 BA2
P1 CMDA20 T2 P9
CMDA20 T2 VSS P9 RESET VSS T1
RESET VSS VSS CMD28 WE* WE* A10 A10
T1 ZQ3 L8 T9
ZQ2 L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS CMD29 BA0 BA0 BA0 BA0
1
3 VGA@ 3
1
R2101 J1 B1 CMD30 BA2 BA2

VGA@ J1 B1 243_0402_1% L1 NC/ODT1 VSSQ B9
R2100 L1 NC/ODT1 VSSQ B9 J9 NC/CS1 VSSQ D1
NC/CS1 VSSQ NC/CE1 VSSQ Not Available
243_0402_1% J9 D1 L9 D8
NC/CE1 VSSQ NCZQ1 VSSQ
2
L9 D8 E2
NCZQ1 VSSQ VSSQ
2
E2 E8
VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
VSSQ G1 VSSQ G9
G9
VSSQ 96-BALL ODTx 10k
96-BALL SDRAM DDR3
SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 DDR3 CKEx 10k
H5TQ2G63BFR-11C_FBGA96 RST 10k
CS* No Termination
+1.5VSDGPU
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
VGA@ C2059
VGA@ C2060
VGA@ C2061
VGA@ C2062
VGA@ C2063
VGA@ C2064
VGA@ C2065
VGA@ C2066
VGA@ C2067
VGA@ C2068
VGA@ C2069
VGA@ C2070
1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2
4 4

N16X Upper Rank1 7/9
Size DocumentNumber
Custom

A B C D E
A B C D E

DQSA[7..0]
DQSA#[7..0]
<20,24,25,27> DQSA#[7..0]
DQMA[7..0]
<20,24,25,27> DQMA[7..0]
MDA[63..0]
<20,24,25,27> MDA[63..0]
CMDA[30..0]
<20,24,25,27> CMDA[30..0]
Upper Rank 0 BOT SIDE Mode E

Rank0 Rank1
1 1
Address 0..31 32..63 0..31 32..63
CMD0 ODT ODT
U2008 X76@ U2009 X76@
CMD1 CS1*
+MEM_VREFCA1 M8 E3 MDA33 +MEM_VREFCA1 M8 E3 MDA50
+MEM_VREFDQ1 H1 VREFCA DQL0 F7 MDA39 +MEM_VREFDQ1 H1 VREFCA DQL0 F7 MDA52
VREFDQ DQL1 VREFDQ DQL1 CMD2 CS0*
F2 MDA32 F2 MDA49
CMDA7 N3 DQL2 F8 MDA36 CMDA7 N3 DQL2 F8 MDA53
A0 DQL3 A0 DQL3 CMD3 CKE CKE
CMDA10 P7 H3 MDA35 Group4 CMDA10 P7 H3 MDA48 Group6
P3 A1 DQL4 H8 P3 A1 DQL4 H8
CMDA24
A2 DQL5
MDA37 CMDA24
A2 DQL5
CMDA6 N2 G2 MDA34 CMDA6 N2 G2 MDA51
CMDA22 P8 A3 DQL6 H7 MDA38 CMDA22 P8 A3 DQL6 H7 MDA54
A4 DQL7 A4 DQL7
CMD5 A6 A6 A7 A7
CMDA26 P2 CMDA26 P2
CMDA5 R8 A5 CMDA5 R8 A5
A6 A6 CMD6 A3 A3 BA1 BA1
CMDA21 R2 D7 MDA56 CMDA21 R2 D7 MDA41
CMDA8 T8 A7 DQU0 C3 MDA59 CMDA8 T8 A7 DQU0 C3 MDA44
CMDA4 R3 C8 MDA58 CMDA4 R3 C8 MDA40
L7 A9 DQU2 C2 L7 A9 DQU2 C2
CMDA25
A10/AP DQU3
MDA62 CMDA25
A10/AP DQU3
CMDA23 R7 A7 MDA57 Group7 CMDA23 R7 A7 MDA43 Group5
CMDA9 N7 A11 DQU4 A2 MDA61 CMDA9 N7 A11 DQU4 A2 MDA47
A12 DQU5 A12 DQU5
CMD9 A12 A12 A0 A0
CMDA12 T3 B8 MDA60 CMDA12 T3 B8 MDA42
CMDA14 T7 A13 DQU6 A3 MDA63 CMDA14 T7 A13 DQU6 A3 MDA45
M7 M7
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU CMD11 RAS* RAS* RAS* RAS*
CMDA29 M2 B2 CMDA29 M2 B2 CMD12 A13 A13 A14 A14
CMDA13 N8 BA0 VDD D9 CMDA13 N8 BA0 VDD D9
CMDA27 M3 BA1 VDD G7 CMDA27 M3 BA1 VDD G7
BA2 VDD BA2 VDD
CMD13 BA1 BA1 A3 A3
K2 K2
VDD K8 VDD K8
VDD VDD CMD14 A14 A14 A13 A13
N1 N1
2 CLKA1 J7 VDD N9 CLKA1 J7 VDD N9 2
CK VDD CK VDD CMD15 CAS* CAS* CAS* CAS*
CLKA1# K7 R1 CLKA1# K7 R1
K9 CK VDD R9 K9 CK VDD R9
CMDA19
CKE/CKE0 VDD
CMDA19
CKE/CKE0 VDD
CMD16 ODT ODT
CMD17 CS1*
CMDA16 K1 A1 CMDA16 K1 A1
CMDA18 L2 ODT/ODT0 VDDQ A8 CMDA18 L2 ODT/ODT0 VDDQ A8
CS/CS0 VDDQ CS/CS0 VDDQ CMD18 CS0*
CMDA11 J3 C1 CMDA11 J3 C1
CMDA15 K3 RAS VDDQ C9 CMDA15 K3 RAS VDDQ C9
CAS VDDQ CAS VDDQ CMD19 CKE CKE
CMDA28 L3 D2 CMDA28 L3 D2
WE VDDQ E9 WE VDDQ E9
VDDQ 310mAVDDQ CMD20 RST RST RST RST
F1 F1
DQSA4 F3
310mAVDDQ H2 DQSA6 F3 VDDQ H2
DQSL VDDQ DQSL VDDQ CMD21 A7 A7 A6 A6
DQSA7 C7 H9 DQSA5 C7 H9
DQSU VDDQ DQSU VDDQ
CMD22 A4 A4 A5 A5
DQMA4 E7 A9 DQMA6 E7 A9 CMD23 A11 A11 A9 A9
DQMA7 D3 DML VSS B3 DQMA5 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS VSS
CMD24 A2 A2 A1 A1
G8 G8
DQSA#4 G3 VSS J2 DQSA#6 G3 VSS J2
DQSL VSS DQSL VSS
CMD25 A10 A10 WE* WE*
DQSA#7 B7 J8 DQSA#5 B7 J8
DQSU VSS M1 DQSU VSS M1
VSS VSS CMD26 A5 A5 A4 A4
M9 M9
VSS P1 VSS P1
VSS VSS CMD27 BA2 BA2
CMDA20 T2 P9 CMDA20 T2 P9
RESET VSS T1 RESET VSS T1
VSS VSS
CMD28 WE* WE* A10 A10
ZQ5 L8 T9 ZQ4 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
CMD29 BA0 BA0 BA0 BA0
1
1
J1 B1 J1 B1 CMD30 BA2 BA2
R2083 VGA@ L1 NC/ODT1 VSSQ B9 R2084 VGA@ L1 NC/ODT1 VSSQ B9
3 J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1 3
243_0402_1% 243_0402_1% Not Available
L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ NCZQ1 VSSQ
2
2
E2 E2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
Command Bit Default Pull-down
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 ODTx 10k
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96
DDR3 CKEx 10k
RST 10k
CS* No Termination
+1.5VSDGPU
1
1
R2088 R2089 CLKA1
<20,27> CLKA1
VGA@ VGA@
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1.33K_0402_1% 1.33K_0402_1%
VGA@ C2098
VGA@ C2104
VGA@ C2094
VGA@ C2103
VGA@ C2095
VGA@ C2097
VGA@ C2100
VGA@ C2096
VGA@ C2102
VGA@ C2101
VGA@ C2099
VGA@ C2105
1 1 1 1 1 1 1 1 1 1 1 1 VGA@
2
2
R2103
+MEM_VREFCA1 +MEM_VREFCA1 <27> +MEM_VREFDQ1 +MEM_VREFDQ1 <27> 162_0402_1%
2
2 2 2 2 2 2 2 2 2 2 2 2
1
1
1 1 CLKA1#
<20,27> CLKA1#
R2096 R2097
VGA@ C2057 VGA@ VGA@ C2058 VGA@
1.33K_0402_1% .1U_0402_16V7K 1.33K_0402_1% .1U_0402_16V7K
2 2
2
2
4 4

N16X Lower Rank0 8/9
Size DocumentNumber
Custom

A B C D E
A B C D E

DQSA[7..0]
DQSA#[7..0]
<20,24,25,26> DQSA#[7..0]
DQMA[7..0]
<20,24,25,26> DQMA[7..0]
MDA[63..0]
<20,24,25,26> MDA[63..0]
CMDA[30..0]
<20,24,25,26> CMDA[30..0]
1
Upper Rank 1 TOP SIDE 1
Rank0 Rank1
Mode E
Address 0..31 32..63 0..31 32..63
CMD0 ODT ODT
U2010 X76@ U2011 X76@
CMD1 CS1*
+MEM_VREFCA1 M8 E3 MDA39 +MEM_VREFCA1M8 E3 MDA52
<26> +MEM_VREFCA1 VREFCA DQL0 VREFCA DQL0
+MEM_VREFDQ1 H1 F7 MDA33 +MEM_VREFDQ1H1 F7 MDA50 CMD2 CS0*
<26> +MEM_VREFDQ1 VREFDQ DQL1 F2 VREFDQ DQL1 F2
MDA36 MDA53
CMDA9 N3 DQL2 F8 MDA32 CMDA9 N3 DQL2 F8 MDA49
A0 DQL3 A0 DQL3
CMD3 CKE CKE
CMDA24 P7 H3 MDA38 Group4 CMDA24 P7 H3 MDA54 Group6
CMDA13 N2 G2 MDA37 CMDA13 N2 G2 MDA55
CMDA22 P2 CMDA22 P2
R8 A5 R8 A5
CMDA21
A6
CMDA21
A6
CMD6 A3 A3 BA1 BA1
CMDA5 R2 D7 MDA59 CMDA5 R2 D7 MDA44
CMDA8 T8 A7 DQU0 C3 MDA56 CMDA8 T8 A7 DQU0 C3 MDA41
A8 DQU1 A8 DQU1
CMD7 A0 A0 A12 A12
CMDA23 R3 C8 MDA62 CMDA23 R3 C8 MDA46
CMDA28 L7 A9 DQU2 C2 MDA58 CMDA28 L7 A9 DQU2 C2 MDA40
A10/AP DQU3 A10/AP DQU3 CMD8 A8 A8 A8 A8
CMDA4 R7 A7 MDA63 Group7 CMDA4 R7 A7 MDA45 Group5
CMDA7 N7 A11 DQU4 A2 MDA60 CMDA7 N7 A11 DQU4 A2 MDA42
A5MUB SWAP
CMDA14 T3 B8 MDA61 CMDA14 T3 B8 MDA47
CMDA12 T7 A13 DQU6 A3 MDA57 CMDA12 T7 A13 DQU6 A3 MDA43
M7 M7
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU CMD11 RAS* RAS* RAS* RAS*
CMDA29 M2 B2 CMDA29 M2 B2 CMD12 A13 A13 A14 A14
CMDA6 N8 BA0 VDD D9 CMDA6 N8 BA0 VDD D9
2 CMDA30 M3 BA1 VDD G7 CMDA30 M3 BA1 VDD G7 2
BA2 VDD BA2 VDD CMD13 BA1 BA1 A3 A3
K2 K2
VDD K8 VDD K8
VDD VDD
CMD14 A14 A14 A13 A13
N1 N1
CLKA1 J7 VDD N9 CLKA1 J7 VDD N9
<20,26> CLKA1 CK VDD CK VDD CMD15 CAS* CAS* CAS* CAS*
CLKA1# K7 R1 CLKA1# K7 R1
<20,26> CLKA1# CMDA19 K9 CK VDD R9 CMDA19 K9 CK VDD R9
CKE/CKE0 VDD CKE/CKE0 VDD CMD16 ODT ODT
CMD17 CS1*
CMDA16 K1 A1 CMDA16 K1 A1
L2 ODT/ODT0 VDDQ A8 L2 ODT/ODT0 VDDQ A8
CMDA17
CS/CS0 VDDQ
CMDA17
CS/CS0 VDDQ
CMD18 CS0*
CMDA11 J3 C1 CMDA11 J3 C1
CMDA15 K3 RAS VDDQ C9 CMDA15 K3 RAS VDDQ C9
CAS VDDQ CAS VDDQ CMD19 CKE CKE
CMDA25 L3 D2 CMDA25 L3 D2
WE VDDQ E9 WE VDDQ E9
310mAVDDQ 310mAVDDQ CMD20 RST RST RST RST
F1 F1
DQSA4 F3 VDDQ H2 DQSA6 F3 VDDQ H2
DQSL VDDQ DQSL VDDQ CMD21 A7 A7 A6 A6
DQSA7 C7 H9 DQSA5 C7 H9
DQSU VDDQ DQSU VDDQ
CMD22 A4 A4 A5 A5
DQMA4 E7 A9 DQMA6 E7 A9 CMD23 A11 A11 A9 A9
DQMA7 D3 DML VSS B3 DQMA5 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS VSS CMD24 A2 A2 A1 A1
G8 G8
DQSA#4 G3 VSS J2 DQSA#6 G3 VSS J2
DQSL VSS DQSL VSS CMD25 A10 A10 WE* WE*
DQSA#7 B7 J8 DQSA#5 B7 J8
DQSU VSS M1 DQSU VSS M1
VSS VSS
CMD26 A5 A5 A4 A4
M9 M9
VSS P1 VSS P1
VSS VSS
CMD27 BA2 BA2
CMDA20 T2 P9 CMDA20 T2 P9
RESET VSS T1 RESET VSS T1
VSS VSS CMD28 WE* WE* A10 A10
ZQ6 L8 T9 ZQ7 L8 T9
3 ZQ/ZQ0 VSS ZQ/ZQ0 VSS 3
CMD29 BA0 BA0 BA0 BA0
1
1
J1 B1 J1 B1 CMD30 BA2 BA2
R2090 VGA@ L1 NC/ODT1 VSSQ B9 R2102 VGA@ L1 NC/ODT1 VSSQ B9
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
NC/CE1 VSSQ NC/CE1 VSSQ Not Available
L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
2
2
E2 E2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
96-BALL 96-BALL ODTx 10k
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 DDR3 CKEx 10k
RST 10k
CS* No Termination
+1.5VSDGPU
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
VGA@ C2151
VGA@ C2147
VGA@ C2150
VGA@ C2148
VGA@ C2149
VGA@ C2107
VGA@ C2152
VGA@ C2146
VGA@ C2109
VGA@ C2108
VGA@ C2106
VGA@ C2110
1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2
4 4

N16X Lower Rank1 9/9
Size DocumentNumber
Custom

A B C D E
A B C D E
EDP / LVDS conn. Place closed to JLVDS1

+LCDVDD
+3VS
1 1
C375
C419 @
1
LCD POWER CIRCUIT 2
0.1U_0402_16V7K
2
.1U_0402_16V7K
1
W=60mils W=60mils
+3VS +LCDVDD +19VB +INVPWR_B+
U8 W=60mils
5 1
1U_0402_6.3V6K
C140
IN OUT L11
1
2 1 1 HCB2012KF-221T30_2P
GND 1 2
4 3 C368 @ EMI@
2 EN OC .1U_0402_16V7K XEMI@ 1 1 XEMI@
SY6288C20AAC_SOT23-5 C367 2 2 C365 C364
4.7U_0603_6.3V6K 68P_0402_50V8J 1000P_0402_50V7K
<10> PCH_ENVDD 2 2
SM01000EJ00 3000ma
220ohm@100m hz Follow A4QAS pin assignment
DCR 0.04
LCD/ LED PANEL Conn.
C372 1 2 .1U_0402_16V7K EDP_TXN0_C +INVPWR_B+ JEDP1

<6> EDP_TXN0 W=60mils
C371 1 2 .1U_0402_16V7K EDP_TXP0_C 1
<6> EDP_TXP0 2 1 41
XEMI@ 3 2 G1 42
C374 1 2 .1U_0402_16V7K EDP_TXN1_C PCH_INV_PWM C549 1 2 220P_0402_50V7K 4 3 G2 43
<6> EDP_TXN1 <10> PCH_INV_PWM W=60mils 4 G3
C373 1 2 .1U_0402_16V7K EDP_TXP1_C 5 44
<6> EDP_TXP1 5 G4
BKOFF# C528 1 2 220P_0402_50V7K PCH_INV_PWM 6 45
<38> BKOFF# 7 6 G5 46
4K2K@ BKOFF#
C376 1 2 .1U_0402_16V7K EDP_TXN2_C XEMI@ +LCDVDD EDP_HPD 8 7 G6
<6> EDP_TXN2 8
2 C377 1 2 .1U_0402_16V7K EDP_TXP2_C 9 2
<6> EDP_TXP2 10 9
4K2K@
4K2K@ 11 10
C388 1 2 .1U_0402_16V7K EDP_TXN3_C 12 11
<6> EDP_TXN3 12
C389 1 2 .1U_0402_16V7K EDP_TXP3_C EDP_AUXN_C 13
<6> EDP_TXP3 EDP_AUXP_C 14 13
4K2K@
15 14
+3VS EDP_TXP0_C 16 15
EDP_TXN0_C 17 16
17
<6> EDP_AUXN C369 1 2 .1U_0402_16V7K EDP_AUXN_C R613 2 @ 1 100K_0402_5% 18
18
<6> EDP_AUXP C370 1 2 .1U_0402_16V7K EDP_AUXP_C R614 2 @ 1 100K_0402_5% EDP_TXP1_C 19
EDP_TXN1_C 20 19
21 20
EDP_TXP2_C 22 21
EDP_TXN2_C 23 22
1 2 EDP_HPD 24 23
<10> CPU_EDP_HPD @
R406 EDP_TXP3_C 25 24
25
1
0_0402_5% EDP_TXN3_C 26
27 26
+TS_PWR 27
R364 28
100K_0402_5% 29 28
<38> TS_EN USB20_P5 30 29
<12> USB20_P5 30
2
USB20_N5 31
<12> USB20_N5 31
PCH_I2C0_SCL 32
<11> PCH_I2C0_SCL PCH_I2C0_SDA 33 32
Touch Screen <11> PCH_I2C0_SDA 33
I2C_TS_RST# 34
<38> I2C_TS_RST# 34
I2C_TS_INT# 35
<11> I2C_TS_INT# 35
36
37 36
+3VS 37
USB20_P6_CAMERA 38
USB20_N6_CAMERA 39 38
For Camera 39
40
3 40 3
E-T_0871K-F40N-00L
CONN@
SP010011Z00
Touch Screen
+3VS
+TS_PWR Camera
@ R82
0_0603_5%
1 2
R427 1 @ 2 0_0402_5%
+5VS @ R81
0_0603_5% R428 1 @ 2 0_0402_5%
1 2
USB20_N6 3 4 USB20_N6_CAMERA
<12> USB20_N6 3 4
USB20_P6 2 1 USB20_P6_CAMERA
<12> USB20_P6 2 1
L27
CMMI21T-900Y-N_4P
4 XEMI@ 4

eDP Connector
Size DocumentNumber
Custom

A B C D E
A B C D E
HDMI conn.
SM070001310 400ma 90ohm@100mhz DCR 0.3
+HDMI_5V_OUT
+5VS U3
3
W=40mils HDMI_CLK- R368 1 @ 2 0_0402_5% HDMI_R_CK-
1 VOUT EMI@ 1
1
1 C378 L2507 XEMI@
VIN .1U_0402_16V7K 1 2
1 1 1 2
EMI@ EMI@ 2
C398 C396 GND 2
.1U_0402_16V7K .1U_0402_16V7K 4 3
2 2 4 3
APL3517AI-TRG_SOT23-3
WCM2012F2S-900T04_0805
HDMI_CLK+ R369 1 @ 2 0_0402_5% HDMI_R_CK+
HDMI_TX0- R370 1 @ 2 0_0402_5% HDMI_R_D0-
L2508 XEMI@
1 2
1 2
RP17
470_8P4R_5% 4 3
C385 2 1 0.1U_0402_16V7K HDMI_CLK- 4 5 4 3
<6> CPU_DP2_N3
C386 2 1 0.1U_0402_16V7K HDMI_CLK+ 3 6 WCM2012F2S-900T04_0805
<6> CPU_DP2_P3
C381 2 1 0.1U_0402_16V7K HDMI_TX1- 2 7
<6> CPU_DP2_N1
C382 2 1 0.1U_0402_16V7K HDMI_TX1+ 1 8 HDMI_TX0+ R371 1 @ 2 0_0402_5% HDMI_R_D0+
<6> CPU_DP2_P1
HDMI_GND
C383 2 1 0.1U_0402_16V7K HDMI_TX0- 4 5
<6> CPU_DP2_N2
C384 2 1 0.1U_0402_16V7K HDMI_TX0+ 3 6 HDMI_TX1- R372 1 @ 2 0_0402_5% HDMI_R_D1-
<6> CPU_DP2_P2
C379 2 1 0.1U_0402_16V7K HDMI_TX2- 2 7
<6> CPU_DP2_N0
C380 2 1 0.1U_0402_16V7K HDMI_TX2+ 1 8 L2509 XEMI@
<6> CPU_DP2_P0
1 2
RP18 1 2
470_8P4R_5%
3
4 3
2 4 3 2
Q14B WCM2012F2S-900T04_0805
5 L2N7002DW1T1G_SC88-6
+3VS
HDMI_TX1+ R373 1 @ 2 0_0402_5% HDMI_R_D1+
4
HDMI_TX2- R374 1 @ 2 0_0402_5% HDMI_R_D2-
RP15 L2510 XEMI@

1 8 HDMI_SCLK 1 2
2 7 HDMI_SDATA 1 2
+HDMI_5V_OUT
3 6 DDI2_CTRL_CK
4 5 DDI2_CTRL_DATA 4 3
+3VS 4 3
2.2K_0804_8P4R_5% WCM2012F2S-900T04_0805
HDMI_TX2+ R375 1 @ 2 0_0402_5% HDMI_R_D2+

+3VS
Q15A
2
1 6 HDMI_SCLK
<10> DDI2_CTRL_CK
HDMI connector
JHDMI1
5
Q15B HDMI_HPD 19
3 18 HP_DET 3
L2N7002DW1T1G_SC88-6 +HDMI_5V_OUT
17 +5V
4 3 HDMI_SDATA HDMI_SDATA 16 DDC/CEC_GND
<10> DDI2_CTRL_DATA SDA
HDMI_SCLK 15
14 SCL
Reserved
2
13
HDMI_R_CK- 12 CEC 20
11 CK- GND 21
HDMI_R_CK+ 10 CK_shield GND 22
HDMI_R_D0- 9 CK+ GND 23
D2015
YSLC05CH_SOT23-3 8 D0- GND
+3VS XESD@ HDMI_R_D0+ 7 D0_shield
+3VS HDMI_R_D1- 6 D0+
5 D1-
D1_shield
1
1
Q14A HDMI_R_D1+ 4
HDMI_R_D2- 3 D1+
R376 L2N7002DW1T1G_SC88-6
D2-
2
1M_0402_5% 2
HDMI_R_D2+ 1 D2_shield
D2+
2
1 6 HDMI_HPD LCN_AUF05-1922S10-0019
<10> CPU_HDMI_HPD
CONN@
1
DC232002K00
R121
100K_0402_5%
2
4 4

HDMI Conn
Size DocumentNumber
Custom

A B C D E
5 4 3 2 1
DP to VGA Realtek RTD2168
D D
+3VS +HDMI_5V_OUT
L6
1 2 +3VS_CRT
FBMA-L11-160808-800LMT_0603
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
10U_0603_6.3V6M
1 1 1 1
<10> SOC_DP1_HPD
C1
C5
C73
C4
2
2.2K_0402_5%
2.2K_0402_5%
2 2 2 2
1
R2530 @
100K_0402_5%
R16
R22
1
1
2
20
U2
9
DVCC_33
DVCC_33
VDD_DAC_33
SOC_DP1_HPD 1
HPD
C19 1 2 0.1U_0402_16V7K SOC_DP1_AUXN_C 27 6 CRT_DATA
<10> SOC_DP1_AUXN AUX_N VGA_SDA CRT_DATA <31>
C72 1 2 0.1U_0402_16V7K SOC_DP1_AUXP_C 26 4 CRT_CLK
<10> SOC_DP1_AUXP AUX_P VGA_SCL CRT_CLK <31>
8 HSYNC
HSYNC HSYNC <31>
C68 1 2 0.1U_0402_16V7K SOC_DP1_P0_C 29 7 VSYNC
<6> SOC_DP1_P0 LANE0P VSYNC VSYNC <31>
C71 1 2 0.1U_0402_16V7K SOC_DP1_N0_C 30
<6> SOC_DP1_N0 LANE0N 15 CRT_R
1 2 0.1U_0402_16V7K SOC_DP1_P1_C 31 RED_P CRT_R <31>
C65
<6> SOC_DP1_P1 LANE1P
C69 1 2 0.1U_0402_16V7K SOC_DP1_N1_C 32 12 CRT_G
<6> SOC_DP1_N1 LANE1N GREEN_P CRT_G <31>
10 CRT_B
+3VS BLUE_P CRT_B <31>
C 22 POL1_SDA C
POL1_SDA
4
3
2
1
C35 2 1 2.2U_0402_6.3V6M 23 POL2_SCL
POL2_SCL 75_0804_8P4R_1%
C26 2 1 0.1U_0402_16V7K VCCK_12 19 2 CRT_SMB_CLK R18 1 @ 2 0_0402_5% RP52
VCCK_12 SMB_SCL 3 CRT_SMB_SDA R19 1 @ 2 0_0402_5%
10/7. Follow vendor review result, change U2 C70 2 1 0.1U_0402_16V7K 24 SMB_SDA
pin 25 netname from AVCC_12 to VCCK_12, the AVCC_33
5
6
7
8
same with U2 pin 19. C67 2 1 0.1U_0402_16V7K VCCK_12 25
AVCC_12 21 LDO_EN
1 2 12K_0402_1% 28 LDO_EN
R21
RRX
18
11 XO
13 BLUE_N 17
14 GREEN_N XI/CKIN
16 GND_DAC
33 RED_N EC_SMB_CK2
EPAD_GND EC_SMB_CK2 <9,19,38>
EC_SMB_DA2
EC_SMB_DA2 <9,19,38>
2
RTD2168-CG_QFN32_5X5
C63 Address:(layout guide P.11)
10U_0603_6.3V6M
1 Please reserve slave address of
0x64/0x65 and 0x68/0x69 for RTD2168’s use
B +3VS +3VS +3VS B

4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1
1
R17 @
R12
R14
POL_SDA
2
0 1 LDO_EN:
POL2_SCL POL1_SDA LDO_EN
*1: Internal 1.2V
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
0 X EP
0: External 1.2V
1
1
R23 @
POL_SCL
R15
R20
1 *ROM EEPROM
@
ROM: Internal ROM

2
EP: Programmed external EC

EEPROM: External ROM
A A

Realtek RTD2168
Size DocumentNumber
Custom

5 4 3 2 1
A B C D E
CRT conn.
1 1
W=40mils
SM01000LU00 ( S SUPPRE_ MURATA BLM15BA220SN1D 0402)
+HDMI_5V_OUT
L2503 EMI@
BLM15BA220SN1D_2P CRT Connector
1 2 CRT_R_2 JCRT1
<30> CRT_R
L2505 EMI@ 6
BLM15BA220SN1D_2P T99 @ 11
1 2 CRT_G_2 1
<30> CRT_G
L2504 EMI@ 7
BLM15BA220SN1D_2P 12
1 2 CRT_B_2 2
<30> CRT_B
8
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
13
1 1 1 1 1 1 3
9
C2529
C2530
C2531
C2532
C2533
C2534
14
T109 @ 4
2 2 2 2 2 2 10 16
G
15 G 17
2 5 2
C-H_13-12201536CP
CONN@
R2524
DC060005700
1 @ 2 0_0603_5% CRT_HSYNC_2
+HDMI_5V_OUT
U2502 R2525 CRT_CLK <30>
1 5 1 @ 2 0_0603_5% CRT_VSYNC_2
OE Vcc CRT_DATA <30>
R2526 1 1
0_0402_5%
2 @ 1 CRT_HSYNC 2 @ C2536 @ C2537
<30> HSYNC IN A 10P_0402_50V8J 10P_0402_50V8J
2 2
3 4 CRT_HSYNC_1
GND OUT Y
M74VHC1GT125DF2G_SC70-5
R2528 +HDMI_5V_OUT
0_0402_5% U2503
2 @ 1 1 5
OE Vcc
2 @ 1 CRT_VSYNC 2
<30> VSYNC IN A
R2529
0_0402_5%
3 4 CRT_VSYNC_1
GND OUT Y
M74VHC1GT125DF2G_SC70-5
3 3
4 4

CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
A B C D E
5 4 3 2 1
LAN-RTL8411B
+3VALW +3V_LAN
@
R2551 2 1 0_0805_5%
Using for Switch mode
The trace length from Lx to
60mil 60mil PIN48 (REGOUT) and from C to Lx
2 U2504 W=60mil must < 200mils. W=60mil
D 5 1 +LAN_VDD +3V_LAN D
IN OUT W=60mil
C2551 300mA 1.4A
1U_0402_6.3V6K 2 L2506
1 GND +REGOUT 1 2
4 3 2.2UH_HPC252012NF-2R2M_20%
EN OC
4.7U_0603_6.3V6K
C2538
0.1U_0402_16V7K
C2539
0.1U_0402_16V7K
C2540
0.1U_0402_16V7K
C2541
0.1U_0402_16V7K
C2542
0.1U_0402_16V7K
C2543
0.1U_0402_16V7K
C2544
1U_0402_6.3V6K
C2545
0.1U_0402_16V7K
C2546
4.7U_0603_6.3V6K
C2547
0.1U_0402_16V7K
C2548
0.1U_0402_16V7K
C2549
0.1U_0402_16V7K
C2550
LAN_PWR_EN SY6288C20AAC_SOT23-5 IDC=1200mA 1 1 1 1 1 1 1 1 1 1 1 1 1
<38> LAN_PWR_EN
From EC 2 2 2 2 2 2 2 2 2 2 2 2 2
High active. 11/27: P/N change to SH00000RT00

EN threshold voltage min:1.2V typ:1.6V max:2.0V ( S COIL 2.2UH +-20%
HPC252012NF-2R2M 1.3A)
Current limit threshold 1.5~2.8A Place near Pin 3,8,33,46 Place near Pin 20 Using for Switch mode Place near Pin 11,32,48
+3V_LAN Rising time must >0.5ms and <100ms The trace length
from C to
PIN46,47(VDDREG)
must < 200mils.
C C
reserve EC_PME# pull high 100K to +3VAL W_EC

+3VS PVT modify 01/06
+3V_LAN U2505 R2534, R2537, R2539, R2535, R2536
change to R-short
1
Power Manahement/Isolation
R2543 R2550 1 2 10K_0402_5% ISOLATEB 31
ISOLATEBPIN
1K_0402_5% <38> EC_PME# R2533 1 @ 2 0_0402_5% LAN_PME# 39
LANWAKEB Card Reader
DVT modify 12/04 15 SD_D0 R2534 1 @ 2 0_0402_5% SD_D0_R
SD_D0/MS_D1 SD_D0_R <33>
2
ISOLATEB for WOL pull high to +3V_LAN PCI-Express 14 SD_D1 R2537 1 @ 2 0_0402_5% SD_D1_R
23 SD_D1 16 SD_D1_R <33>
<9> CLK_PCIE_LAN
CLK_PCIE_LAN SD_CLK R2538 1 2 10_0402_5% SD_CLK_R
SD_CLK_R <33>
REFCLK_P SD_CLK/MS_D0
2
CLK_PCIE_LAN# 24 17 SD_CMD R2539 1 @ 2 0_0402_5% SD_CMD_R

<9> CLK_PCIE_LAN# REFCLK_N SD_CMD/MS_D2 SD_CMD_R <33>
R2544 18 SD_D3 R2535 1 @ 2 0_0402_5% SD_D3_R 2
30 SD_D3/MS_D3 19 SD_D3_R <33>
15K_0402_5% PLT_RST_BUF# SD_D2 R2536 1 @ 2 0_0402_5% SD_D2_R
<10,34> PLT_RST_BUF# PERSTBPIN SD_D2/MS_CLK SD_D2_R <33>
LAN_CLKREQ# 29 28 SD_WP C2554
<9> LAN_CLKREQ# CLKREQBPIN MS_BS/SD_WP# SD_WP <33>
5P_0402_50V8C
1
C2552 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P3 25 1

<12> PCIE_PRX_DTX_P3 HSOP XEMI@
C2553 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N3 26
<12> PCIE_PRX_DTX_N3 21 HSON 42 SD_CD#
<12> PCIE_PTX_C_DRX_P3 HSIP SD_CD# SD_CD# <33> close to pin17
22 43
<12> PCIE_PTX_C_DRX_N3 HSIN MS_CD#
Transceiver Interface
C2552, C2553 LAN_MIDI0+ 1
<33> LAN_MIDI0+ LAN_MIDI0- 2 MDIP0 +3V_LAN
Place near Pin 25,26 <33> LAN_MIDI0-
LAN_MIDI1+ 4 MDIN0
<33> LAN_MIDI1+ 5 MDIP1 48 1400mA
LAN_MIDI1-
<33> LAN_MIDI1-
LAN_MIDI2+ 6 MDIN1 HV_GIGA 11 Protect cotact Card contact
<33> LAN_MIDI2+ LAN_MIDI2- 7 MDIP2 HV_GIGA 12
Y2500
<33> LAN_MIDI2- 9 MDIN2 VDD33 32
25MHZ_10PF_7V25000014 LAN_MIDI3+
<33> LAN_MIDI3+
LAN_MIDI3- 10 MDIP3 VDD33 Write protect Write Enable
<33> LAN_MIDI3- MDIN3 +LAN_VDD
B XTLI 1
1 3
3 XTLO_R
PVT modify 01/16
(Lock) (Unlock) B
GND GND Add 0 ohm on XTL0 R2552 XTLI 44 33 300mA

1 1 CKXTAL1 VDD10 Card Uninsert Open Open Open
12P_0402_50V8J XTLO_R 1 @ 2 XTLO 45 Clock 3
12P_0402_50V8J 2 4 C2559 CKXTAL2 AVDD10 8
C2558 0_0402_5% AVDD10 Card insert Open Close Close
2 2 Regulator and Reference
+REGOUT 36 20
35 REG_OUT VDDTX
+3V_LAN VDDREG
SWR mode 34 800mA
46 ENSWREG 13
+LAN_VDD LV_GEN CARD_3V3 +CARD_3V3
R2542 2 1 2.49K_0402_1% LAN_RST 47
RSET 27 +VDD33_18
DV33/18
+3V_LAN 41
C2555
C2556
C2557
0.1U_0402_16V7K
4.7U_0603_6.3V6K
0.1U_0402_16V7K
1 2GPO 38 LED0
R2540 @ 1 1 1
<38> LAN_GPO 37 LED1/GPO LEDs
0_0402_5%
LED2
1
40
R2541 LED_CR 49 @
DVT modify 12/20 E_PAD 2 2 2
10K_0402_5%
for disable PHY
@ reserve 0 ohm
2
GPO
Place near Pin 27
RTL8411B-CGT_QFN48_6X6
A A

LAN RTL8411-CG

5 4 3 2 1
5 4 3 2 1
RJ45 / Card Reader conn.
D D
T2500
LAN_TERMAL1 24 JRJ45
LAN_MIDI0- 2 TCT1 MCT1 23 RJ45_MIDI0- RJ45_MIDI0+ 1
<32> LAN_MIDI0- TD1+ MX1+ PR1+
LAN_MIDI0+ 3 22 RJ45_MIDI0+
<32> LAN_MIDI0+ TD1- MX1- RJ45_MIDI0- 2
4 21 PR1-
LAN_MIDI1- 5 TCT2 MCT2 20 RJ45_MIDI1- RJ45_MIDI1+ 3
<32> LAN_MIDI1- TD2+ MX2+ PR2+
<32> LAN_MIDI1+ TD2- MX2- RJ45_MIDI2+ 4
7 18 PR3+
LAN_MIDI2- 8 TCT3 MCT3 17 RJ45_MIDI2- RJ45_MIDI2- 5
<32> LAN_MIDI2- TD3+ MX3+ PR3-
<32> LAN_MIDI2+ TD3- MX3- RJ45_MIDI1- 6
10 15 PR2-
LAN_MIDI3- 11 TCT4 MCT4 14 RJ45_MIDI3- RJ45_MIDI3+ 7 9
<32> LAN_MIDI3- TD4+ MX4+ PR4+ GND
LAN_MIDI3+ 12 13 RJ45_MIDI3+ 10
<32> LAN_MIDI3+ TD4- MX4- GND
RJ45_MIDI3- 8
PR4-
SANTA_130456-291
4
3
2
1
GST5009-E CONN@ 40mil
SP050006B10 75_0804_8P4R_1%
RP41
DC234008800 RJ45_GND 1 2 LANGND
1
C2560
C2561 40mil 10P_0402_50V8J
5
6
7
8
0.1U_0402_16V7K
2 LANGND
1
Place close to TCT pin @
C JUMP_43X118 C
J15 JP2500
B88069X9231T203_4P5X3P2-2
RJ45_GND XEMI@
D1
2
ESD@
MESC5V02BD03_SOT23-3
1
Card Reader Connector
JREAD1
SD_D3_R 1
<32> SD_D3_R CD/DAT3
+CARD_3V3 SD_CMD_R 2
<32> SD_CMD_R CMD
3
VSS1
Close to Card Reader CONN 4
VDD
5
4.7U_0603_6.3V6K
C2564
0.1U_0402_16V7K
C2565 <32> SD_CLK_R SD_CLK_R
CLK
1 1
6
VSS2
SD_D0_R 7
2 2 <32> SD_D0_R DAT0
SD_D1_R 8 12
<32> SD_D1_R DAT1 G1
SD_D2_R 9 13
B
<32> SD_D2_R DAT2 G2 B
SD_CD# 10 14
<32> SD_CD# CD G3
SD_WP 11 15
<32> SD_WP WP G4
TAITW_PSDAT4-11GLBS1NN4H2
CONN@
SP07000ZC00
R2610 XEMI@ C2608 XEMI@

0_0402_5% 10P_0402_50V8J
SD_CLK_R 1 2 1 2
Close to JREAD1 for EMI
A A

LAN RJ45/CR SD Connector

5 4 3 2 1
A B C D E
Wireless LAN
1 1
+3VALW +3VS_WLAN
U9 +3VS R2607 +3VS_WLAN

5 1
W=60mils
0_0805_5% 60mil
IN OUT 1 2
1U_0402_6.3V6K
C165
1 2 1 1 1
GND
NBYOC@ C458 C459 C460
@ 4 3 @ 0.1U_0402_16V7K
EN OC 4.7U_0603_6.3V6K 0.1U_0402_16V7K
2 SY6288C20AAC_SOT23-5 2 2 2
BYOC@
<38> WLAN_ON
NGFF Card E key module pin define

+3VS_WLAN
2 JNGFF1 2
1 2
USB20_P4 3 GND_1 3.3VAUX_2 4
<12> USB20_P4 5 USB_D+ 3.3VAUX_4 6
USB20_N4
<12> USB20_N4 7 USB_D- LED1# 8
9 GND_7 PCM_CLK 10
11 SDIO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_OUT 14
15 SDIO_DAT0 PCM_IN 16
17 SDIO_DAT1 LED2# 18
19 SDIO_DAT2 GND_18 20
21 SDIO_DAT3 UART_WAKE 22 UART_0_CRXD_DTXD
+3VS_WLAN 23 SDIO_WAKE UART_TX UART_0_CRXD_DTXD <11>
SDIO_RST
24 UART_0_CTXD_DRXD
UART_RX UART_0_CTXD_DRXD <11>
1
25 26
R429 PCIE_PTX_C_DRX_P4 27 GND_33 UART_RTS 28
<12> PCIE_PTX_C_DRX_P4 PET_RX_P0 UART_CTS
10K_0402_5% PCIE_PTX_C_DRX_N4 29 30 E51TXD_P80DATA_R R435 2 @ 1 0_0402_5%
<12> PCIE_PTX_C_DRX_N4 31 PET_RX_N0 CLink_RST 32 E51TXD_P80DATA<38>
E51RXD_P80CLK_R R436 2 @ 1 0_0402_5%
PCIE_PRX_DTX_P4 33 GND_39 CLink_DATA 34 E51RXD_P80CLK <38>
<12> PCIE_PRX_DTX_P4 PER_TX_P0 CLink_CLK
2
PCIE_PRX_DTX_N4 35 36
<12> PCIE_PRX_DTX_N4 PER_TX_N0 COEX3
37 38
WLAN_PME# CLK_PCIE_MINI1 39 GND_45 COEX2 40
<9> CLK_PCIE_MINI1 REFCLK_P0 COEX1
CLK_PCIE_MINI1# 41 42 SUSCLK_R R2612 2 @ 1 0_0402_5%
<9> CLK_PCIE_MINI1# 43 REFCLK_N0 SUSCLK(32KHz) 44 PLT_RST_BUF#_R R2613 2 1 0_0402_5% SUSCLK <10>
@
MINI1_CLKREQ# 45 GND_51 PERST0# 46 E51RXD_P80CLK PLT_RST_BUF# <10,32>
<9,10> MINI1_CLKREQ# CLKREQ0# W_DISABLE2#
WLAN_PME# 47 48 WL_OFF#
<38> WLAN_PME# PEWAKE0# W_DISABLE1# WL_OFF# <38>
49 50
GND_57 I2C_DAT
1
51 52
53 RSVD/PCIE_RX_P1 I2C_CLK 54
55 RSVD/PCIE_RX_N1 I2C_IRQ 56 R437
57 GND_63 RSVD_64 58 100K_0402_5%
3 59 RSVD/PCIE_TX_P1 RSVD_66 60 E51RXD_P80CLK 3
RSVD/PCIE_TX_N1 RSVD_68
2
61
63 GND_69 RSVD_70
62
64
multiplexed with
65 RSVD_71
RSVD_73
3.3VAUX_72
3.3VAUX_74
66 BT_ON function.
67
GND_75 68
69 GND1
GND2
BELLW_80152-3221
SP070013E00
CONN@
4 4

NGFF CARD (WLAN)
Size DocumentNumber
Custom

A B C D E
A B C D E
+5VS +VDDA Int. Speaker Conn.

HD Audio Codec 1
40mil 1
J1
JUMP_43X118
2 40mil
4.75V
SPKR+
SPKR-
SPKL+
EMI@ 1
EMI@ 1
EMI@ 1
L2511
L2512
L2513
2
2
2
PBY160808T-121Y-N_2P
PBY160808T-121Y-N_2P
PBY160808T-121Y-N_2P
40mil
SPK_R+
SPK_R-
SPK_L+
1
2
3
JSPK1
1
2 5
3 G1
XESD@ C2111 @ SPKL- EMI@ 1 L2514 2 PBY160808T-121Y-N_2P SPK_L- 4 6
4 G2
.1U_0402_16V7K
SM01000EJ00 3000ma 2 (output = 300 mA) ACES_88266-04001
2
220ohm@100m hz CONN@
+PVDD_HDA GND
+VDDA
DCR 0.04 GND SP02000K200
Place near Pin41 Place near Pin46 XESD@ XESD@
L2003 2 1 D2003 D2004
HCB2012KF-221T30_2P 1 1 1 TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1 C2112 C2113 C2114 1
40mil @
2 2 2 +AVDD1_HDA 20mil @ R2119 +VDDA GND GND
Place near Pin26 0_0603_5%
1 2
GND GND GND 1 1 1
0.1U_0402_16V7K
0.1U_0402_16V7K
10U_0603_6.3V6M
C2115 C2116 C2117
2
@
2
@
2
Digital Mic +3VS (MIC BOM upload by Audio Team)
C2137 1 2 0.1U_0402_16V7K
+3VS GND MIC2
C2138 1 2 10U_0603_6.3V6M +3VS 6 5 DMIC_DATA
MIC1 VDD DATA
Place near Pin 9
R2128 1 2 0_0402_5% +3VS_DVDDIO 6 5 DMIC_DATA_S 2 4 DMIC_CLK
VDD DATA R460 CS CLK
+3VS_DVDD
GNDA
2 4 DMIC_CLK 2 2DMIC@1 1 3
Place near Pin1
20mil Place near Pin40
CS CLK ENHANCE GND
2
R2124 1 2 0_0402_5% R2125 +1.5VS 1 3 0_0402_5% S MIC ST MP45DT02TR
+1.5VS_VDDA 1 2 ENHANCE GND
@ @
2
1 1 1 1 S MIC ST MP45DT02TR @ 2
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0_0402_5% @ @
.1U_0402_16V7K
C2141
C2118 C2119 C2121 C2122 @ R467 D2009
1
@ 10U_0603_6.3V6M 0_0402_5% TVNST52302AB0_SOT523-3
2 2 2 2 1
0_0402_5%
D2014 XESD@
41
46
26
40
1
1
R2611
U2012 TVNST52302AB0_SOT523-3
1
XESD@
DVDD-IO
DVDD
PVDD1
PVDD2
AVDD1
AVDD2
GND GND
1
GNDA
LINE1-L 22 43 SPKL-
LINE1-R 21 LINE1-L(PORT-C-L) SPK-OUT-L- 42 SPKL+
LINE1-R(PORT-C-R) SPK-OUT-L+
2 24 45 SPKR+ 2
23 LINE2-L(PORT-E-L) SPK-OUT-R+ 44 SPKR- HDA_BITCLK_AUDIO 1 XEMI@ 2 1 2 C2123 XEMI@
LINE2-R(PORT-E-R) SPK-OUT-R- GND
R2126 0_0402_5% 22P_0402_50V8J
+MICBIAS 31
+MICBIAS LINE1-VREFO-L
30 32 HP_LEFT
LINE1-VREFO-R HPOUT-L(PORT-I-L) 33 HP_RIGHT
RING2 17 HPOUT-R(PORT-I-R)
SLEEVE 18 MIC2-L(PORT-F-L)/RING
U2012
MIC2-R(PORT-F-R)/SLEEVE
SYNC
10 HDA_SYNC_AUDIO HDA_SYNC_AUDIO <8> Headphone out
DMIC_DATA 2 6 HDA_BITCLK_AUDIO
DMIC_CLK 3 GPIO0/DMIC-DATA BCLK 5 HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO <8> +MIC2_VREFO
GPIO1/DMIC-CLK SDATA-OUT HDA_SDOUT_AUDIO <8>
8 HDA_SDIN0_AUDIO 1 2
+3VS SDATA-IN HDA_SDIN0 <8>
255@ R2605 EC_MUTE# 47 R2127 33_0402_5% R2134 1 2 2.2K_0402_5% SLEEVE
PDB 48 1 2 2.2K_0402_5% SLEEVE <37>
100K_0402_1% R2133 RING2
2 1 HDA_RST_AUDIO# 11 SPDIF-OUT/GPIO2 RING2 <37>
ALC283-CG_MQFN48_6X6
RESETB 16
283@
SA000060500 255@ R2129 MONO_IN 12 MONO-OUT +MIC2_VREFO +MICBIAS
10mil PCBEEP D2006
200K_0402_1%
HP_PLUG# 2 1 SENSE_A 13 29 2
<37> HP_PLUG# HP/LINE1JD(JD1) MIC2-VREFO
14
R2132 2 283@ 1 20K_0402_1% 15 MIC2/LINE2JD(JD2) 1
R2129 SPDIFO/FRONTJD(JD3)/GPIO3 7 C2124 1 2 10U_0603_6.3V6M
1 LDO3-CAP GND
C2125 37 39 C2126 1 2 10U_0603_6.3V6M 3
35 CBP LDO2-CAP 27 1 2 10U_0603_6.3V6M
GNDA 2.2U_0402_6.3V6M C2127 GNDA
CBN LDO1-CAP
2
2 R2130 1 2 100K_0402_5% BAT54A-7-F_SOT23-3 R2145
36 28
10mil
+3VS_DVDD CODEC_VREF R2146 4.7K_0402_5%
39.2K_0402_1% CPVDD VREF 4.7K_0402_5%
283@ 1 1 1
1
1 2 0_0402_5% 20 HP_LEFT R2135 1 2 0_0603_5% HPOUT_L_1
2.2U_0402_6.3V6M
@
SD034392280 +3VALW R2131 @ HPOUT_L_1 <37>
VD33 STB
.1U_0402_16V7K
C2129
C2130
10U_0603_6.3V6M
C2131
10U_0603_6.3V6M2 1 C2128 19 34 CPVEE HP_RIGHT R2138 1 2 0_0603_5% HPOUT_R_1
3 GNDA MIC CAP CPVEE 2 2 2 HPOUT_R_1 <37> 3
1 LINE1-L C2135 1 2 4.7U_0603_6.3V6K

C2132
R468 2 283@ 1 0_0402_5% 4 25 2.2U_0402_6.3V6M LINE1-R C2136 1 2 4.7U_0603_6.3V6K
49 DC DET AVSS1 38
ThermalPAD AVSS2 2
Pin4
Place next pin27
ALC283 : DVSS ALC255-CG_MQFN48_6X6 +3VS +3VLP
ALC255/256 : DC DET (For Japen customer only) 255@ 255 involve this circuit already. +3VALW
RING2
SA000082700 (S IC ALC255-CG MQFN 48P CODEC) GND GNDA
2
Pin20 GND GNDA R2144
2
@ 283@
ALC283 : NC R2143 100K_0402_5%
2
ALC255/256 : Power for combo jack depop @ 100K_0402_5%
3
circuit at system shutdown mode R2142
1
@ R2137 100K_0402_5%
1
27K_0402_5%
2 1 BEEP#_R 1 2 MONO_IN 5
Pin15 <38> BEEP#
1
ALC283 : Ref. Resistor for Jack Detect
6
R2140 C2133 @ R2147 Q2003B 283@
2
ALC255/256 : Jack Detect for SPDIF-OUT and SPK-OUT port 27K_0402_5% 1 1U_0402_6.3V6K 10K_0402_5% L2N7002DW1T1G_SC88-6
4
2 1 2 1
<11> PCH_SPKR <38> EC_MUTE# 2
XEMI@ R2141 2 283@ 1 GNDA
2 <8> HDA_RST_AUDIO#
C2134 4.7K_0402_5% R2148
1
J11 J12 100P_0402_50V8J 10K_0402_5% Q2003A 283@
1
JUMP_43X39 JUMP_43X39 1 2 L2N7002DW1T1G_SC88-6
1 2 1 2
@ 1 2 @ 1 2 @ C2139 GNDA
1U_0402_6.3V6K
J9 J10 GND GNDA
JUMP_43X39 JUMP_43X39
4 1 2 1 2 4
@ 1 2 @ 1 2 To solve the background noise while combo jack
connecting to an active
J2 J3 speaker and system entry into S3/S4/S5 without analog
JUMP_43X39 JUMP_43X39 power
1 2 1 2
@ 1 2 @ 1 2
J4 J5
JUMP_43X39 JUMP_43X39
1 2 1 2 2014/09/16 2014/05/24 Title
Issued Date Deciphered Date
@ 1 2 @ 1 2
HD Audio Codec ALC255
GND GNDA GND GNDA Size DocumentNumber
Custom

A B C D E
A B C D E
SATA HDD1 Conn. SATA ODD Conn.

JHDD1
JODD1
HDD1@ 1
SATA_PTX_DRX_P0 C392 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 GND 1
<8> SATA_PTX_DRX_P0 A+ GND
<8> SATA_PTX_DRX_N0
SATA_PTX_DRX_N0 C393 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3
<8> SATA_PTX_DRX_P1 C401 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 2
1 4 A- C402 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 3 A+ 1
HDD1@ HDD1@ <8> SATA_PTX_DRX_N1
GND A-
SATA_PRX_DTX_N0 C391 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5 4
<8> SATA_PRX_DTX_N0 1 2 0.01U_0402_16V7K 6 B- GND
SATA_PRX_DTX_P0 C394 SATA_PRX_C_DTX_P0 C403 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 5
<8> SATA_PRX_DTX_P0 B+ <8> SATA_PRX_DTX_N1 B-
HDD1@ 7 C405 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 6
GND <8> SATA_PRX_DTX_P1 7 B+
GND
8 +5VS R218 +5VS_ODD
9 V33 8
0_0805_5% 80mils
10 V33 1 2 +5VS_ODD 9 DP
11 V33 10 +5V
GND 1 1 +5V
+5VS +5VS_HDD 12 11
10U_0603_6.3V6M
C404
0.1U_0402_16V7K
NBYOC@ ODD_MD
+5VS_HDD 13 GND 12 MD 14
C407
R49 1 @ 2 0_0805_5% +5VS_HDD 14 GND T185 @ 13 GND GND 15
15 V5 +5VS +5VS_ODD 2 2 GND GND
100mils 16 V5
17 V5
U66 SANTA_201501-2
G_SEN_INT2 18 GND 5 1
10U_0603_6.3V6M
C420
.1U_0402_16V7K
C397
1 1 <40> G_SEN_INT2 Reserved IN OUT CONN@

19 23
20 GND GND 24 2
HDD1@
@ 21 V12 GND GND SP01001MV00
2 2 22 V12 ODD_EN 4 3 ODD_OC# @ T187
V12 <38> ODD_EN EN OC
SY6288C20AAC_SOT23-5
SANTA_192602-1 BYOC@
CONN@
DC021409221
2 2
FFC type HDD w/o re-driver

SATA_PTX_DRX_P0 HDD3@ R2635 2 1 0_0402_5% SATA_PTX_C_DRX_P0_2 SATA_PTX_C_DRX_P0_2 C538 1 2 HDD3@ 0.01U_0402_16V7K RDSATA_PTX_C_DRX_P0
SATA_PTX_DRX_N0HDD3@ R2636 2 1 0_0402_5% SATA_PTX_C_DRX_N0_2 SATA_PTX_C_DRX_N0_2 C539 1 2 HDD3@ 0.01U_0402_16V7K RDSATA_PTX_C_DRX_N0
SATA_PRX_DTX_P0 HDD3@ R2637 2 1 0_0402_5% SATA_PRX_C_DTX_P0_2 SATA_PRX_C_DTX_P0_2 C541 1 2 HDD3@ 0.01U_0402_16V7K RDSATA_PRX_C_DTX_P0
SATA_PRX_DTX_N0HDD3@ R2638 2 1 0_0402_5% SATA_PRX_C_DTX_N0_2 SATA_PRX_C_DTX_N0_2 C540 1 2 HDD3@ 0.01U_0402_16V7K RDSATA_PRX_C_DTX_N0
3 3
SATA HDD2 Conn.

+3VS
FFC type HDD w/ re-driver +3VS
+5VS_HDD
1
0.01U_0402_16V7K
HDD2@
0.1U_0402_16V7K
1 1 HDD2@
R589 JHDD2
4.7K_0402_5% 1
2 5V
C410
C411
+3VS @ 2 2 5V
U2506 3
5V
2
7 10 4
R338 1 HDD2@ 2 4.7K_0402_5% APE0 EN VDD 20 RDSATA_PRX_DTX_P0 C537 1 2 HDD2@ 0.01U_0402_16V7K RDSATA_PRX_C_DTX_P0 5 GND
SATA_PTX_DRX_P0 HDD2@ C406 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P0_1 1 VDD RDSATA_PRX_DTX_N0 C536 1 2 HDD2@ 0.01U_0402_16V7K RDSATA_PRX_C_DTX_N0 6 RXP
A_INp RXN
R335 1 HDD2@ 2 4.7K_0402_5% BPE0 SATA_PTX_DRX_N0 HDD2@ C409 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N0_1 2 6 1 R660 2 HDD2@ 7
A_INn NC 16 GND
4.99K_0402_1% RDSATA_PTX_DRX_N0 C535 1 2 HDD2@ 0.01U_0402_16V7K RDSATA_PTX_C_DRX_N0 8
R332 1 @ 2 4.7K_0402_5% APE1 SATA_PRX_DTX_P0 HDD2@ C399 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_P0_1 5 NC RDSATA_PTX_DRX_P0 C534 1 2 HDD2@ 0.01U_0402_16V7K RDSATA_PTX_C_DRX_P0 9 TXN
SATA_PRX_DTX_N0 HDD2@ C400 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_N0_1 4 B_OUTp 9 APE0 10 TXP
R337 1 @ 2 4.7K_0402_5% BPE1 B_OUTn A_PRE0 8 BPE0 GND
APE1 19 B_PRE0
A_PRE1
R334 1 @ 2 4.7K_0402_5% TEST BPE1 17 15 RDSATA_PTX_DRX_P0 11
B_PRE1 A_OUTp 14 RDSATA_PTX_DRX_N0 12 GND
TEST 18 A_OUTn +5VS_HDD GND
TEST
R586 1 @ 2 4.7K_0402_5% APE0 3 11 RDSATA_PRX_DTX_P0
13 GND B_INp 12 RDSATA_PRX_DTX_N0 ACES_51625-01001-001
GND B_INn 100mils
R339 1 @ 2 4.7K_0402_5% BPE0 21 CONN@
EPAD
R588 1 HDD2@ 2 4.7K_0402_5% APE1 PS8527CTQFN20GTR2A_TQFN20_4X4 1 1
DC021407091
2
HDD2@
R587 1 HDD2@ 2 4.7K_0402_5% BPE1 @ R658 R659 HDD2@ C421 C412 HDD2@
0_0402_5% 4.7K_0402_5% USE 8527 re-driver 10U_0603_6.3V6M .1U_0402_16V7K
4 R351 1 HDD2@ 2 4.7K_0402_5% TEST HDD2@ 2 2 4
for 8520 use SA00007JU00
1

HDD/ODD/ HDD Re-Driver

A B C D E
A B C D E
USB3.0 (Port 1) R2618 1 @ 2 0_0402_5%

For ESD request
R2619 1 @ 2 0_0402_5%
D15 W=60mils
U3RXDN1 1 1 10 9 U3RXDN1 +5VALW
L24 XEMI@ +USB3_VCCA
2 1 PCH_USB3_TX1_N_C 2 1 U3TXDN1 U3RXDP1 2 2 9 8 U3RXDP1
<12> PCH_USB3_TX1_N 2 1
C482 .1U_0402_16V7K U25
U3TXDN1 4 4 7 7 U3TXDN1 5 1
2 1 PCH_USB3_TX1_P_C 3 4 U3TXDP1 IN OUT
<12> PCH_USB3_TX1_P 3 4
C484 .1U_0402_16V7K U3TXDP1 5 5 6 6 U3TXDP1 2 R454 @
1 GND 1
DLW21HN900HQ2L_4P 0_0402_5%
3 3 USB_EN 4 3 1 2
<38> USB_EN EN OC USB_OC0# <11,12>
R2620 1 @ 2 0_0402_5% 2
8 SY6288C20AAC_SOT23-5
R2621 1 @ 2 0_0402_5% C483
L05ESDL5V0NA-4_SLP2510P8-10-9 0.1U_0402_16V7K
ESD@ 1
EMI@
L25 XEMI@
PCH_USB3_RX1_N 2 1 U3RXDN1
<12> PCH_USB3_RX1_N 2 1
D2012 +USB3_VCCA
PCH_USB3_RX1_P 3 4 U3RXDP1 6 3 U2DP0_L
<12> PCH_USB3_RX1_P 3 4 I/O4 I/O2
W=100mils SF000006R00
DLW21HN900HQ2L_4P +USB3_VCCA
220U 6.3V OSCON
1
5
VDD GND
2 1 ESR 17mohm@100Khz
+
0.1U_0402_16V7K
C487
C486
150U_6.3V_M_D2
R458 1 XEMI@ 2 0_0402_5%
R461 1 XEMI@ 2 0_0402_5%

4
I/O3 I/O1
1 U2DN0_L 2 2
USB3.0 Conn.
AZC099-04S.R7G_SOT23-6
L26 EMI@ ESD@ JUSB1
USB20_P0 2 1 U2DP0_L 1
<12> USB20_P0 2 1 2 VBUS
U2DN0_L
U2DP0_L 3 D-
USB20_N0 3 4 U2DN0_L 4 D+
<12> USB20_N0 3 4 U3RXDN1 5 GND
DLW21HN900HQ2L_4P U3RXDP1 6 StdA-SSRX- 10
7 StdA-SSRX+ GND 11
U3TXDN1 8 GND-DRAIN GND 12
U3TXDP1 9 StdA-SSTX- GND 13
2 StdA-SSTX+ GND 2
SINGA_2UB4037-000101F
CONN@
DC23300AK00
USB3.0 (Port2) R2622
R2623
1
1
@
@
2 0_0402_5%
2 0_0402_5%
For ESD request
U3RXDN2
D16
1 1 10 9 U3RXDN2 +5VALW
W=60mils
+USB3_VCCB
U3RXDP2 2 2 9 8 U3RXDP2
L28 XEMI@ U26
2 1 PCH_USB3_TX2_N_C 2 1 U3TXDN2 U3TXDN2 4 4 7 7 U3TXDN2 5 1
<12> PCH_USB3_TX2_N 2 1 IN OUT
C488 0.1U_0402_16V7K
U3TXDP2 5 5 6 6 U3TXDP2 2 @ R466
2 1 PCH_USB3_TX2_P_C 3 4 U3TXDP2 GND 0_0402_5%
<12> PCH_USB3_TX2_P 3 4
C485 0.1U_0402_16V7K 3 3 4 3 1 2
<38> USB_CHARGE_2A EN OC USB_OC1# <11,12>
DLW21HN900HQ2L_4P 2
8 SY6288C20AAC_SOT23-5
C491
R2624 1 @ 2 0_0402_5% L05ESDL5V0NA-4_SLP2510P8-10-9 0.1U_0402_16V7K
ESD@ 1
EMI@
R2625 1 @ 2 0_0402_5%
D2013
3 L30 XEMI@
6
I/O4 I/O2
3 U2DP1_L
USB/B (USB 2.0 + AUDIO) 3
PCH_USB3_RX2_N 2 1 U3RXDN2 +USB3_VCCB
<12> PCH_USB3_RX2_N 2 1
5 2
+USB3_VCCB Need check Audio Pin Sequence
VDD GND W=100mils
PCH_USB3_RX2_P 3 4 U3RXDP2 SF000006R00 JUSB3
<12> PCH_USB3_RX2_P 3 4 HPOUT_L_1 1
DLW21HN900HQ2L_4P 220U 6.3V OSCON <35> HPOUT_L_1
HPOUT_R_1 2 1
1 <35> HPOUT_R_1 2
4
I/O3 I/O1
1 U2DN1_L 1 ESR 17mohm@100Khz <35> SLEEVE
SLEEVE 3
3
+ 4
C2609
0.1U_0402_16V7K
C490 RING2
<35> RING2 4
AZC099-04S.R7G_SOT23-6 150U_6.3V_M_D2 HP_PLUG# 5
<35> HP_PLUG# 5
ESD@ 6
R464 1 XEMI@ 2 0_0402_5%

2 2
USB3.0 Conn. GNDA
7
8
6
7
R465 1 XEMI@ 2 0_0402_5% USB Host Charger 1

JUSB2
<12> USB20_P2
<12> USB20_N2
USB20_P2
USB20_N2
USB_EN
9
10
11
8
9
10
CB SELCDP VBUS 11
L29 EMI@ U2DN1_L 2 12
U2DP1 2 1 U2DP1_L U2DP1_L 3 D- 13 12 15
2 1 0 X DCP(Dedicated Charging Port) D+ 13 GND
autodetect with mouse/keyboard wakeup 4 14 16
GND +5VALW 14 GND
U3RXDN2 5
U2DN1 3 4 U2DN1_L U3RXDP2 6 StdA-SSRX- 10 ACES_51524-0140N-001
3 4 1 0 S0 charging with SDP(Standard Downstream Port) only StdA-SSRX+ GND
7 11 CONN@
U3TXDN2 8 GND-DRAIN GND 12
DLW21HN900HQ2L_4P 1 1 S0 charging with CDP(Charging Downstream Port) or
U3TXDP2 9 StdA-SSTX- GND 13
SDP only StdA-SSTX+ GND SP010021H00
SINGA_2UB4037-000101F
+3VLP CONN@
DC23300AK00
1
R853
10K_0402_5%
4 R854 @ 4
0_0402_5% U77
2
1 2 8 1 USB_CEN
<38> USB_CHARGE_CB CB CEN USB_CEN <38>
USB20_N1 7 2 U2DN1
<12> USB20_N1 USB20_P1 6 TDM DM 3 U2DP1
<12> USB20_P1 5 TDP DP 4
+5VALW R857 1 2
+5VALW
VddSMART-CDP 9 10K_0402_5%
1 Thermal-Pad
C966 SLG55594AVTR_TDFN8_2X2
0.1U_0402_16V7K Issued Date 2014/09/16 Deciphered Date 2014/05/24 Title
2
USB3.0 Conn/USB_B/PWR_B

A B C D E
A B C D E
XEMI@ C501 XEMI@ R477 SM010030010 200ma 120ohm@100mhz DCR 0.2

22P_0402_50V8J 33_0402_5%
2 1 2 1 CLK_PCI_LPC +3VLP @ R236 +3VALW_EC L31 +EC_VCCA
0_0805_5% BLM15BD121SN1D_2P
1 2 1 2 +EC_VCCA
1
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1 1 1 @ 2 XEMI@
1 1
C502
C503
C505
C506 C508
1000P_0402_50V7K .1U_0402_16V7K
2
ECAGND
ESD@
C509 2 1 .1U_0402_16V7K EC_RST# 2 2 2 1
ECAGND <43>
125
111
22
33
96
67
U28
9
9022: ECRST# is internally pull-up to VCC via 40Kohm resistor,
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
so can remove external pull-up resistor and capacitor.
1 21 VCCST_PG_EC
EC_KBRST# 2 GATEA20/GPIO00 GPIO0F 23 BEEP# VCCST_PG_EC <10,13>
<11> EC_KBRST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 BEEP# <35> +3VALW_EC
SERIRQ
+3VALW_EC <11,39> SERIRQ LPC_FRAME# 4 SERIRQ GPIO12 27 EC_RTCRST#
<9,39> LPC_FRAME# LPC_AD3 5 LPC_FRAME# ACOFF/GPIO13 EC_RTCRST# <8> LID_SW# 1 2 100K_0402_5%
R476
<9,39> LPC_AD3 7 LPC_AD3
LPC_AD2 PWM Output C510 2 1 100P_0402_50V8J ECAGND
1 2 100K_0402_5% <9,39> LPC_AD2 8 LPC_AD2 63
R484 @ EC_PME# LPC_AD1 BATT_TEMP
<9,39> LPC_AD1 LPC_AD0 10 LPC_AD1 BATT_TEMP/GPIO38 64 VCIN1_BATT_DROP BATT_TEMP<43>
<9,39> LPC_AD0 LPC & MISC
LPC_AD0 GPIO39 VCIN1_BATT_DROP <43>
65 ADP_I
1 ADP_I/GPIO3A ADP_I <43,44> +3VS
R2614 V3@ 2 100K_0402_5% SEN_DET# CLK_PCI_LPC 12 AD Input 66 AD_BID0
<9> CLK_PCI_LPC PLT_RST# 13 CLK_PCI_EC GPIO3B 75 WLAN_PME#
<10,19,39> PLT_RST# PCIRST#/GPIO05 GPIO42 WLAN_PME# <34>
R2615 1 V3@ 2 100K_0402_5% LID_SW2# EC_RST# 37 76 EC_PME#
<40> EC_RST# 20 EC_RST# IMON/GPIO43 EC_PME# <32> 1 2 10K_0402_5%
EC_SMI#_SCI# EC_MUTE# R481 @
<11> EC_SMI#_SCI# 38 EC_SCII#/GPIO0E 1 2 10K_0402_5%
WLAN_ON EC_LID_OUT# R482 @
<34> WLAN_ON GPIO1D 68 LAN_PWR_EN
DAC_BRIG/GPIO3C 70 EN_DFAN1 LAN_PWR_EN <32> GPU_ALERT 1 2 10K_0402_5%
Reserve for 15" V3 R486
EN_DFAN1/GPIO3D 71 TP_EN EN_DFAN1 <40> GPU_OVERT 1 2 10K_0402_5%
DA Output R487
55 IREF/GPIO3E 72 TP_EN <39>
KSI0 KBL_EN
56 KSI0/GPIO30 CHGVADJ/GPIO3F KBL_EN <39>
KSI1
+3VALW_EC RP12 KSI2 57 KSI1/GPIO31 9012_PECI R497 1 2 43_0402_1%
2 58 KSI2/GPIO32 83 H_PECI <6> 2
KSI3 EC_MUTE#
1 8 EC_SMB_CK1 KSI4 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 USB_EN EC_MUTE# <35>
2 7 EC_SMB_DA1 KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 USB_CEN USB_EN <37>
3 6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 USB_CEN <37>
EC_SMB_CK2 KSI6 PS2 Interface USB_CHARGE_CB
4 5 EC_SMB_DA2 KSI7 62 KSI6/GPIO36 EAPD/GPIO4D 87 TP_CLK USB_CHARGE_CB <37>
+3VS KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <39>
KSO0 39 88 TP_DATA
KSI[0..7] KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <39>
2.2K_0804_8P4R_5%
<39> KSI[0..7] KSO1/GPIO21
KSO2 41 R691 2 1 100K_0402_5%
KSO[0..17] KSO3 42 KSO2/GPIO22 97 ENBKL
<39> KSO[0..17] KSO4 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 TP_PW R_EN ENBKL <10>
1 2 0.01U_0402_16V7K PLT_RST# KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 HDA_SDO TP_PWR_EN <39>
KSO5/GPIO25 Int. K/B
C511
45 HDA_SDO/GPXIOA02 109 HDA_SDO <8> 1 2 0_0402_5%
ESD@ KSO6 VCIN0_PH R509 @
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <43> ACIN <10,44>
ESD request KSO7/GPIO27 SPI Device Interface
KSO8 47 Reserve for Share ROM EC
KSO9 48 KSO8/GPIO28 119 EC_SPI_SI EC_ACIN 2 1 100P_0402_50V8J
EC_SPI_SI <9> C512
KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SPI_SO
KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_SO <9>
R616 1 2 100K_0402_5% I2C_TS_RST# KSO11 50 SPI Flash ROM 126 EC_SPI_CLK
EC_SPI_CLK <9>
KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128 EC_SPI_CS#
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS# <9>
KSO13 52
KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73 GPU_ALERT
KSO16 81 KSO15/GPIO2F ENBKL/GPIO40 74 GPU_OVERT GPU_ALERT <19>
82 KSO16/GPIO48 PECI_KB930/GPIO41 89 GPU_OVERT <19>
For abnormal shutdown KSO17 BATT_4S EC_RTCRST# R490 1 2 10K_0402_5%
KSO17/GPIO49 FSTCHG/GPIO50 BATT_4S <44>
90 BATT_BLUE_LED#
BATT_CHG_LED#/GPIO52 91 ODD_EN BATT_BLUE_LED# <39>
D25
EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 PWR_LED ODD_EN <36>
RB751V-40SOD-323
<43,44> EC_SMB_CK1 EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54 PWR_LED <39> @ R499
SPOK 1 2 PCH_RSMRST# EC_SMB_DA1 78 93 BATT_AMB_LED# 0_0402_5%
<43,44> EC_SMB_DA1 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 BATT_AMB_LED# <39>
EC_SMB_CK2 SM Bus SYSON H_PROCHOT#_EC 1 2
<9,19,30> EC_SMB_CK2 80 EC_SMB_CK2/GPIO46 SYSON/GPIO56 121 SYSON <41,46>
D26 EC_SMB_DA2 EC_TP_INT#
<9,19,30> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 USB_CHARGE_2A EC_TP_INT# <10,39>
RB751V-40SOD-323 @ R496
PM_SLP_S4#/GPIO59 USB_CHARGE_2A <37>
@ 1 2 PCH_PWROK 0_0402_5%
1 2 H_PROCHOT# <6,19>
<49> VR_HOT#
3 PM_SLP_S3# 6 100 PCH_RSMRST# 3
<10> PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 PCH_RSMRST# <10>
PM_SLP_S5# EC_LID_OUT#
<10> PM_SLP_S5# SEN_DET# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 VCIN1_PROCHOT EC_LID_OUT# <11>
<39> SEN_DET# I2C_TS_RST# 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 H_PROCHOT#_EC VCIN1_PROCHOT <43>
<28> I2C_TS_RST# TS_EN 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 MAINPWON
+3VALW_EC <28> TS_EN WL_OFF# 18 GPIO0B VCOUT0_PH/GPXIOA07 105 BKOFF# MAINPWON <40,43,45>
<34> WL_OFF# GPIO0C GPO BKOFF#/GPXIOA08 BKOFF# <28>
LID_SW2# 19 GPIO 106 LAN_GPO
Board ID <39> LID_SW2#
<45> SPOK
SPOK 25 GPIO0D
EC_INVT_PWM/GPIO11
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
107 3V_EN_R LAN_GPO <32> For thermal protect shutdown
2
Analog Board ID definition, FAN_SPEED1 28 108 VCCST_PWRGD

<40> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 VCCST_PWRGD <13,47>
R503 29 D2016
100K_0402_5%
Please see page 3. E51TXD_P80DATA 30 EC_PME#/GPIO15 RB751V-40_SOD323-2
Ra <34> E51TXD_P80DATA EC_TX/GPIO16
E51RXD_P80CLK 31 110 EC_ACIN MAINPWON 1 2 3V_EN
<34> E51RXD_P80CLK PCH_PWROK 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 EC_ON 3V_EN <45>
<10> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <45>
1
AD_BID0 PWR_SUSP_LED# 34 114 ON/OFFBTN# R2626

<39> PWR_SUSP_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFFBTN# <39>
36 GPI 115 LID_SW# 3V_EN_R 1 2 R2627 1 2
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <39>
1
1 116 SUSP# 1M_0402_5%

SUSP#/GPXIOD05 117 SUSP# <41,44,46,47,48>
R506 DGPU_AC_DETECT 1K_0402_5%
15K_0402_5% C517 @ GPXIOD06 118 9012_PECI DGPU_AC_DETECT <11,19>
Rb PECI_KB9012/GPXIOD07
.1U_0402_16V7K PBTN_OUT# 122
AGND/AGND
2 <10> PBTN_OUT# PM_SLP_S4# 123 XCLKI/GPIO5D 124

GND/GND
GND/GND
GND/GND
GND/GND
<10> PM_SLP_S4# XCLKO/GPIO5E V18R +3VALW_EC

2
GND0
KB9022QC-A3_LQFP128_14X14
24
35
94
69
11
113
20mil L32
BLM15BD121SN1D_2P
ECAGND 1 2
SM010030010 200ma 120ohm@100mhz DCR 0.2

4 4

EC ENE-KB9022

A B C D E
A B C D E
JKB1 +3V_PTP
KB Conn. 30
29
28
GND2
GND1 Touch pad
+3VALW
U2507 +3VS +3VALW

+3V_PTP
ON/OFFBTN# 27 28 5 1
4.7U_0603_6.3V6K
KSO0 26 27 IN OUT R462 1 @ 2 0_0402_5%
26 2 1
KSO1 25 2
C2563
KSO2 24 25 GND
C2562
KSO3 23 24 4 3
1U_0402_6.3V6K
KSO4 22 23 KSI[0..7] 1 EN OC 2 R463 1 2 0_0402_5%
@
22 KSI[0..7] <38>
KSO5 21 SY6288C20AAC_SOT23-5
KSO6 20 21 KSO[0..17]
KSO7 19 20 KSO[0..17] <38>
19 <38> TP_PW R_EN TP_PWR_EN follow SYSON
KSO8 18
KSO9 17 18 behavior +3V_PTP +3V_PTP
1 KSO10 16 17 +3V_PTP 1
KSO11 15 16
15
2
KSO12 14 1
KSO13 13 14
13
1
KSO14 12 R2507 R2509 R633 C663 @
KSO15 11 12 4.7K_0402_5% 4.7K_0402_5% 10K_0402_5% .1U_0402_16V7K
KSO16 10 11 2
10
1
KSO17 9 R456 @ EC_TP_INT#
KSI0 8 9
0_0402_5% JTP1
8
2
KSI1 7 2 1 PS2_CLK_TP 1
6 7 <38> TP_CLK 2 1
KSI2 PS2_CLK_TP
KSI3 5 6 EC PS2 2 1 PS2_DATA_TP PS2_DATA_TP 3 2
KSI4 4 5 <38> TP_DATA EC PS2 4 3
KSI5 3 4 R457 @ PCH_I2C1_R_SDA 5 4
KSI6 2 3 0_0402_5% +3V_PTP PCH_I2C1_R_SCL 6 5
KSI7 1 2 PCH I2C EC_TP_INT# 7 6
1 <10,38> EC_TP_INT# TP_EN 8 7
+3VS <38> TP_EN 8
ACES_85201-2805 9
GND
1
CONN@ R2639 R2640 10
2.2K_0402_5% 2.2K_0402_5% GND
SP01000GO00 CONN@
2
Q2008A ACES_51524-00801-001
SP01001A910
2
KB BackLight <11> PCH_I2C1_SCL
1 6 PCH_I2C1_R_SCL
JBL1
6 1 @ 2
+5VS 5 GND R2641 0_0402_5%
GND
5
U2601
5 1 +5VS_BL 4 Q2008B
2 IN OUT 3 4 2
2 2 3 SP010022M00 L2N7002DW1T1G_SC88-6
4 3 PCH_I2C1_R_SDA
GND 1 2 <11> PCH_I2C1_SDA
4 3 1
<38> KBL_EN EN OC ACES_51524-0040N-001
SY6288C20AAC_SOT23-5 1 CONN@ 1 @ 2
KBL@ R2642 0_0402_5%
C524
0.1U_0603_25V7K
2
@
ON/OFF BTN +3VLP

Lid Switch Lid Switch 2 (reserve for 15")
+3VLP
JLID1
TPM
2
1
R534 +3VLP LID_SW2# 2 1
<38> LID_SW2# 2
100K_0402_5% U4 SEN_DET# 3
3 <38> SEN_DET# 4 3
SW6 @
OUT LID_SW# <38> 4
EVQPLDA15_4P 2 5
VDD 5
1
1 3 1 1 BATT_AMB_LED# 6
ON/OFFBTN# <38> GND 6
BOT BATT_BLUE_LED# 7
+3VALW +3VALW_TPM +3VS +3VS_TPM 2 4 PWR_SUSP_LED# 8 7
R2600 R2601 C62
+3VALW PWR_LED# 9 8
0_0603_5% 0_0603_5% .1U_0402_16V7K
1 2 1 2 2 YB8251ST23_TSOT-23-3 10 9
10
6
5
10U_0603_6.3V6M
0.1U_0402_16V7K
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
C2600 TPM@
C2601 TPM@
C2602 TPM@
C2603 TPM@
C2604 TPM@
C2605 TPM@
1 1 1 1 1 1 Test Only 11
SA00008K800, S IC APX8132AI-TRG SOT -23 3P HALL SENSOR GND1
12
SN100000K00 GND2
3 2 2 near pin5 2 2 2 2 3
ACES_50506-01041-P01
CONN@
SP01001FR00
near pin10, 19, 24
U2600
5
LED
VSB +3VALW_TPM
1 10
GPIO0/XOR_OUT VDD +3VS_TPM
2 19 LED6
GPIO3/BADD with Internal PH (default) 6 GPIO1 VDD 24
0_0402_5% 1 @ 2 R2602 TPM_BADD 9 GPIO2/GPX VDD BATT_AMB_LED# 2 1 3
O
GPIO3/BADD <38> BATT_AMB_LED# +3VALW
CLKRUN# 15 8 R699 560_0402_1%
<10> CLKRUN# GPIO4/CLKRUN# TEST
CLKRUN PH 10K to +3VS at PCH side LPC_AD0 26 BATT_BLUE_LED# 2 1 2 1
<9,38> LPC_AD0 LAD0/MISO <38> BATT_BLUE_LED#
23
B
LPC_AD1 R698 430_0402_1%
<9,38> LPC_AD1 LPC_AD2 20 LAD1/MOSI 3
<9,38> LPC_AD2 LPC_AD3 17 LAD2/SPI_IRQ# NC 12 LTST-S115KFTBKT-CA_AMBER-BLUE
<9,38> LPC_AD3 LAD3 NC 13 PWR_LED#
LPCPD# had internal PH NC 14
28 NC 1 D
Q17
CLK_PCI_TPM 21 LPCPD# 2
<38> PWR_LED L2N7002LT1G_SOT23-3 LED7
<9> CLK_PCI_TPM LCLK/SCLK
LPC_FRAME# 22 G
<9,38> LPC_FRAME# LRFAME#/SCS#
1
16 4 2 1 3
O
PLT_RST# S <38> PWR_SUSP_LED# PWR_SUSP_LED#
<10,19,38> PLT_RST# LRSET#/SPI_RST# GND
3
SERIRQ 27 11 R535 R700 560_0402_1% +3VALW

<11,38> SERIRQ 7 SERIRQ GND 18
SERIRQ PH 10K to +3VS at PCH side 100K_0402_5%
PP GND 25 PWR_LED# 2 1 2 1
GND R701 430_0402_1%
B
avoid flash issue when
2
NPCT650AA0WX_TSSOP28 abnormall shutdown LTST-S115KFTBKT-CA_AMBER-BLUE

4 TPM@ 4
BADD SELECTION
SA00007IO00
0 EEh - EFh
1 7Eh - 7Fh
*
CLK_PCI_TPM R2603 1 2 33_0402_5% C2606 1 2 22P_0402_50V8J
XEMI@ XEMI@
KB & TP & TPM Connector & LED
Size DocumentNumber
Custom

A B C D E
FAN1 Conn Screw Hole
+5VS C632
4.7U_0603_10V6K H17
1 2 H3 H4 H5 H6 H9 H10 H11 H21 H_3P3 FD1 FD2
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P3
U31 @ @
1
1 8
EN GND
1
2 7 FIDUCIAL_C40M80 FIDUCIAL_C40M80
+VCC_FAN1 3 VIN GND 6
2 @ 1 4 VOUT GND 5 FD3 FD4
<38> EN_DFAN1 VSET GND @ @ @ @ @ @ @ @ @
R515 1 NCT3942S SOP 8P
0_0402_5% H13 H14 H15 H16 H20 H22 H24 @ @
1
@ C626 H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H_3P0 H_3P0
.1U_0402_16V7K FIDUCIAL_C40M80 FIDUCIAL_C40M80
2
1
C627
4.7U_0603_10V6K @ @ @ @ @ @ @
+3VS 1 2
@ C631
1
1000P_0402_50V7K
R516 1 2
10K_0402_5%
40mil
JFAN1
2
+VCC_FAN1 1
2 1 4
<38> FAN_SPEED1 3 2 GND 5 H12 H18
3 GND H_3P7X3P2N H_6P0N
2
H23 H25 H_3P7X3P2N H_6P0N
C2610 ACES_88231-03041 H_3P5X3P0N H_3P0N
1000P_0402_50V7K CONN@
1
XEMI@ SP020020710 @ @ @ @
1
Reset Circuit
G-Sensor +3VLP
R2632 1 @
R2631
2 0_0402_5%
MAINPWON <38,43,45>
0_0402_5%
1 2
EC_RST# <38>
2
R2606
10K_0402_5%
6
1
+3VS
BI_GATE PH to +RTCVCC at PWR side BI_GATE# 2
1
1 Q2004A
3
R518 +3VS L2N7002DW1T1G_SC88-6
1
10K_0402_5% C2607
GSEN@ U5 GSEN@ .1U_0402_16V7K
1 C633 1 2 10U_0603_6.3V6M BI_GATE 5 2
Vdd_IO
2
8 GSEN@ <43> BI_GATE

4 CS 14 C628 1 2 0.1U_0402_16V4Z
<9,17,18> D_CK_SCLK SCLSPC Vdd
<9,17,18> D_CK_SDATA 6 Q2004B
SDA/SDI/SDO
4
7 L2N7002DW1T1G_SC88-6
R519 1 @ 2 10K_0402_5% SDO/SA0 11 G_SEN_INT
+3VS INT1 G_SEN_INT <10>
R520 1 GSEN@ 2 10K_0402_5% 16 9 G_SEN_INT2_R 1 2
ADC1 INT2 G_SEN_INT2 <36>
15
13 ADC2 10 @ R2630
ADC3 RES 0_0402_5%
2
3 NC 5
NC GND 12
GND BI SW
LIS3DHTR_LGA16_3X3
GSEN@ SW4
Reset Button 1
1 BI_GATE
LIS3DH
SA0 ->0, Address is 0011 000 (0x30h) Reset Button
SA0 ->1, Address is 0011 001 (0x32h) 2
2
SW5 3
3
1 2 BI_GATE 4
GND 5
1-2 : Power Off
GND 6 2-3 : Power ON
SKPMAME010_2P GND 7
GND
MSS312-Q-T-R(913)_3P

FAN & Screw Hole & Reset
Size DocumentNumber
Custom

A B C D E
DC & VGA Interface

U11 @ J36 For ESD
1 14 +5VS_OUT 1 2
+5VALW VIN1 VOUT1 1 2 +5VS +5VS +3VALW_PCH +CPU_CORE +1.05VS_VTT
@ R926 2 13
0_0402_5% VIN1 VOUT1 C976 JUMP_43X118
2 1 5VS_ON 3 12 2 1 330P_0402_50V7K
ON1 CT1 1 2
R927 +5VALW
4 11
47K_0402_5% VBIAS GND C967
1 1 XEMI@ 1 XEMI@ 1 XEMI@ XEMI@ C93
1
SUSP# 2 1 3VS_ON 5 10 2 1 330P_0402_50V7K 22U_0603_6.3V6M
ON2 CT2
22U_0603_6.3V6M
C39
22U_0603_6.3V6M
C64
10U_0603_6.3V6M
C92
1 2 6 9 @ J37
+3VALW VIN2 VOUT2 2 2 2
7 8 +3VS_OUT 1 2
VIN2 VOUT2 1 2 +3VS
C980
.1U_0402_16V7K 15 JUMP_43X118
GPAD
EM5209VF_DFN14_3X2
+5VALW
+1.35V +5VALW
2
+0.675VS +1.05VS_VTT
2
R552
2
100K_0402_5% R573 R554
1
@ 470_0603_5% 100K_0402_5%
R566 R567 @ @
1
470_0603_5% 470_0603_5%
1
SUSP @
@
1
+1.35V_R SYSON#
2
+0.675VS_R +1.05VS_VTT_R
3
1
@ D
D D
1
2
<38,44,46,47,48> SUSP#
G SUSP 2 2 SUSP SYSON# 2 5 SYSON
SYSON <38,46>
1
S G G
3
R555 Q29 Q36 S S Q37
3
10K_0402_5% L2N7002LT1G_SOT23-3 L2N7002LT1G_SOT23-3 L2N7002LT1G_SOT23-3
4
@ @ @ @ Q40A @ Q40B
2 L2N7002DW1T1G_SC88-6 L2N7002DW1T1G_SC88-6 2
+1.05VS_VTT to +1.05VSDGPU
160mil
+1.05VS_VTT +1.05VSDGPU +VGA_CORE
R469 U40
AO4478L_SO8
2
8 1
7 2 R572
+3VS to +3VSDGPU_AON for GPU
10U_0603_6.3V6M
C613
1 6 3 47_0603_5%
10U_0603_6.3V6M
C617
0.1U_0603_25V7K
C683
5 1 1 @
1
200K_0402_5% VGA@ VGA@ +VGA_CORE_R
1
+3VS +3VSDGPU_AON SGT@ VGA@ VGA@ VGA@ R514
4
2
U12 100mil(1.5A) SD028200380 47_0402_5% L2N7002LT1G_SOT23-3
1
5 1 2 2 @ D
IN OUT DGPU_PWR_EN# 2
2
2
C620 2 2 +1.05VSDGPU_R G
4.7U_0603_6.3V6K GND VGM@ R469
10mil S
3
3
VGA@ 4 3 C621 470K_0402_5% Q35
3
1 EN OC VGA@
10mil 1 2 1.05VSDGPU_GATE
3
1 4.7U_0603_6.3V6K +19VB
SY6288C20AAC_SOT23-5
VGA@ 1 5 VGA_PWROK#
6
DGPU_PWR_EN
C622 VGA@
0.01U_0603_50V7K VGA@ Q1007B
4
VGA_PWROK# 2 2 L2N7002DW1T1G_SC88-6
+3VSDGPU_AON R2633 +3VSDGPU_MAIN Q1007A VGA@

0_0603_5% L2N7002DW1T1G_SC88-6 1
1 2
NGC6@
+5VALW +1.5VSDGPU
DVT modify 11/20
+5VALW +3VLP +5VALW change to +3VLP
2
@ R998 @ R571
2
@ VGA@ 100K_0402_5% 47_0603_5%

R994 R995
100K_0402_5% 100K_0402_5%
+3VS to +3VSDGPU_MAIN for GC6-2.0
1
1.5VS_DGPU_PWR_EN# +1.5VSDGPU_R
1
100mil(1.5A) DGPU_PWR_EN# VGA_PWROK#
+3VS +3VSDGPU_MAIN L2N7002LT1G_SOT23-3 L2N7002LT1G_SOT23-3

1
1
U14 @ D D VGA@ D D
5 1 2 2 1.5VS_DGPU_PWR_EN 2 2 1.5VS_DGPU_PWR_EN#
IN OUT <10,11,52> DGPU_PWR_EN VGA_PWROK <9,19,52> <19,51> 1.5VS_DGPU_PWR_EN
G G G G
2
2 2 2 S S @ S S
3
3
GND
2
4 C624 GC6@ Q33 Q34 R999 @ Q2005 @ Q2006 4

1U_0402_6.3V6K 4 3 C625 @ VGA@ 100K_0402_5% L2N7002LT1G_SOT23-3 L2N7002LT1G_SOT23-3
GC6@ EN OC 4.7U_0603_6.3V6K R996 R997
1 SY6288C20AAC_SOT23-5 1 100K_0402_5% 100K_0402_5%
1
GC6@
1
<19,52> 3VSDGPU_MAIN_EN

DC Interface
3VSDGPU_MAIN_EN From GPU AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
A B C D E
A B C D
1 +19V_ADPIN EMI@ PL101

+19V_VIN 1
@ PJP101 5A_Z120_25M_0805_2P
ACES_50305-00441-001_4P
1 2
1
2
3
4
GND
1
GND EMI@ PC102 EMI@ PC103
100P_0603_50V8 1000P_0603_50V7K
2
2 2
3 3
@ PR111
0_0402_5%
1 2
+3VLP +CHGRTC
- PBJ101 @ + PR112
560_0603_5%
PR113
560_0603_5%
2 1 1 2 1 2
+R TCBATT
ML1220T13RE
4 4

DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
A B C D
A B C D
PR208 100_0402_1%
1 2
EC_SMB_DA1 <38,44> +3VLP
PR210 100_0402_1%
1 2
EC_SMB_CK1 <38,44>
PR211
1
6.49K_0402_1%
1 2 @ PC202
+3VLP
1
PJP201 0.1U_0603_25V7K
2
1
1
1 2 1 2 @ PR204 @ PR205
1
2 3 EC_SMB_DA1-1
BATT_TEMP <38> 10K_0402_1%
3 4 EC_SMB_CK1-1 PR209 1K_0402_1%
<45,47> 10K_0402_1%
4 5
2
BATT_TS
5 6
1
BATT_B/I @ PU201
6 7 @ PR206 1 8
7 8 100K_0402_1% VCC TMSNS1
8 9 +RTCVCC 2 7 2 1
GND 10 GND RHYST1
GND
1
MAINPWON 3 6 @ PR207
<38,40,45> MAINPWON OT1 TMSNS2
ACES_50458-00801-001 47K_0402_1%
1
4 5 @ PH201
PR212 OT2 RHYST2 100K_0402_1%_NCP15WF104F03RC
@
100K_0402_5% G718TM1U_SOT23-8
2
2
D
1
2 PQ201 2013/10/28 update PH201 chang
<40> BI_GATE G BSS138LT1G_SOT23-3
S Common part SL200002H00
3
+17.4V_BATT+
EMI@ PL201
5A_Z120_25M_0805_2P
1 2
+17.4V_BATT
EMI@ PL202
5A_Z120_25M_0805_2P
1 2
2 2
1
1
PC201 EMI@ PC205 @EMI@
1000P_0603_50V7K 0.01U_0603_25V7K
2
2
2014/09/30 update
For KB9022
sense 20mΩ
Active Recovery
45W PR202
10K ohm 58.5W,0.61V 45W,0.47V
SD034100280
65W PR202
19.1K ohm 84.5W,0.61V 65W,0.47V
PH202 under CPU botten side : SD034191280
CPU thermal protection at 90 degree C ( shutdown )
Recovery at 56 degree C +EC_VCCA
3 3
2013/10/02 ADP_I <38,44>

Add for ENE9022 Battery Voltage drop detection.
65W@ PR202
Connect to ENE9022 pin64 AD1.
1
19.1K_0402_1%
+19VB_5V PR216 PR202
18.2K_0402_1% 10K_0402_1%
Battery is 3-cell design. 45W@
2
B+=9V @
1
PR230
<38> VCIN0_PH
80.6K_0402_1%
@ PR229
2
0_0402_5% VCIN1_PROCHOT <38>

1 2
VCIN1_BATT_DROP<38>
1
PH202
1
100K_0402_1%_NCP15WF104F03RC
2
@ PC203 @ PR228
B value:4250K±1% @
2
0.1U_0402_25V6 10K_0402_1% T201
1
2013/10/28 update PH202 chang @

2
T202
Common part SL200002H00
1
1
PR203
10K_0402_1%
PR225
0_0402_5%
2
For 65W adapter==>action 70W , Recovery 54W
4 4
2
For 40W adapter==>action 52W , Recovery 40W
<38> ECAGND

BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DocumentNumber Rev
A B C D
A B C D
Protection for reverse input
Vgs = 20V 2013/10/14

PR303 10m ohm chang -->20m ohm +19VB
1
PQ301 D
2
Vds = 60V
G Id = 250mA SD00000S120
S 2N7002KW_SOT323-3
3
PR302
PR301
1 2 1 2
1M_0402_5% 3M_0402_5% 2014/09/30 update PQ303&PQ304 change
1
Need check the SOA for inrush Common part SB0000010A00 1
2014/01/21 update PL301 change

+19V_VIN PQ303 Common part SH00000YG00
+19V_P1 MDV1526URH_PDFN33-8-5 +19V_P2 PQ304
1 1 PR303 EMI@ PL301 +19VB_CHG AON7506_DFN33-8-5
2 2 0.02_1206_1% 1UH +-30% 2.8A 1
5 3 3 5 1 4 1 2 2
Isat: 4A 5 3
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
2 3
2200P_0402_50V7K
DCR: 27mohm
0.1U_0402_25V6
0.1U_0402_25V6
4
@EMI@PC306
1
1
PQ302
PC303
PC304
EMI@ PC305
0_0402_5%
0.01U_0402_50V7K
PC301
@ PR304
4
1
1
MDU1512RH_POWERDFN56-8-5 +19V_VIN
PC302
PC307
2
2
2
2
VF = 0.5V
2
2
3
2
PD301
BQ24725A_ACDRV_1 BAS40CW_SOT323-3
0.1U_0402_25V6
BQ24725A_BATDRV 1 2BQ24725A_BATDRV_1
0.1U_0402_25V6
Rds(on) = 30mohm max
1
1
PR305
PC308
PC310
Vgs = 20V
1 1
1 2 PC311 4.12K_0603_1%
10_1206_1%
0.047U_0402_25V7K Vds = 30V
PR306
2
PC309 1 2 ID = 7A (Ta=70C) 2013/11/29 update PL302 change
MDV1528URH_PDFN33-8-5
0.1U_0402_25V6 VF = 0.37V Common part SH00000YB00
5
2.2_0603_5%
PD302
PR307
BQ24725A_VCC2
RB751V-40_SOD323-2 Support max charge 3.5A
@ PR308 7*7*3
BQ24725A_ACP
0_0603_5%
Power loss: 0.245W
BQ24725A_REGN
CSR rating: 1W
BQ24725A_BST 2
2
DH_CHG 1 2 4
PQ305
VSRP-VSRN spec < 81.28mV
BQ24725A_LX
4.12K_0603_1%
4.12K_0603_1%
2 2
1
PC312 +17.4V_BATT
PR309
PR310
1 2
DH_CHG
PL302
10UH_PCMB063T-100MS_4A_20% PR311
3
2
1
1U_0603_25V6K 1 2 0.01_1206_1%
BQ24725A_ACN
BQ24725A_LX 1 2 CHG1 4
2
PC313
5
1U_0603_25V6K 2 3
20
19
18
17
16
MDV1528URH_PDFN33-8-5
PU301
CSON1
1
CSOP1
4.7_1206_5%
VCC
PHASE
HIDRV
BTST
REGN
10U_0805_25V6K
10U_0805_25V6K
21
@EMI@
PR312
PAD
0.1U_0402_25V6
0.1U_0402_25V6
PC314
PC315
1
1
1 15 DL_CHG 4
PQ306
ACN LODRV
PC316
PC317
2
2
2 14
ACP GND
680P_0402_50V7K
PR313
3
2
1
2
1
BQ24735RGRR_QFN20_3P5X3P5 10_0603_1%
@EMI@
PC318
BQ24725A_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP
1
PR314
2
6.8_0603_1%
BQ24725A_ACDRV 4 12 SRN1 2 CSON1
ACDRV SRN
2
PC319
0.1U_0603_16V7K
+3VLP
1 2 5
ACOK BATDRV
11 BQ24725A_BATDRV **Design Notes**
Module model information PR315 100K_0402_1%
#For 65 /90W system, 3S1P/3S2P battery
ACDET
+3VLP
IOUT
Maximum Charging current 3.5A
SDA
SCL
ILIM
BQ24735A_V1.mdd 1 2 Battery discharge power 55W.
<10,38> ACIN @ PR324 #Register Setting
10
6
9
316K_0402_1% +3VALW
1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke
3
BQ24735A_V2.mdd 2. 0X12 bit3 set 1 (default 0) to enable turbo boost function
3
BQ24725A_ACDET
BQ24725A_ILIM 1 2
3. Disable turbo when AC only
BQ24725A_IOUT
PR316
100K_0402_1%
316K_0402_1%
#Circuit Design
0.01U_0402_25V7K
1
For 4S per cell 4.35V battery 1. ACOK,ILIM pull high voltage need base on 3/5V enable control
PC320
PR317
1
PR318
422K_0402_1% 2. Use 10X10 choke and 3X3 H/L side MOSFET
1 2 Charge current 3.5A
2
BQ24725A_ACDET
+19V_VIN Power loss : 1.82W
2
Power density : 0.81 (15X15)

3. If use 4S per cell 4.35V battery, need additional circuit
1
PR321
for ACDET(PR218/PR220/PR222 change to 0.1%, parallel resistors
2M_0402_1% with PR222 for ACDET setting)
4. PC223 2200p is for quick response when AC plug out.
5. For hybrid design, need double check PQ202,PQ203,PQ204,PQ205 component rating
2200P_0402_50V7K
2
66.5K_0402_1%
EC_SMB_CK1 <38,43> #Protect function

1. ACOVP : ACDET voltage > 3.14V
100P_0402_50V8J
1
1
PC321
2. Charger timeout : No communication within 175s(default)

PC322
PR322 @
PR319
0_0402_5% EC_SMB_DA1 <38,43> 3. ACOC : 3.33 X Input current DAC setting(default)

2
4. CHGOCP : 3/4.5/6A based on current current setting

2
@ PR320
2
5. BATOVP : 103-106%
1 2
0_0402_5%
1 2
ADP_I <38,43> 6. BATLOWV : 2.5V
PQ307
PR323 LTC015EUBFS8TL_UMT3F
7. TSHUT : 155C
8. IFAULT HI : 750mV (default)
1
100K_0402_1%
<38> BATT_4S
1 2 2 PC323 @ 9. IFAULT LOW : 110mV (default)
100P_0402_50V8J
2
4
Close EC chip 4
Vin Dectector
3
1
PQ308 D
2 Min. Typ Max.
<38,41,46,47,48> SUSP#
G
L-->H 17.16V 17.63V 18.12V
S 2N7002KW_SOT323-3 H-->L 16.76V 17.22V 17.70V
3

VILIM = 20*ILIM*Rsr Issued Date 2013/10/01 Deciphered Date 2014/05/24 Title
ILIM = 3.3*100/(100+316)/20/0.01 CHARGER
= 3.966 A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Common Circuit 1.0
A B C D
A B C D E
Module model information

SY8208B_V2.mdd
SY8208C_V2.mdd
EN1 and EN2 dont't floating

PR402
1 499K_0402_1% 1
+19VB ENLDO_3V5V 1 2
EMI@ PL401 PU401 @ PR401 PC403 +19VB
5A_Z120_25M_0805_2P SY8286BRAC_QFN20_3X3 0_0603_5% 0.1U_0603_25V7K
1
150K_0402_1%
1 2 +19VB_3V BST_3V1 2 1 2
PR404
2200P_0402_50V7K
2
10U_0805_25V6K
@EMI@ PC401
EMI@ PC404
0.1U_0402_25V6
BS
IN
IN
IN
IN
1
1
LX_3V 6 20
PC405
LX LX PL402
2
7 19 LX_3V 1 2
GND LX 1.5UH_6A_20%_5X5X3_M +3V ALWP
8 18
@EMI@ PR405
GND GND
4.7_1206_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
35.2
1
9 17
PG LDO +3VLP
PC407
PC408
PC409
PC410
1
10 16
NC NC
2
PC411
OUT
EN2
EN1
21 4.7U_0402_6.3V6M
NC
FF
GND
13V_SN 2
PR412
12
13
14
15
11
680P_0603_50V7K
100K_0402_5% 3.3V LDO 150mA~300mA
1 2
@EMI@ PC412
+3V ALWP
ENLDO_3V5V
Vout is 3.234V~3.366V Ipeak=7A
Imax=4.9A
2
<38> SPOK Iocp=10A
2 2
Check pull up resistor of
SPOK at HW side @ PJ401
PC402 PR403 +3V AL WP 1 2 +3VALW
1000P_0402_25V8J 1K_0402_5% 1 2
<38> 3V_EN 3V_FB 1 2 1 2 JUMP_43X118
+19VB @ PJ402
EMI@ PL403 +19VB_5V @ PR407 PC416 +5V AL WP 1 2 +5VALW
5A_Z120_25M_0805_2P 0_0603_5% 0.1U_0603_25V7K 1 2
1 2 +19VB_5V BST_5V 1 2 1 2 JUMP_43X118
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
PU402 SY8286CRAC_QFN20_3X3
0.1U_0402_25V6
1
1
PC414
PC415
EMI@ PC417
@EMI@ PC418
BS
IN
IN
IN
IN
5*5*3
2
LX_5V 6 20
@ LX LX PL404
7 19 LX_5V 1 2 +5V ALWP
GND LX
1.5UH_6A_20%_5X5X3_M
8 18 @ @
GND GND
1
3
PR408
3
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
680P_0603_50V7K 4.7_1206_5%
PC419 35.2
1
@EMI@
SPOK 1 2 9 17 1 2
PG VCC
PC420
PC421
PC422
PC423
PC428
PC427
@ PR413 10 16
NC NC 4.7U_0603_6.3V6M
2
15V_SN
0_0402_5%
OUT
LDO
2
EN2
EN1
21
FF
GND
12
13
14
15
11
PC425
VL
@EMI@
2
Vout is 4.998V~5.202V
ENLDO_3V5V
5V LDO 150mA~300mA
1
5V_EN
PC424
Ipeak=7A
4.7U_0603_6.3V6M
Imax=4.9A
2
PR409
2.2K_0402_5% Iocp=10A
1 2
<38> EC_ON @ PR410
0_0402_5%
1 2
<38,40,43> MAINPWON
PC413 PR406
1000P_0402_25V8J 1K_0402_5%
5V_EN 5V_FB 1 2 1 2
1M_0402_1%
4.7U_0402_6.3V6M
1
PC426
PR411
4 4
2
2
EC VDD0 is +3VL, PC426 UNPOP

EC VDD0 is +3VALW, PC426 POP

+3VALW/+5VALW
A B C D E
5 4 3 2 1

RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer
D D
Pin19 need pull separate from +1.5VP.

If you have +1.5V and +0.75V sequence question, 0.75Volt +/- 5%
EMI@ PL501 you can change from +1.5VP to +1.5VS. TDC 0.7A
+19VB 5A_Z120_25M_0805_2P
Peak Current 1A
1 2 +19VB_1.35V PR501
2.2_0603_5%
BST_1.35V 1 2 BOOT_1.35V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2014/10/09 +1.35VP
1
1
Vin=14.8V
@EMI@ PC502
PC503
PC504
PC505
Iin=0.431A DH_1.35V +0.675VSP
2
2
Via=2
EMI@
SW_1.35V
(No includ +0.675VSP)
10U_0805_6.3V6K
10U_0805_6.3V6K
1
2014/10/09
1
PC501
PC506
PC507
Vout=0.675V
5
0.1U_0603_25V7K
16
17
18
19
20
2
C
2014/10/16 update PU501
Imax=0.84A C
2
Setting OCP__PR502-->9.1K
PHASE
UGATE
BOOT
VLDOIN
VTT
H=4.5 PAD
21 Via=2
SF000002Z00 Common Part 4 DL_1.35V 15
LGATE VTTGND
1
ESR=15m ohm
PL502 14 2
PGND VTTSNS
1.364V 1.01% 1.5UH_9A_20%_7X7X3_M PQ501 PR502
1
2
3
MDV1528URH_PDFN33-8-5 13.7K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP PC508
CS RT8207MZQW_WQFN20_3X3
GND
1
1U_0603_10V6K
5
1 2 12 4 VTTREF_1.35V
VDDP VTTREF
2014/10/09 35.4
@EMI@ PR503
4.7_1206_5%
PR504
5.1_0603_5%
1
Vout=1.35V 1 2 VDD_1.35V 11 5
+5VALW VDD VDDQ
+1.35VP
1 2
1
+
PGOOD
Imax=3.78A
1
PC511 4 PC510
TON
Via=8
1
330U_2.5V_ESR17M_6.3X4.5 @EMI@ PC512 PR505 0.033U_0402_16V7K
FB
S5
S3
2
2
680P_0402_50V7K PC513 2.2_0402_1%
2
1U_0603_10V6K
10
6
1
2
3
2
PQ502
FB_1.35V
EN_0.675VSP
SI7716ADN-T1-GE3_POWERPAK8-5
TON_1.35V
EN_1.35V
+5VALW PR506
8.2K_0402_1%
2013/10/14 update PR507 1 2 +1.35VP
887K_0402_1%
B PQ502__AON7702A EOL change +19VB_1.35V 1 2 B
-->AON7506_SB000010A00
1
Mode Level +0.75VSP VTTREF_1.5V @ PR509 PR508
0_0402_5% 10K_0402_1%
S5 L off off 1 2
S3 L off on <38,41> SYSON
2
S0 H on on
1
MOSFET: 3x3 DFN @ PC514
0.1U_0402_16V4Z
Note: S3 - sleep ; S5 - power off H/S Rds(on): 27mohm(Typ), 34mohm(Max)
L/S Rds(on): 22mohm(Typ), 13.5mohm(Max)
2
@ PR510
0_0402_5%
Choke: 7x7x3 1 2
<38,41,44,47,48> SUSP# @ PR511
Rdc=8.3mohm(Typ), 10mohm(Max) 0_0402_5% @ PJ501
1 2 +1.35VP 1 2 +1.35V
Switching Frequency: 285kHz <17> DDR_VTT_PG_CTRL 1 2
1
JUMP_43X118
Ipeak=5.4A @ PC515 @ PJ502
Delta I =4.4A 0.1U_0402_16V4Z 1 2
1 2
2
Iocp=9.15~6.58A
OVP: 110%~120% JUMP_43X118
VFB=0.75V, Vout=1.364V @ PJ503

A5WAH PVT: ESD request add 0.1u 1 2
+0.675VSP 1 2 +0.675VS
JUMP_43X39
A A
Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2013/10/01 Deciphered Date 2014/05/24
+1.35VP/+0.675VSP
5 4 3 2 1
5 4 3 2 1
D D

SY8208D_V1.mdd
EN pin don't floating

If have pull down resistor at HW side, pls delete PR2
VC CS T_ PW R G D <1 3 , 38 >
PR608
10K_0402_5%
C
2 1
+3VS C
EMI@ PL601
+19VB 5A_Z120_25M_0805_2P PU601
1 2 +19VB_1.05V 2 9 @ PR601 PC601 @EMI@ PR604 @EMI@ PC603
IN PG 0_0603_5% 0.1U_0603_25V7K 4.7_1206_5% 680P_0603_50V7K
10U_0805_25V6K
3 1 BST_1.05V 1 2 1 2 1 2SNB_1.05V 1 2
0.1U_0402_25V6
2200P_0402_50V7K
IN BS
1
1
@EMI@ PC606
PC604
4 6 TDC 8A
EMI@ PC605
IN LX
2
2
5
IN LX
19
PL602 1.062V 1.01%
7
GND LX
20 LX_1.05V 1 2
+1.05VSP
8 14 FB_1.05V PCMB063T-1R0MS12A
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
GND FB
LDO_3V
1
@ PR602 18 17 LDO_3V PL602 from SH00000PJ00
330P_0402_50V7K
GND VCC
0_0402_5%
change to common part (R1)
PC609
PC610
PC611
PC612
PC615
PC616
1
1
<38,41,44 ,46,48> S U SP # 1 2 11 10
PC608
SH00000YE00 2013/10/23
2
EN NC
1
PC613
ILMT_1.05V 13 12 2.2U_0402_6.3V6M PR606 @ @
2
ILMT NC
@ PR605 15.4K_0402_1%
1
15 16
0_0402_5% +3VALW
2
BYP NC
1
PR603 @ PC602
2
ILMT_1.05V
PR606 part count reduce 1M_0402_1% 0.22U_0402_10V6K
PAD
21 PC609, PC610 from 47U_0603_6.3V6M change to
1
PC614
22U_0603_6.3V6M 2013/10/23
2
1
1U_0402_6.3V6K SY8288RAC_QFN20_3X3
2
@ PR607 2 FB = 0.6V
0_0402_5%
2
1
PR609 +1.05VSP PJ601
20K_0402_1% 1 2
1 2 +1.05VS_VTT
VFB=0.6V
2
Vout=0.6V* (1+R1/R2) (R2) JUMP_43X118 @
B Vout=1.062V B
The current limit is set to 8A, 12A or 16A when this pin Module model information
is pull low, floating or pull high
SY8208D_V1.mdd
A A
SecurityClassification Compal Secret Data Compal Electronics, Inc.

+1.05VSP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
5 4 3 2 1
5 4 3 2 1
2014/10/09 +3VS
Vin=3.3V
+5V ALW Iin=0.091A
Via=2
1
@ PJ701
1
JUMP_43X39
D D
2
PC702
1U_0402_6.3V6K
2
2
Ultra Low Dropout 0.23V(typical) at 3A Output Current
1
PC703
4.7U_0805_6.3V6K
2
6
5
1.507V 1.053%
VPP
7 VIN
POK 9 @ PJ702
TPAD
+1.5VSP +1.5VSP 1
1 2
2 +1.5VS
1
3
20K_0402_1%
PR701
VO
1
100K_0402_5% JUMP_43X39
1 2 8 4
PR703
PC704
<38,41,44,46,47> SUSP# VEN VO
Rup 0.01U_0402_25V7K
2014/10/09
GND
1
2 PC705
ADJ
Vout=1.5V
2
1
1
22U_0603_6.3V6M
0.1U_0402_16V7K
PC701
PR704 PU701
Imax=0.161A
2
47K_0402_5% G971ADJF11U_SO8
2
Via=2
1
2
PR705
Rdown 22.6K_0402_1%
2
C C
Vout=0.8V* (1+Rup/Rdown)
Ultra Low Dropout 0.23V(typical) at 3A Output Current
B B
A A

+1.5VSP
5 4 3 2 1
5 4 3 2 1
Base on BDW PDDG Rev_0_73 H-side MOS: MDV1525URH

Module model information: Rds(on):
ISL95813 (for 15W & 28W CPU) 15W 28W <10.1mohm@Vgs=10V
<14.0mohm@Vgs=4.5V
TDC 14A TDC 19A Id :24A@Vgs=10V
Location MAX 32A MAX 40A Note

D D
L-side MOS: MDU1511RH
OCP 38.4A OCP 48A Rds(on):
<2.4mohm@Vgs=10V
Loadline=-2.0mv/A Loadline=-2.0mv/A <3.3mohm@Vgs=4.5V
Follow intel guideline Id :100A@Vgs=10V
+1.05VS_VTT PR802 130_0402_1% PR820 392 Ohm 499Ohm OCP
1 2
PR816 1.27kOhm 1.58kOhm Droop
PC802
PC816 0.033uF 0.022uF RC Match -->20130828
1U_0402_6.3V6K PR803 54.9_0402_1% Choke: 0.15UH (Size:7*7*4)
1 2 1 2 PR804 90.9kOhm 113kOhm PROG1 SH00000U300
Rdc=0.66mohm +-7%
PR807 93.1kOhm 95.3kOhm IMON Heat Rating Current=36A
Saturation Current=45A
<13> VR_SVID_DATA
PC811 0.1uF ( 0402 ) 0.1uF ( 0402 ) RC Filter
Note:
VR_SVID_ALRT# Pull high on HW side
<13> VR_ALERT# PL803 EMI@
5A_Z120_25M_0805_2P
1 2
15W@ PR804 Note:

<13> VR_SVID_CLK
90.9K_0402_1%
PR804=113K +19VB_CPU PL801 EMI@
+19VB
1 2 5A_Z120_25M_0805_2P
C =>Icc(max)=40A C
VR_SVID_ALRT#
fsw=700KHz +19VB_CPU 1 2
VR_SVID_DATA
VR_SVID_CLK
2200P_0402_50V7K
0.01U_0402_50V7K
<13> VR_ON
10U_0805_25V6K
10U_0805_25V6K
68U_25V_M_R0.36
28W@ PR804 1
MDU1516URH_POWERDFN56-8-5
Height 8 mm 2014/10/09
@EMI@ PC805
EMI@ PC806
PC807
113K_0402_1% PQ801
PRGM1
1
+
PC804
PR805
100u_SF000000I80Vin=14.8V
1
PC803
1.91K_0402_1%
1 2
Iin=3.193A
2
@ PR806 2
Height 6 mm
2
68u_SF000000W00 Via=8
0_0603_5%
21
20
19
18
17
PU801 1 2 4
<13> VGATE
SCLK
SDA
ALERT#
PRGM1
PAD
PC808 VR_ON 1 16 LAGTE

2014/01/21 update PL802 change PL802
Common part SH000011H00
3
2
1
1000P_0402_50V7K VR_ON LGATE
1 2 0.22UH 20% FDUE0640J -H 25A
2 15 PHASE 1 4
PR807 PGOOD PHASE
+CPU_CORE
4.7_1206_5%
@EMI@ PR808
93.1K_0402_1% 2 3
MDU1511RH_POWERDFN56-8-5
1
1 2 IMON 3 14 UAGTE 28W@
IMON UGATE PR801 PC801 PQ803 PQ802
5
ISL95813HRZ-T_QFN20_3X4 2.2_0603_5% 0.22U_0603_16V7K
1
<38> VR_HOT# VR_HOT_1# 4 13 BOOT 1 2 1 2
PH802 VR_HOT# BOOT PR809
2
47P_0402_50V8J
470K_0402_5%_TSM0B474J4702RE PR810 3.65K_0603_1%

Over temperature protection: 1 2 1 2 NTC 5 12
NTC VCC +5VS
1
680P_0603_50V7K
PC809
@EMI@ PC810
4 4 TDC 19A
OTP Setting: 100C active
2
1
5.62K_0402_1%
Pin5 (NTC) voltage <0.88V, Protect PR811 COMP 6 11 PRGM2
MAX 40A
OCP 48A
2
Pin5 (NTC) voltage >0.92v, recovery COMP PRGM2
1
27.4K_0402_1%
ISUMN
ISUMP
Loadline=-2.0mv/A
2
1 2 PC811
RTN
3
2
1
3
2
1
124K_0402_1%
0.1U_0402_25V6
FB
2
1
2013/10/28 update PH802 chang
PR812
B B
10
7
Common part SL200002E00

3.65K_0402_1%
1
2014/10/09
2
FB Note:
ISUMN
ISUMP
PR813
33P_0402_50V8J PR812=124K Vout=1.35V

1
PC812 =>Slew rate=53mV/us Imax=28A

6800P_0402_25V7K
2K_0402_1%
10_0402_1%
2
Vboot = 1.7V
1
Via=56
@ PR815
2
PR814
1
1.27K_0402_1%
PC813
PR816
2
1
20M_0402_5%
390P_0402_50V7K
1
1
330P_0402_50V7K
PR818
2
1
@ PC815
PR817
2.61K_0402_1%
RC Match
2
PC814
Droop
2
2
15W@
2
1
28W@ PR816
1.58K_0402_1% PC816 PC817 PR819
@ 0.033U_0402_16V7K 0.1U_0402_16V4Z 11K_0402_1%
2
1
15W@
<13> VCC_SENSE
28W@ PC816 PH801
28W@ PR820 OCP Setting 0.022U_0402_16V7K 10KB_0402_5%_ERTJ0ER103J
499_0402_1%
@ PC818
15W: 38A
28W: 48A
2
0.082U_0402_16V7K
1 2
2013/10/28 update PH801 chang
@ PC819
330P_0402_50V7K
Common part SL200002G00
1
PR820 15W@
1 2
A A
2
PC820 392_0402_1%
1 2
0.01U_0402_50V7K
@ PC821 @ PR821
<13> VSS_SENSE
1 2 1 2
123
4700P_0402_25V7K 1.5K_0402_1% Title
Local sense put on HW site CPU_CORE/GFX_CORE

Size DocumentNumber Rev
1.0
A4WAB M/B LA-C341P
Date: Wednesday,March 18,2015 Sheet 49 of 56
5 4 3 2 1
5 4 3 2 1
PWR Rule
需確認最新SPEC.
需確認最新
Modify 8/6.
D D
+CPU_CORE
30 X 22uF 0805
22U_0603_6.3V6M 2012/10/23
PC901
22U_0603_6.3V6M
PC902
22U_0603_6.3V6M
PC903
22U_0603_6.3V6M
PC904
22U_0603_6.3V6M
PC920
check the output cap Qty!!!
1
1
2012/10/24
23 pcs 22uF and reserve 7 pcs
2
2
2013/01/14
22uF*17 unpop:22uF*3
20130828
22U_0603_6.3V6M
PC906
22U_0603_6.3V6M
PC907
22U_0603_6.3V6M
PC918
22U_0603_6.3V6M
PC909
22U_0603_6.3V6M
PC910
15W: 22uF*14
1
1
28W: 22uF*16
2
2
C C
22U_0603_6.3V6M
PC911
22U_0603_6.3V6M
PC912
22U_0603_6.3V6M
PC913
22U_0603_6.3V6M
PC914
22U_0603_6.3V6M
PC915
1
1
2
2
22U_0603_6.3V6M
PC916
22U_0603_6.3V6M
PC917
22U_0603_6.3V6M
PC908
22U_0603_6.3V6M
PC919
22U_0603_6.3V6M
PC905
1
1
2
B B
A A

CPU_CORE_CAP
5 4 3 2 Date: Wednesday, March 18, 2015 1 Sheet 50 of 56
5 4 3 2 1
D D
EN pin don't floating

If have pull down resistor at HW side, pls delete PR2
PL1001 VGA_EMI@
+19VB 5A_Z120_25M_0805_2P PU1001 VGA@ @VGA@ VGA@ @VGA_EMI@ @VGA_EMI@
1 2 +19VB_1.5VSDGPUP 2 9 PR1001 PC1001 PR1004 PC1006
IN PG 0_0603_5% 0.1U_0603_25V7K 4.7_1206_5% 680P_0603_50V7K
10U_0805_25V6K
3 1 1
BST_1.5VSDGPUP 2 1 2 1 2 SNB_1.5VSDGPUP 1 2
VGA_EMI@ PC1003
@VGA_EMI@ PC1004
2200P_0402_50V7K
0.1U_0402_25V6
IN BS
1
1
PC1005
4 6 TDC 8A
IN LX
2
C GM@ PR1002 5
IN LX
19 VGA@ PL1002
1.527V 1.018% +1.5VSDGPUP C
VGA@
15K_0402_1%
7 20 LX_1.5VSDGPUP 1 2
GND LX
8 14 FB_1.5VSDGPUP PCMB063T-1R0MS 12A
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
GND FB
1
GT@ PR1002 18 17 LDO_3V_1.5VSDGPUP PL1002 from SH00000PJ00
GND VCC
0_0402_1%
(R1)
@VGA@ PC1010
VGA@ PC1011
VGA@ PC1012
VGA@ PC1013
@VGA@ PC1016
VGA@ PC1017
change to common part
330P_0402_50V7K
1
1
<19,41> 1.5 VS_DGPU_PW R_EN 1 2 11 10 VGA@
EN NC SH00000YE00 2013/10/23
2
PC1014 GT@
VGA@ PC1008
ILMT_1.5VSDGPUP 13 12 2.2U_0402_6.3V6M GM4G@ PR1005 GM2G@ PR1005 PR1005
ILMT NC
2
25.5K_0402_1% 30.9K_0402_1% 30.9K_0402_1%
1
VGA@ 15 16
+3V ALW BYP NC
2
1
GM@
VGA@ PC1015
1U_0402_6.3V6K
1M_0402_1% PC1002 21
PAD
1
PR1003 0.1U_0402_16V7K GM4G need 1.35V

2
SY8288RAC_QFN20_3X3
GT/GM2G need 1.5V
2
LDO_3V_1.5VSDGPUP FB = 0.6V
@
VFB=0.6V PJ1002
1
1
+1.5VSDGPUP 1 2 +1.5VSDGPU
1 2
@
PR1007
Vout=0.6V* (1+R1/R2) VGA@
PR1006 JUMP_43X118
0_0402_5% Rup=25.5K Vout=1.365V 20K_0402_1%
Rup=30.9K Vout=1.527V
2
2
ILMT_1.5VSDGPUP
(R2)
1
B B
@
PR1008
0_0402_5%
2

SY8208D_V1.mdd
A A
The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high
Issued Date 2013/10/01 Deciphered Date Title
1.5VSDGPUP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
5 4 3 2 1
A B C D
Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot) Current Limit threshold setting Different VGA Chip (different EDP-Peak Current) need select different solution
Rocset= (Ivalley * Rds(on) + 40 mV) / 10uA
Rt=Rrefadj // (Rboot+Rref2)
Module model information:
Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)] I_ripple=(19-0.9)*0.9/ VGA Chip N14P-GV N14P-GV2 N14M-GS N14M-LP N14P-LP N14P-GE N14P-GS N14P-GT N15S-GT N15V-GM
RT8813A_V1A for IC module (304.89Khz*0.36u*19)=7.811A
RT8813A_V1B for SW module Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2]
OpenVReg Configurations Config B Config B Config B Config B Config B Config B Config B Config B Config B Config C
Vout=Vmin+N*Vstep OCP=54A/2=27A per phase
Ivalley=27A-7.811A/2=23.1A
Vstep=(Vmax-Vmin)/Nmax Rated TDP Power at Tj=102C 18W 25W 18W 13W 18.9W 25W 25.6W 35.5W 18W 18.16W
PWM-VID Spec and component Values Boosted GPU Total at Tj=102C 25W 32W 25W 20W 23W N/A 30W 40W 25W 24.72W
H-side MOS:AON6552 L-side MOS:AON6554
Rds(on): Rds(on):
PWM-VID Spec Config B Config C Config D 5.6mohm@Vgs=10V 3.2mohm@Vgs=10V EDP-Continuous at Tj=102C 24A 32A 26A 22A 25A 27A 38A 45A 31A 29.2A
1 1
Vmin 0.6V 0.65V 0.9V 6.7mohm@Vgs=4.5V 3~3.8mohm@Vgs=4.5V

Id :20A@Ta=25 degC Id :85A@Ta=25 degC EDP-Peak at Tj=102C 35A 55A 45A 35A 35A 40A 60A 75A 60A 44.3A
Vmax 1.2V 1.15V 1.15V
Vboot 0.9V 0.9V 1.028V Istep max (Evaluation) 15A 27A 25A 20A 14A 12A 31.5A 35A
Voltage step 6.25mV 25mV 12.5mV Choke: 0.22uH (Size:7*7*4)
Rdc=0.97mohm +-5% OCP Setting Current 42A 66A 54A 42A 42A 48A 72A 90A 72A 54A
N of Voltage level 96 20 20 Heat Rating Current=34A
PSI : Rrefadj PR1209 20K 39K 27K Saturation Current=25A Rocset 8.96K 12.45K 10.7K 8.96K 8.96K 9.83K 8.3K 9.39K 13K 10.2K
1 phase with DEM 0V to 0.8V
1 phase with CCM 1.2V to 1.8V Rref1 PR1208 20K 30K 7.5K
Recommendation 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H2L 2phase 1H2L 2phase 1H1L 2phase 1H1L
2 phase with CCM 2.4V to 5.5V Rboot PR1211 2K 3K 0 C=3*330uF (9mohm)=990uF
Vripple=Iripple*ESR(min)=7.811A*3mohm=23.4mV
Rref2=PR1210 PR1210 18K 24K 6.2K 6mohm * 3 4.5mohm * 3
+PR1224 Polymer Cap (330uF) 6mohm * 2 9mohm * 3 9mohm * 3 6mohm * 2 6mohm * 2 6mohm * 2 (L=0.22uH) (L=0.15uH)
PR1224 0 3K 1.74K
EN High Threshold = 1.6V
C PC1210 2.7nf 1.8nf 5.6nf
Or OSCON (390uF) 10mohm * 3 10mohm * 3 10mohm * 3 10mohm * 3 10mohm * 3 10mohm * 3 NULL NULL GT@ GM@
N15S-GT N15V-GL N15V-GM
N16S-GT
N16V-GM
unmount PRV5 for 2 phase select +19VB_VGA VGA_EMI@ PL1201

PSI <19>
2 5A_Z120_25M_0805_2P 2
NGC6 for DIS GM 2 1

+19VB
GC6 for DIS GT
<19>
VGA@ PR1208 +3VS NGC6@ PR1202
DGPU_VID
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
20K_0402_1% 40.2K_0402_1%
2014/10/09
VGA@ PC1202
VGA@ PC1203
VGA@ PC1204
VGA@ PC1207
0.1U_0402_25V6
2200P_0402_50V7K
1
1
2 1 VGA_EN 1 2
@VGA_EMI@ PC1205
Dgpu_Pwr_En <10,11,41> Vout=14.8V
VGA_EMI@ PC1208
10K_0402_5%
10K_0402_5%
.1U_0402_16V7K
2
2
VGA@ PR1211 VGA@ PR1209 GC6@ PR1206
Imax=4.071A
@VGA@ PR1203
@VGA@ PR1205
0_0402_5%
2
1
2K_0402_1% 20K_0402_1% 15K_0402_1%
VGA@
PR1204
PC1209
2 1 2 1 1 2 VGA@ Via=10
3VSDGPU_MAIN_EN <19,41>
5
PQ1201
2
1
1
1
@VGA@
PR1210 PR1207
VGA@
18K_0402_1% 0_0603_5%
VGA@ UG1_VGA 1 2 UG1_VGA_R 4
1
1 2
PC1210 @VGA@
2700P_0402_50V7K PR1201
2
PR1224 0_0603_5%
VGA@
3
2
1
0_0402_5% BST1_VGA 1 2 BST1_VGA_R PL1202
VGA@ VGA@
0.36UH_PDME064T-R36MS1R405_24A_20% +VGA_CORE
2
1
NVVDD_GND_SENSE_R VGA@ PC1201 LX1_VGA 1 2
UGATE1
BOOT1
VID
PSI
EN
2
0.1U_0603_25V7K VGA@
@VGA_EMI@
680P_0402_50V7K 4.7_1206_5%
2
PQ1202
REFADJ 6 20 LX1_VGA
PR1212
REFADJ PHASE1
1SNUB_VGA1 1
REFIN_VGA 7 19 LG1_VGA 4
REFIN LGATE1
@VGA@ PR1213
0_0402_5%
1
VREF_VGA 8 PU1201 18 PVCC_VGA 1 2
+5VS
VGA@ PR1225
@VGA_EMI@
13K_0402_1%
VREF PVCC
VGA@
3
2
1
1
1
RT8812AGQW_WQFN20_3X3 VGA@ PC1214
PC1215
3
PC1213
1U_0402_6.3V6K
VGA@ PR1215
499K_0402_1%
TON_VGA 9
TON LGATE2
17 LG2_VGA
1U_0603_10V6K +19VB_VGA 2014/10/09 3
Vout=1.35V
2
2
VGA@ +19VB_VGA 2 1
+19VB_VGA
2
10 16
RGND PHASE2 Imax=35.7A
UGATE2
PGOOD
BOOT2
PR1214: OCP setting Via=72

VSNS
GND
VGA@
SS
from 50A to 25A
5
VGA@ PR1216 LX2_VGA PQ1203
100_0402_1%
21
11
12
13
14
15
1 2
1
VGA@ PC1216
@VGA@ PR1218 @VGA@ UG2_VGA_R 4
0_0402_5% PR1217 2 0.1U_0603_25V7K
1 2 NVVDD_GND_SENSE_R 0_0603_5%
<21> VSSSENSE_VGA
BST2_VGA 1 2 BST2_VGA_R
1
@VGA@ PC1218 PL1203
3
2
1
1
@VGA@ PC1217 @VGA@ PR1219 VGA@

.1U_0402_16V7K 0_0603_5% 0.36UH_PDME064T-R36MS1R405_24A_20% +VGA_CORE
2
@VGA@ PR1220 1000P_0402_50V7K UG2_VGA 1 2 UG2_VGA_R LX2_VGA 1 2

2
0_0402_5%
@VGA_EMI@
4.7_1206_5%
2
1 2 NVVDD_SENSE_R
<21> VCCSENSE_VGA
5
VGA@
PR1222
VGA_ PW R OK < 9, 1 9, 4 1>
PQ1204 N16S-GT EDP continuous:26A peak: 51A
VGA@ PR1221 L side Rds(on): 3mohm(Typ), 3.8mohm(Max)
100_0402_1% VGA@ PR1223
Idsm: 11A@Ta=25C, 14A@Ta=70C
1SNUB_VGA2 1
1 2 10K_0402_5%
+VGA_CORE 2 1 +3VS LG2_VGA 4
CHOKE:0.36uH, DCR 1.4m ohm, L/2 over 36A
680P_0402_50V7K
@VGA_EMI@
FSW = 304Khz
(R=499K-->304Khz) (R=620K-->245Khz)
PC1219
3
2
1
Imax=35A
Ipeak-51A
OCP = 61A
2
OVP=Vout*(145%~155%)
Remove GPU OTP circuit for HW request

4 4
SecurityClassification Compal Secret Data Compal Electronics, Inc.

RT8812
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
A B C D
5 4 3 2 1
D D
+VGA_CORE Under GPU Core GB4-128 package +VGA_CORE

N15x 2013/12/10
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
VGA@ PC1320
VGA@ PC1338
VGA@ PC1322
VGA@ PC1323
VGA@ PC1324
VGA@ PC1325
VGA@ PC1326
VGA@ PC1327
VGA@ PC1328
VGA@ PC1329
Under
4.7uF_0603_10pcs
1
1
1uF_0402_4pcs
Near
2
2
1 1
47uF_0805_1pcs
22uF_0603_1pcs(2PCS unpop)
560U_2.5V_M
560U_2.5V_M
+ +
4.7uF_0805_5pcs
PC1211
PC1212
1U_0402_10V7
1U_0402_10V7
1U_0402_10V7
1U_0402_10V7
VGA@ PC1334
VGA@ PC1335
VGA@ PC1336
VGA@ PC1337
2 2
1
N15x2013/10/17
VGA@
VGA@
Under
2
4.7uF_0603_15pcs
1uF_0402_8pcs
C
Near C
47uF_0805_0pcs
22uF_0603_9pcs(2PCS unpop)
4.7uF_0805_5pcs
N15x2013/10/07
Under
4.7uF_0603_15pcs
1uF_0402_8pcs
Near
47uF_0805_0pcs
+VGA_CORE 22uF_0805_9pcs(2PCS unpop)
4.7uF_0805_5pcs
PC1330
PC1331
PC1332
PC1333
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
+VGA_CORE Near GPU Core N15x2013/10/02

Under
2
B B
4.7uF_0603_15pcs
47U_0805_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
VGA@ PC1339
VGA@ PC1340
VGA@ PC1341
VGA@ PC1342
VGA@ PC1343
VGA@ PC1344
VGA@ PC1345
@RF@_VGA@
@RF@_VGA@
@RF@_VGA@
@RF@_VGA@
1uF_0402_8pcs
22U_0603_6.3V6M
PC1321
Near
1
1
47uF_0805_0pcs
22uF_0805_14pcs
4.7uF_0805_5pcs
2
2
VGA@
N14x
Under
4.7uF_0603_10pcs
0.1uF_0402_4pcs
Near
47uF_0805_1pcs
22uF_0805_1pcs
4.7uF_0805_5pcs
A A

VGA_CORE CAP
Date: W ednesday, March 18, 2015 Sheet 53 of 56
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Fixed Issue Reason for change PG# Modify List Date Phase
1 Design Update BOM Stucture Identical P.51 Add GT GM2G for PR1005 20141120 DVT
2 Design Update IC will Stop Production P.48 Change the PU701 from APL5930KAI to G971ADJF11U 20141120 DVT
D D
PR1208:20kOhm, PR120920kOhm, PR1210:18kOhm
Nvidia N16S-GT and N16V-GM PR1211:2kOhm, PR1224:0Ohm, PC1210:2700pF 20141120 DVT
3 Design Update P.52
Open VReg Configuration both use B PR1225:13kOhm
Change the PR817 from 4.99MOhm to 20MOhm.
P.49 Change the PR807 from 121kOhm to 93.1kOhm.
4 Design Update CPU Load Line Request Change the PR813 from 1.91kOhm to 3.65kOhm. 20141128 DVT
P.50
Change the PC917 PC908 and PC919 from @ to 22uF.
Change the PU401 from SYX198BQNC to SY8286BRAC
P.45 Change the PU402 from SYX198CQNC to SY8286CRAC
5 Design Update Solution Change P.47 Change the PU601 from SYX198DQNC to SY8288RAC 20141128 DVT
P.51 Change the PU1001 from SYX198DQNC to SY8288RAC
GM: PR1002:15kOhm, PC1002:0.1uF.
GT: PR1002:4.7kOhm, PC1002:0.1uF.
RC Value for GPU Sequence Fine Tune 20141128 DVT
P.51
6 Design Update GM(No Support GC6, Use DGPU_PWR_EN)
P.52
GC6 Function PR1202:40.2kOhm, PC1209:0.1uF.
C
GT(Support GC6, Use 3VSDGPU_MAIN_EN) C
PR1206:20kOhm, PC1209:0.1uF.
7 Design Update EMI request P.44 Add PL301 Delete PJ301 20141203 DVT
P.45 Change the PC403、
、PC416、、PC601、、PC1001
8 Design Update FAE request P.47 from 1000P_0402_25V8J to 0.1U_0603_25V7K 20141204 DVT
P.51
Change the PC411
9 Design Update FAE request P.45 from 4.7U_0603_6.3V6M to 4.7U_0402_6.3V6M 20141205 DVT
Change the PR1002 from 15K_0402_5% to 15K_0402_1% at GM

10 Design Update Solution Change P.51 Change the PR1002 from 4.7K_0402_5% to 10K_0402_1% at GT 20141215 DVT
11 Design Update Solution Change P.46Change the PU501 from RT8207P to RT8207M 20150105 PVT
P.51GT: PR1002 change to 0 ohm and depop PC1002.
12 Design Update GPU sequence fine tune RC value GT: PR1206 change to 15k ohm. 20150119 PVT
P.52
PQ303 change to MDV1526URH.
B P.44 PQ305,PQ306,PQ501 change to MDV1528URH. B
13 Design Update Solution Change P.46 PQ502 change to SI7716ADN. 20150119 PVT
P.49 PQ801,PQ1201,PQ1203 change to MDU1516URH.
PQ802,PQ803,PQ1202,PQ1204 change to MDU1511RH.
14 Design Update Thermal request P.43 Change the PR216 from 16.9K to 18.2K 20150122 PVT
P.44~47 Change the PR308 PR401 PR407 PR511 PR601
15 Design Update Solution Change P.49 PR602 PR806 PR1001 PR1002 PR1201 PR1207 20150122 PVT
P.51~52 PR1217 PR1219 from 0ohm to R-short
Change the PJP201 footprint from ACES_50458-00801-001_8P-T
16 Design Update DFX request P.43 to CVILU_CI9908M2HR0-NH_8P 20150122 PVT
A A

PIR (PWR)
Size DocumentNumber
5 4 3 2 1
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Version change list (P.I.R. List) Page 1 of 2 for HW
Item Page Title Date Issue Description Solution Description Phase Rev.
1 35 Codec 11/10 PC Beep is digital signal Change C2134 pin 2 connect from GNDA to GND. DVT 0.2
1
2 37 USB charger 11/12 USB charger function abnormal. Change U25 pin 4 from USB_CHARGE_2A to USB_EN DVT 0.2 1
Change U26 pin 4 from USB_EN to USB_CHARGE_2A
3 37 USB charger 11/17 Board ID change for DVT. Change R506 from 0_0402_5% to 12K_0402_5%. DVT 0.2
4 02 Block Diagram 11/19 Some block diagram descirptoin mistake. Correct block diagram description. DVT 0.2
change 3V_EN from pin 86 to 107, and original pin107 "DGPU_AC_DETECT"

5 38 EC 11/19 To solve 3V_EN need to connect to "Fixed code drive high" pin signal connect to EC pin 117 (NC now) DVT 0.2
Change L26 & L29 from CMMI21T-900Y-N_4P (0805 size) to

6 37 USB2.0 11/ 20 Follow EMI's request mail 1120. MCM1012B900F06BP_4P (0504 size), and remove R458, R461, R454, DVT 0.2
R465 0_0402_5% co-lay resistors.
7 37 USB 11/ 26 JUSB3 change from bottom to top side. Reverse JUSB3 pin connection. DVT 0.2
8 32 LAN 11/ 27 Request by DFb Change L2506 from SHI0000AA00 (S INDUC_ 2.2UH +-5% DVT 0.2
2 NLC252018T-2R2J-N) [2.2mm height] to SH00000RT00 (S COIL 2.2UH +-20% 2
HPC252012NF-2R2M 1.3A) [1.2mm height)
9 39 LED 11/ 27 LED light test Change R699 & R700 from 301_0402_1% to 470_0402_1%. DVT 0.2
10 32 Crystal 11/ 27 Crystal EA. Change C2558 & C2559 from 10P_0402_50V8J to 12P_0402_50V8J DVT 0.2
Reset
11 40 switch 12/ 01 RESET buvon 接 EC_RST# or MAINPWON? Add R2632 R-short connect to MAINPWON. DVT 0.2
12 24, 25 VRAM 12/ 01 fine tune VRAM Swap U2004 & U2006 group2 connection. DVT 0.2
26, 27 Swap U2008 & U2010 group4 connection.
13 40 Batt Switch 12/ 01 DFb request Change SW4 from DE100000T00 to SN200003I00. DVT 0.2
14 36 FFC HDD 12/ 01 FFC type HDD could pass Gen2 & Gen3 TX and iEMT EA Add C413~C416, C538~C541 cap for co-layout without re-driver path. DVT 0.2
3 15 19 NV 12/ 02 NV and EC didn't implement GPU_OVERT & GPU_ALERT code. Change Q2000 from VGA@ to @. DVT 0.2 3
16 19 NV 12/ 02 Follow NV's suggestion 1. Change D2002 & R2055 from GC6@ to @, change U2002 & R2628 from @ DVT 0.2
to GC6@.
2. Change Q2001 pin 2 & 5 from connect +3VSDGPU_MAIN to PLTRST_VGA#.
17 41 NV 12/ 03 N16V-GM not support GC6 2.0 Change J14 jumper to R2633 0_0603_5% DVT 0.2
18 31 CRT 12/ 03 CRT EA RGB rise time fail Change L2503 from SM01000FH00 (S SUPPRE_ MURATA DVT 0.2
BLM15BB470SN1D 0402) to SM01000LU00 ( S SUPPRE_ MURATA
BLM15BA220SN1D 0402)
19 35 Part 12/ 03 Correct part referernce type Change R2120~R2123 to L2511~L2514 DVT 0.2
Reference
4 4

PIR-HW
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z5WAH M/B LA-B161P
A B C D E
A B C D E
follow 2015 project design. Press reset button to pull down EC_RST# Change R2632 from R-short to non-pop.
42 40 Reset button 1/21
signal. Change R2631 from non-pop to R-short.
PVT 1.0
1 1
1. Change R65, R427, R428, R368~R375,R2552, R2125, R2131, R2611, R467, PVT 1.0
43 NPI confirm 1/22 NPI test confirm ready. R2618~R2626, R854 from 0_0402_5% to R-short.
2. Change R2075, R81 from 0_0603_5% to R-short.
44 Correct LED6 & LED7 footprint from LED_HT-210UD5-NB5_3P to

39 update footprint 1/22 Link LED symbol to CIS. LED_LTST-S115KFTBKT-CA_3P PVT 1.0
45 37 USB Follow 2015 project USB power switch OC pin design. Change R454 & R466 from R-short to non-pop.
1/22 PVT 1.0
power switch
2 2
3 3
4 4

PIR-HW
Custom 0.2
A B C D E
A B C D E
21 17 Test 12/05 Test plan Reserve Q2007 , place close to U45. DVT 0.2
1
22 10 Test 12/05 Test plan Reserve R2634 , place close to U30. DVT 0.2 1
23 13,17 DRAM 12/10 Choose cap. for better placement. Depop C18, pop C118. DVT 0.2
24 39 Lid SW 12/10 Change main source. Change U4 PN to SA00008K800. DVT 0.2
25 37 USB20 choke 12/17 SM070003K00 will shift when SMT and prohibit by factory. Change L26 & L29 to SM070003Y00. DVT 0.2
To prevent could not read or read wrong graphic temperature DVT 0.2
26 19 NV 12/17 Add Q2000 to let GPU_OVERT work.
via I2C and cause over temperature.
VGA_PWROK pull high to +3VS via 10K ohm, but R2014 10K pull down DVT 0.2
27 19 NV 12/17 willl make VGA_PWROK high voltage level out of spec. Change R2014 from 10K to 200K ohm. (Follow NV reference schematic.)
28 38 Board ID 12/22 Change board ID for PCB Revision 0.3 Change R506 from SD028120280 12K ohm to SD028150280 15K ohm PVT 1.0
29 13, 17 POS Cap 12/22 Follow schematic design common rule, POS Cap should use Serial P/N Change C18 & C118 from SGA20331E10 to SGA00009S00 PVT 1.0
2 2
30 39 ON/OFF button 12/30 SW6 is for RD test at NPI phase only. Change SW6 from DB@ to @. PVT 1.0
31 39 LED 12/30 LED test with DVT ME module. Change R699 & R700 from 470 ohm (SD034470080) to 560 ohm (SD000008380) PVT 1.0
Change R698 & R701 from 390 ohm (SD00000QZ00) to 430 ohm (SD00000LM00 )
32 19 NV 12/30 GPU throttle test. Reserve U17 for test. PVT 1.0
33 39 NV 12/30 Reserve level shift circuit to prevent Elan touch pad back drive issue. Reserve Q2008, R2640~R2642 level shift circuit. PVT 1.0
34 Component 1/7 Follow standard part Change Q7, Q8, Q14, Q15, Q40, Q1007, Q2000, Q2001, Q2003, Q2004, PVT 1.0
Q2008 from SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6) to
SB00000PV00 (S TR L2N7002DW1T1G 2N SC88-6)
35 36 Test 1/8 Reserve G-SEN_INT2 connector to JHDD2. Reserve R2643 & R2644. PVT 1.0
36 34 WLAN 1/12 SUSCLK will back drive to +3VS_WLAN when S3 or S5 with Broadcome Change R2612 from R-short to non-pop. PVT 1.0
3 3
NFA435 module. Check module datasheet not support SUSCLK, and intel
module could define as NC.
37 40 Screw hole 1/12 ME change NGFF standoff hole from 3.2 change to 3.3mm Change H17 Footprint from H_3P2 to H_3P3. PVT 1.0
38 35 Codec 1/19 ALC255 have PC beep in detect ciucuit in chip. Signal level under Change R2140 from SD028470280 (47K_0420_5%) to SD028270280 PVT 1.0
400mV will disable PC Beep function. (27K_0402_5%)
39 41 NV 1/19 To meet N16S-GT power sequence Add virtual symbol R469 for SGT@, change vaule from 47K_0402_5% to PVT 1.0
20K_0402_5%. Original R469 change from VGA@ to VGM@.
40 37 USB Charger 1/19 USB charger CB pin need a dedicate pin to control behavior. Change USB charger CB control pin from SUSP# to USB_CHARGE_CB connect PVT 1.0
to EC pin 86.
41 18 ESD 1/21 ESD Jason request to reserve a cap for DIMM_DRAMRST#. Reserve C2611. PVT 1.0
4 4

PIR-HW
Custom 0.2
A B C D E

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M/B Schematics Document

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, March 18, 2015 Sheet 1 of 56

Wildcat point I2C (PORT0)

SATA HDD SATA CDROM

Card Reader RJ45 conn.

RTC CKT. Sub Board

DC/DC Interface CKT.

Power Circuit DC/DC

Date: Wednesday, March 18, 2015 Sheet 2 of 56

Power Plane Description S1 S3 S5 Full ON HIGH HIGH HIGH HIGH ON ON ON ON

USB Port Table BTO Option Table

USB 3.0 Port ESD Reserve XESD@

3 CPU_IDEN HW@, BW@

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, March 18, 2015 Sheet 3 of 56

+3VS 2.2K +3V_PTP

Dual channel NMOS

+3VALW_PCH 2.2K +3VS

Dual channel NMOS

Dual channel NMOS

VGA Internal Thermal Senser 0x9E

KB9022 2.2K 2.2K

Dual channel NMOS

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, March 18, 2015 Sheet 4 of 56

VR_ON ISL95813HRZ-T 12000mA

+1.5VS_DGPU_PW R_EN SY8208DQNC

SPOK SY8208DQNC R-Short

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn Issued Date 2013/04/12 Deciphered Date 2014/04/12 Title

A4WAB M/B LA-C341P

+1.05VS_VTT U1B BDW_ULT_DDR3L(Interleaved)

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, March 18, 2015 Sheet 6 of 56

D DDR interleave routing DDR interleave routing D

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, March 18, 2015 Sheet 7 of 56

HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5

W =20mils trace width 10mil W =20mils @

+RTCBATT +CHGRTC +RTCVCC

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, March 18, 2015 Sheet 8 of 56

C43 A25 XTAL24_IN

LPC_AD0 AU14 AN2 PCH_GPIO11

3 1 VGA_CLKREQ# PCH_SPI_MOSI AA2

10/20: 2015 project not implement auto load,

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, March 18, 2015 Sheet 9 of 56

PCH_RSMRST# R117 1 2 10K_0402_5%

@ D21 Note: Deep Sx need use EC GPIO for

1 2 PCH_ACIN ACPRESENT function DSW ODVREN - On Die DSW VR Enable

SYS_PWROK R61 1 @ 2 0_0402_5% SYS_PWROK_R AG2 AJ5 PCH_PCIE_WAKE#

PLT_RST# AE6 SUSCLK

0: Port B or C is not detected

(Have internal PD)

R214 R215 Reserved 0 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, March 18, 2015 Sheet 10 of 56

R615 1 2 100K_0402_5% I2C_TS_INT#

3 6 PCH_GPIO25 CPU INFO DGPU_PRSNT# 1: Intel ME TLS with confidentiality

Security Classification Compal Secret Data Compal Electronics, Inc.