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EE141 Integrated Circuits2nd
Arithmetic Circuits
A B

## Cin Full Cout

Sum

EE141 Integrated Circuits2nd
Arithmetic Circuits
A B

Sum

S = A B Ci

## = ABC i + ABC i + ABCi + ABCi

C o = AB + BCi + AC i

EE141 Integrated Circuits2nd
Arithmetic Circuits
Express Sum and Carry as a function of P, G, D

## Define 3 new variable which ONLY depend on A, B

Generate (G) = AB
Propagate (P) = A B
Delete = A B

## Can also derive expressions for S and Co based on D and P

Note that we will be sometimes using an alternate definition for
Propagate (P) = A B
EE141 Integrated Circuits2nd
Arithmetic Circuits
VDD

VDD
Ci A B

A B
A

B
Ci B
VDD
A
X
Ci

Ci A S
Ci

A B B VDD
A B Ci A

Co B

28 Transistors
EE141 Integrated Circuits2nd
Arithmetic Circuits
A Better Structure: The Mirror Adder
VDD

VDD VDD A

A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate Generate
A B B A B Ci A

24 transistors

EE141 Integrated Circuits2nd
Arithmetic Circuits
Stick Diagram
VDD

A B Ci B A Ci Co Ci A B

Co

GND
EE141 Integrated Circuits2nd
Arithmetic Circuits
• The NMOS and PMOS chains are completely symmetrical.
A maximum of two series transistors can be observed in the carry-
generation circuitry.
• When laying out the cell, the most critical issue is the minimization
of the capacitance at node Co. The reduction of the diffusion
capacitances is particularly important.
• The capacitance at node Co is composed of four diffusion
capacitances, two internal gate capacitances, and six gate
capacitances in the connecting adder cell .
• The transistors connected to Ci are placed closest to the output.
• Only the transistors in the carry stage have to be optimized for
optimal speed. All transistors in the sum stage can be minimal
size.

EE141 Integrated Circuits2nd
Arithmetic Circuits

P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci

A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P

EE141 Integrated Circuits2nd
Arithmetic Circuits

EE141 Integrated Circuits2nd
Arithmetic Circuits

EE141 Integrated Circuits2nd
Arithmetic Circuits

EE141 Integrated Circuits2nd
Arithmetic Circuits
A0 B0 A1 B1 A2 B2 A3 B3

FA FA FA FA
( Ci,1)

S0 S1 S2 S3

td = O(N)

## Goal: Make the fastest possible carry path circuit

EE141 Integrated Circuits2nd
Arithmetic Circuits
Inversion Property

A B A B

Ci FA Co Ci FA Co

S S

EE141 Integrated Circuits2nd
Arithmetic Circuits
Minimize Critical Path by Reducing Inverting Stages

## Even cell Odd cell

A0 B0 A1 B1 A2 B2 A3 B3

FA FA FA FA

S0 S1 S2 S3

## Exploit Inversion Property

EE141 Integrated Circuits2nd
Arithmetic Circuits

EE141 Integrated Circuits2nd
Arithmetic Circuits

EE141 Integrated Circuits2nd
Arithmetic Circuits

EE141 Integrated Circuits2nd
Arithmetic Circuits

Co k = G k + P k G k – 1 + P k – 1 Co k–2 G3

G2

G1
All the way:
G0
Co k = Gk + P k G k – 1 + P k – 1 + P 1 G 0 + P 0 Ci 0
Ci,0
Co,3

P0

P1

P2

P3

EE141 Integrated Circuits2nd
Arithmetic Circuits
Manchester Carry Chain
VDD
Pi
VDD
Pi
Ci Co
Gi
Co Gi
Ci

Di
Pi

EE141 Integrated Circuits2nd
Arithmetic Circuits
Manchester Carry Chain
VDD

P0 P1 P2 P3
C3

Ci,0
G0 G1 G2 G3

C0 C1 C2 C3

EE141 Integrated Circuits2nd
Arithmetic Circuits
Manchester Carry Chain
Stick Diagram

Propagate/Generate Row

VDD
Pi Gi Pi + 1 Gi + 1

Ci - 1 Ci Ci + 1

GND

Inverter/Sum Row

EE141 Integrated Circuits2nd
Arithmetic Circuits
P0 G1 P0 G1 P2 G2 P3 G3 Also called
Carry-Skip
Ci,0 C o,0 C o,1 Co,2 Co,3
FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2
FA FA FA FA

Multiplexer
Co,3

## Idea: If (P0 and P1 and P2 and P3 = 1)

then C o3 = C0, else “kill” or “generate”.

EE141 Integrated Circuits2nd
Arithmetic Circuits
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
Setup tsetup Setup Setup Setup
tbypass

## Carry Carry Carry Carry

propagation propagation propagation propagation

M bits

## tadder = tsetup + Mtcarry + (N/M –1)tbypass + (M – 1)tcarry + tsum

EE141 Integrated Circuits2nd
Arithmetic Circuits
Carry Ripple versus Carry Bypass

tp

4..8 N

EE141 Integrated Circuits2nd
Arithmetic Circuits
Setup

P,G

## Co,k-1 Multiplexer Co,k+ 3

Carry Vector

Sum Generation

EE141 Integrated Circuits2nd
Arithmetic Circuits
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
Setup Setup Setup Setup

## Multiplexer Multiplexer Multiplexer Multiplexer

Ci,0 Co,3 Co,7 Co,11 Co,15

## Sum Generation Sum Generation Sum Generation Sum Generation

S0–3 S4–7 S8–11 S12–15

EE141 Integrated Circuits2nd
Arithmetic Circuits
Linear Carry Select
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

(1)

"0" "0" "0" "0"
(1)

## "1" Carry "1" Carry "1" Carry "1" Carry

"1" "1" "1" "1"
(5) (5) (5) (5) (5)
(6) (7) (8)
Multiplexer Multiplexer Multiplexer Multiplexer
Ci,0
(9)

## S0-3 S 4-7 S8-11 S 12-15 (10)

EE141 Integrated Circuits2nd
Arithmetic Circuits
Square Root Carry Select
Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13 Bit 14-19

(1)

"0" "0" "0" "0"
(1)

## "1" Carry "1" Carry "1" Carry "1" Carry

"1" "1" "1" "1"
(3) (3) (4) (5) (6) (7)
(4) (5) (6) (7)
Multiplexer Multiplexer Multiplexer Multiplexer Mux
Ci,0
(8)
Sum Generation Sum Generation Sum Generation Sum Generation Sum

## S 0-1 S2-4 S5-8 S 9-13 S 14-19 (9)

EE141 Integrated Circuits2nd
Arithmetic Circuits
50

30

Linear select
20

10
Square root select

0
0 20 40 60
N

EE141 Integrated Circuits2nd
Arithmetic Circuits
“O” Operator

Definizione

EE141 Integrated Circuits2nd
Arithmetic Circuits
Properties of the “O” operator

EE141 Integrated Circuits2nd
Arithmetic Circuits
Properties of the “O” operator

EE141 Integrated Circuits2nd
Arithmetic Circuits
Group Generate and Propagate

EE141 Integrated Circuits2nd
Arithmetic Circuits
Group Generate and Propagate

EE141 Integrated Circuits2nd
Arithmetic Circuits
Group Generate and Propagate

EE141 Integrated Circuits2nd
Arithmetic Circuits
A0 , B 0 A1, B1 ••• AN-1, BN-1

Ci,0 P0 Ci,1 P1
Ci, N-1 PN-1

S0 S1 ••• SN-1

Co k = f A k B k Co k–1 = G k + P k Co k –1

EE141 Integrated Circuits2nd
Arithmetic Circuits
A0 F

A1 A2 A3 A4 A5 A6 A7

A0
tp N
A1

A2
A3
F
A4
A5
A6 tp log2(N)
A7

EE141 Integrated Circuits2nd
Arithmetic Circuits

EE141 Integrated Circuits2nd
Arithmetic Circuits
Folding of the inverse tree

EE141 Integrated Circuits2nd
Arithmetic Circuits
Folding the inverse tree

EE141 Integrated Circuits2nd
Arithmetic Circuits
Dense tree with minimum fan-out

EE141 Integrated Circuits2nd
Arithmetic Circuits
Dense tree with simple connections

EE141 Integrated Circuits2nd
Arithmetic Circuits

Co 0 = G 0 + P 0 Ci 0

Co 1 = G 1 + P 1 G 0 + P 1 P 0 Ci 0
Co 2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C i 0

= G 2 + P 2 G 1 + P 2 P 1 G 0 + P 0 Ci 0 = G 2:1 + P2:1 C o 0

## Can continue building the tree hierarchically.

EE141 Integrated Circuits2nd
Arithmetic Circuits
(A0, B0) S0

(A1, B1) S1

(A2, B2) S2

(A3, B3) S3

(A4, B4) S4

(A5, B5) S5

(A6, B6) S6

(A7, B7) S7

(A8, B8) S8

(A9, B9) S9

## (A15, B15) S15

Arithmetic Circuits
(a 0, b 0) S0

(a 1, b 1) S1

(a 2, b 2) S2

(a 3, b 3) S3

(a 4, b 4) S4

(a 5, b 5) S5

(a 6, b 6) S6

(a 7, b 7) S7

(a 8, b 8) S8

## 16-bit radix-4 Kogge-Stone Tree (a 9, b 9) S9

(a 10, b 10 ) S 10

(a 11, b 11 ) S 11

(a 12, b 12 ) S 12

(a 13, b 13 ) S 13

(a 14, b 14 ) S 14

(a 15, b 15 ) S 15
Arithmetic Circuits
(a 0, b 0) S0

(a 1, b 1) S1

(a 2, b 2) S2

(a 3, b 3) S3

## EE141 Integrated Circuits2nd

(a 4, b 4) S4

(a 5, b 5) S5
Sparse Trees

(a 6, b 6) S6

(a 7, b 7) S7

(a 8, b 8) S8

(a 9, b 9) S9

(a 10 , b 10 ) S 10

(a 11 , b 11 ) S 11

(a 12 , b 12 ) S 12
16-bit radix-2 sparse tree with sparseness of 2

(a 13 , b 13 ) S 13

(a 14 , b 14 ) S 14

(a 15 , b 15 ) S 15
Arithmetic Circuits
(A0, B0) S0

(A1, B1) S1

(A2, B2) S2

(A3, B3) S3

Brent-Kung Tree
(A4, B4) S4

(A5, B5) S5

(A6, B6) S6

(A7, B7) S7

(A8, B8) S8

(A9, B9) S9

## (A15, B15) S15

Arithmetic Circuits
VDD

VDD
Clk
G i = a i bi

Clk
P i = a i + bi ai

ai bi
bi

Clk
Clk

Propagate Generate

EE141 Integrated Circuits2nd
Arithmetic Circuits
VDD
VDD

Clkk Clkk
Pi:i-2k+1 Gi:i-2k+1

Pi:i-k+1 Pi:i-k+1
Gi:i-k+1

Pi-k:i-2k+1 Gi-k:i-2k+1

EE141 Integrated Circuits2nd
Arithmetic Circuits
Example: Domino Sum
VDD VDD Keeper

Clk Clkd

Sum

Gi:0

Clk Si0

Clkd

Clk

Gi:0

Si1

Clk