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VERILOG

8x8 MULTIPLIER CODE

module multiplier (x,y,p,clk);

input clk;

input [7:0] x,y;

output [15:0] p;

reg [9:0] z;

wire [8:3] cout1;

wire [17:12] cout2;

wire [12:0] q;

wire [28:23] cout3;

wire cout33;

wire [31:1] s,c;

reg [7:0] l1,l2,l3,l4,l5,l6,l7,l8;

integer i1,i2,i3,i4,i5,i6,i7,i8;

initial

begin

z=10'b0000000000;

end

always @ (posedge clk )

begin

for(i1=0;i1<6;i1=i1+1)

begin

l1[i1]=x[i1]&y[0];
VERILOG
8x8 MULTIPLIER CODE

end

for(i2=0;i2<5;i2=i2+1)

begin

l2[i2]=x[i2]&y[1];

end

for(i3=0;i3<4;i3=i3+1)

begin

l3[i3]=x[i3]&y[2];

end

for(i4=0;i4<3;i4=i4+1)

begin

l4[i4]=x[i4]&y[3];

end

end

always @ (posedge clk )

begin

for(i1=6;i1<8;i1=i1+1)

begin

l1[i1]=x[i1]&y[0];

end
VERILOG
8x8 MULTIPLIER CODE

for(i2=5;i2<8;i2=i2+1)

begin

l2[i2]=x[i2]&y[1];

end

for(i3=4;i3<8;i3=i3+1)

begin

l3[i3]=x[i3]&y[2];

end

for(i4=3;i4<8;i4=i4+1)

begin

l4[i4]=x[i4]&y[3];

end

end

always @ (posedge clk )

begin

for(i5=0;i5<6;i5=i5+1)

begin

l5[i5]=x[i5]&y[4];

end
VERILOG
8x8 MULTIPLIER CODE

for(i6=0;i6<5;i6=i6+1)

begin

l6[i6]=x[i6]&y[5];

end

for(i7=0;i7<4;i7=i7+1)

begin

l7[i7]=x[i7]&y[6];

end

for(i8=0;i8<3;i8=i8+1)

begin

l8[i8]=x[i8]&y[7];

end

end

always @ (posedge clk )

begin

for(i5=6;i5<8;i5=i5+1)

begin

l5[i5]=x[i5]&y[4];

end
VERILOG
8x8 MULTIPLIER CODE

for(i6=5;i6<8;i6=i6+1)

begin

l6[i6]=x[i6]&y[5];

end

for(i7=4;i7<8;i7=i7+1)

begin

l7[i7]=x[i7]&y[6];

end

for(i8=3;i8<8;i8=i8+1)

begin

l8[i8]=x[i8]&y[7];

end

end

assign p[0]=l1[0];

half_add H1 (l1[1],l2[0],s[1],c[1]),

H2 (l5[1],l6[0],s[10],c[10]),

H3 (s[2],c[1],s[19],c[19]),
VERILOG
8x8 MULTIPLIER CODE

H4 (s[3],c[2],s[20],c[20]),

H5 (s[18],c[17],s[30],c[30]),

H6 (l8[7],c[18],s[31],c[31]);

assign p[1]=s[1];

assign p[2]=s[19];

full_add F1 (l1[2],l2[1],l3[0],s[2],c[2]),

F2 (cout1[8],l3[7],l4[6],s[9],c[9]),

F3 (l5[2],l6[1],l7[0],s[11],c[11]),

F4 (cout2[17],l7[7],l8[6],s[18],c[18]),

F5 (s[4],c[3],l5[0],s[21],c[21]),

F6 (s[5],c[4],s[10],s[22],c[22]),

F7 (cout3[28],s[17],c[16],s[29],c[29]),

F8 (c[19],s[20],z[8],p[3],q[0]),
VERILOG
8x8 MULTIPLIER CODE

F9 (c[20],s[21],q[0],p[4],q[1]),

F10 (c[21],s[22],q[1],p[5],q[2]),

F11 (c[22],s[23],q[2],p[6],q[3]),

F12 (c[23],s[24],q[3],p[7],q[4]),

F13 (c[24],s[25],q[4],p[8],q[5]),

F14 (c[25],s[26],q[5],p[9],q[6]),

F15 (c[26],s[27],q[6],p[10],q[7]),

F16 (c[27],s[28],q[7],p[11],q[8]),

F17 (c[28],s[29],q[8],p[12],q[9]),

F18 (c[29],s[30],q[9],p[13],q[10]),

F19 (c[30],s[31],q[10],p[14],q[11]),

F20 (c[31],z[9],q[11],p[15],q[12]);
VERILOG
8x8 MULTIPLIER CODE

compressor_4 c1 (l1[3],l2[2],l3[1],l4[0],z[0],s[3],c[3],cout1[3]),

c2 (l1[4],l2[3],l3[2],l4[1],cout1[3],s[4],c[4],cout1[4]),

c3 (l1[5],l2[4],l3[3],l4[2],cout1[4],s[5],c[5],cout1[5]),

c4 (l1[6],l2[5],l3[4],l4[3],z[1],s[6],c[6],cout1[6]),

c5 (l1[7],l2[6],l3[5],l4[4],cout1[6],s[7],c[7],cout1[7]),

c6 (z[2],l2[7],l3[6],l4[5],cout1[7],s[8],c[8],cout1[8]),

c7 (l5[3],l6[2],l7[1],l8[0],z[3],s[12],c[12],cout2[12]),

c8 (l5[4],l6[3],l7[2],l8[1],cout2[12],s[13],c[13],cout2[13]),

c9 (l5[5],l6[4],l7[3],l8[2],cout2[13],s[14],c[14],cout2[14]),

c10 (l5[6],l6[5],l7[4],l8[3],z[4],s[15],c[15],cout2[15]),

c11 (l5[7],l6[6],l7[5],l8[4],cout2[15],s[16],c[16],cout2[16]),

c12 (z[5],l6[7],l7[6],l8[5],cout2[16],s[17],c[17],cout2[17]),
VERILOG
8x8 MULTIPLIER CODE

c13 (s[6],c[5],s[11],c[10],cout1[5],s[23],c[23],cout3[23]),

c14 (s[7],c[6],s[12],c[11],cout3[23],s[24],c[24],cout3[24]),

c15 (s[8],c[7],s[13],c[12],cout3[24],s[25],c[25],cout3[25]),

c16 (s[9],c[8],s[14],c[13],cout3[25],s[26],c[26],cout3[26]),

c17 (cout33,s[16],c[15],z[7],cout3[27],s[28],c[28],cout3[28]);

compressor_5 c01 (l4[7],c[9],s[15],c[14],cout2[14],z[6],cout3[26],s[27],c[27],cout33,cout3[27]);

endmodule

module half_add (p,q,s,r);

input p,q;

output r,s;

assign s=p^q;

assign r=p&q;

endmodule

module full_add (A,B,C,SUM,CARRY);


VERILOG
8x8 MULTIPLIER CODE

input A,B,C;

output SUM,CARRY;

assign SUM=(A^B)^C;

assign CARRY=(A&B)|(B&C)|(A&C);

endmodule

module compressor_4 (P,Q,R,S,CIN,SUM,CARRY1,CARRY2);

input P,Q,R,S,CIN;

output SUM,CARRY1,CARRY2;

wire SUM1;

full_add FA1 (P,Q,R,SUM1,CARRY1),

FA2 (SUM1,S,CIN,SUM,CARRY2);

endmodule

module compressor_5 (a,b,c,d,e,f,g,h,i,j,k);

input a,b,c,d,e,f,g;

output h,i,j,k;

wire m,n;

full_add fa1 (a,b,c,m,k),

fa2 (m,d,e,n,j),

fa3 (n,f,g,h,i);
VERILOG
8x8 MULTIPLIER CODE

endmodule