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7.

Addressing Modes I

Data Formats: Registers
• The MFC5270 registers have 32 bits • The data bus is 32 bits wide • Instructions can operate on
• Bits, Bytes, Words & Long words • Indicated by the .B, .W & .L extensions

• Organization of Data Formats in Registers:

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Data Formats: Memory
Data is stored using big-endian scheme Operands are assumed to be aligned based on their size: —16-bit operands aligned on 0-modulo-2 addresses —32-bit operands aligned on 0-modulo-4 addresses Operands can be misaligned; however, this leads to performance degradation
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Byte Transfers
0x1230 0x1234 0x1238 Byte 1 Byte 2 Byte 3 Byte 4

31

15

7

0

Byte 1

move.b 0x1230,%d0

4

l 0x1230.Word Transfers 0x1230 0x1234 0x1238 Byte 1 Byte 2 Byte 3 Byte 4 31 15 7 0 Byte 1 Byte 2 move.w 0x1230.d0 6 .%d0 5 Longword Transfers 0x1230 0x1234 0x1238 Byte 1 Byte 2 Byte 3 Byte 4 31 15 7 0 Byte 1 Byte 2 Byte 3 Byte 4 move.

An instruction’s addressing mode specifies value of an operand. Each addressing mode has an assembler syntax. or how to derive the effective address of an operand. locations) Extension word 1 (if any) Extension word 2 (if any) 7 Effective Address Operand location can be specified using 1. modes. a register that contains the operand. The instruction’s definition (implied specific register). The register field within the instruction 2. other fields within instruction specify whether the register is an address or data register and how it should be used. 8 . The instruction’s effective address field 3.Instruction Format An Instruction consists of – operation code (which function to perform) – location of every operand for the function – extension word(s) with values of the operand(s) Operation word (op code.

Addressing Modes Refer to the way in which an operand address can be specified. Addressing modes of MCF5271: 1 2 3 4 5 6 7 8 9 10 11 12 Data Register Direct Address Register Direct Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement AR Indirect with Scaled Index and 8-Bit Displacement Program Counter Indirect with Displacement Mode PC Indirect with Scaled Index and 8-Bit Displacement Absolute Short Absolute Long Immediate 9 Assumptions for Examples Assume that before each example program segment the MCF5271 designated registers contain the following data: D1 D2 A2 A3 0x12345678 0xFEDCBA98 0x010000 0x011000 0x000200 0x78 0x9A and the contents of memory are: 0x00FFFE 0x010000 0x010002 0x11 0x33 0x55 0x22 0x44 0x66 0x011000 0x011002 0x77 0x99 0x88 0xAA 10 .

Data Register Direct Generation Assembler Syntax EA Mode Field EA Register Field EA = Dn Dn 000 Register number Number of Extension Words 0 11 Data Register Direct move.b %d1.%d2 After D1 D2 0x12345678 0x12345678 Before D1 D2 0x12345678 0xFEDCBA98 12 .%d2 After D1 D2 0x12345678 0xFEDC5678 move.%d2 After D1 D2 0x12345678 0xFEDCBA78 move.w %d1.l %d1.

Address Register Direct Generation Assembler Syntax EA Mode Field EA Register Field EA = An An 001 Register number Number of Extension Words 0 13 ColdFire’s Address Bus The ColdFire has a 32-bit PC – Enabling the addressing of 232 byte locations (4GB) Only 24 bits connected externally – Bits A[23:0] connected: can access 224 (16MB) bytes A31 … A24 A23 … A16 A15 … A8 A7 … A0 internal external – Internal lines used to qualify the address generated by software – Additional addressing space available through chip select (CS) – Byte. Word and Longword access facilitated using byte select (BS) BS3* b31 address address + 4 14 BS2* b24 b23 b16 b15 BS1* b8 b7 BS0* b0 .

b %d0.W = 0x0004 is sign extended to 0x00000004 MOVEA.%A0 give the same result -4.L #4.L #-4.b %a0.%A0 and MOVEA.%A0 and MOVEA.%A0 give the same result #4.%a1 is NOT – Word operands are sign extended 15 Word Operations on Addr. but movea.Special Instructions for A Registers • The ColdFire has special instructions to operate on address registers • Special Instructions – movea. suba (do not affect the CCR) – cmpa (comparison operation .W #4.W #-4.does affect the CCR) • Cannot operate on a byte of an address register – Only word and long word operations permitted move.%d1 is legal. Registers • An address register holds a 32 bit address which is a single entity • All operations are on 32-bits • For word operations the word (16-bits) is first sign extended to longword (32-bits) • Address space wraps-around (in both directions) MOVEA. adda.W = 0xFFFC is sign extended to 0xFFFFFFFC 16 .

l %d1.Address Register Direct movea.%a3 After D1 A3 0x12345678 0x12345678 Before D1 A3 0x12345678 0x00011000 17 Address Register Indirect Generation Assembler Syntax EA Mode Field EA Register Field EA = (An) (An) 010 Register number Number of Extension Words 0 18 .%a3 %d1.b movea.%a3 illegal (invalid size) After D1 A3 0x12345678 0x00005678 movea.w %d1.

w move.%d2 After D2 0xFEDCBA33 After D2 After D2 0xFEDC3344 0x33445566 Before D1 D2 A2 A3 0x12345678 0xFEDCBA98 0x00010000 0x00011000 0x010000 0x010002 0x33 0x44 0x55 0x66 20 .Address Register Indirect A2 0x00010000 0x010000 0x010002 0x33 0x44 0x55 0x66 19 Address Register Indirect Examples move.%d2 (%a2).%d2 (%a2).l (%a2).b move.

W 111 000 Number of Extension Words 1 21 Absolute Addressing: Long Generation Assembler Syntax EA Mode Field EA Register Field EA given xxx.L 111 001 Number of Extension Words 2 22 .Absolute Addressing: Short Generation Assembler Syntax EA Mode Field EA Register Field EA given xxx.

%d0 .2 words .Absolute Addressing The instruction uses the actual absolute address for accessing data in memory Absolute short: After 0x1000 0x12 0x1002 0x56 0x34 0x78 move.b 0x00008000. %d0 . 0x00010000 After 0x10000 0x78 0x44 0x10002 0x55 0x66 Before D1 0x12345678 23 0x00000000 0x00007FFF 0x00008000 Size of assembled instructions move.3 words Absolute Addressing Revisited 24 .b %d1. %d0 move.l %d1.b 0x7fff.b 0x00007fff.%d0 move. 0x1000 Absolute long: move.b 0x8000.2 words (0x8000 becomes 0xffff8000) 0xFFFF8000 0xFFFFFFFF How do we get 0x8000 ??? move.3 words .

%d2 ? 26 .l Before D2 0xFEDCBA98 After D2 0x00001000 D2 0xFEDCBC98 #0x100200.l 0x100200.Immediate Data Generation Assembler Syntax EA Mode Field EA Register Field Operator given #<xxx> 111 100 Number of Extension Words 1 or 2 25 Immediate Data The data is a constant immediately provided by the instruction Used to deal with constants: move.l #0x1000.%d2 add.%d2 After Note: how is this different from add.

%a1 sub. %d0 Loop: move.l #2. The program should start at 0x010000.w (%a0). loop otherwise exit 28 . program .(%a1) adda.l #0x12000.l #0x11000. %a0 adda. %d0 bne Loop .block1 to block2 * increment pointer 1 * increment pointer 2 * decrement counter * if counter not equal 0.10 words = 20 bytes 2010 = 1416 = 0x14 0x11000 0x12000 0x11012 0x12012 Example 1: Write program to move 10 consecutive words of data starting at memory location 0x011000 to a consecutive block of memory starting at memory location 0x012000.l #2.end * initialize counter in d0 * move word -.l #10. 27 Example 1: assembly lang.%a0 * a0 points at start of block 1 movea.l #1.section main Start: movea.%a1 * a1 points at start of block 2 move.

Example 1: pseudo-code addr1 = 0x11000 addr2 = 0x12000 for(i = 0. i < 10. %d0 bne Loop * decrement counter * if counter not equal 0.b #10. loop otherwise exit 30 . %d0 Loop: CODE BLOCK2 * initialize counter in d0 * Loop internals sub. i++) { Read a word from addr1 Write the word to addr2 increment addr1 increment addr2 } 29 Example 1: control constructs CODE BLOCK1 * Initialization statements move.l #1.

Example 1: fill in remaining code (1/2) Start: movea.l #1.block1 to block2 * increment pointer 1 * increment pointer 2 sub. %%d0 Loop: CODE BLOCK2 * initialize counter in d0 * Loop internals sub. %d0 bne Loop * decrement counter * if counter not equal 0.l #1.l #2. %d0 bne Loop * decrement counter * if counter not equal 0. loop otherwise exit 31 Example 1: fill in remaining code (2/2) Start: movea.l #0x11000.l #0x12000.%a1 * a1 points at start of block 2 move.l #0x12000.l #2. %a1 * initialize counter in d0 * move word -.(%a1) adda.l #0x11000.b #10.%a1 * a1 points at start of block 2 move.%a0 * a0 points at start of block 1 movea. loop otherwise exit 32 . %a0 adda.b #10.%a0 * a0 points at start of block 1 movea. %d0 Loop: move.w (%a0).

it might be 64 or 128 bits.%Dm NEGX %Dn [ Dm ] ← [ Dm ] + [ Dn ] + X [ Dm ] ← [ Dm ] .[ Dn ] – X 34 . or 128 bits) – Need special instructions to take into account the carry 33 Multiple Precision Arithmetic • The X – bit and C – carry bit are set by arithmetic operations CCR X N Z V C • Carry is changed by logical operations X is not • The X bit is used by special instructions ADDX %Dn. 8-bits wide • MFC5270 can perform arithmetic operations directly only on longwords (32 bits) • To operate on data of other lengths (e. we are using 3x8=24 bit operands to illustrate the principle of multiple precision arithmetic.%Dm SUBX %Dn.Variable Length Operands Example 2: Add two words P and Q of 24 bits (3 bytes) and to store the result in R 23 P PU Q R QU RU 0 PM QM RM PL QL RL PL PM PU QL QM QL RL RM RU Memory N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 Note: For simplicity. In reality.g.[ Dn ] – X [ Dn ] ← 0 . 64.

b %d0. AR Indirect with Displacement Generation Assembler Syntax EA Mode Field EA Register Field EA = (An) + d16 (d16. %d0 QU. RL store lower byte result in RL move. %d0 get middle byte of P move.An) 101 Register number Number of Extension Words 1 36 .b QM.b PM.b move. RU store middle byte result in RM get upper byte of P get upper byte of Q add upper bytes with carry store lower byte result in RU Note: For simple illustration only – MFC5270 does NOT have byte sized arithmetic operators.b move.b addx.Example 2: Extended Precision Memory .b move. %d1 get middle byte of Q addx. %d1 %d0.b QL.b %d1.%d1 add middle bytes with carry 35 PL N PM N+1 PU N+2 QL N+3 QM N+4 QL N+5 RL N+6 RM N+7 RU N+8 8-bits wide move. %d0 get lower byte of P add. RM PU.b PL.b %d0. %d0 add lower bytes move.section ADD24BIT * This will add two 24 bit numbers in memory * and stores the result in memory start move.%d1 %d1.

%An) • The 16-bit offset d16∈ [-32768.g.%A0 adda.AR Indirect with Displacement • The effective address of the operand is given by the contents of an address register plus a displacement/ offset • Syntax (d16.%D0 .w (0x10. saved one instruction (3 words) .l #ASCII_NUM.%A0 move.%A0 move.b 5(%A0).get the ASCII code for the number “5” into D0 movea.%d0 [d0] ← [M(0x10+[a1])] [d0] ← [M(0x1010)] 37 A1 0x00001000 Memory 0x1000 0x1002 0x1004 0x1006 0x1008 0x1010 16-bits wide Offset = 0x10 (An) with Displacement: Examples Assume that table called “ASCII_NUM” holds ASCII codes for “0” to “9” Example 3 .%a1). If [a1] = 0x1000 move.l #ASCII_NUM.b (%A0).ASCII code for 5 into D0 38 Note: the content of A0 intact.same thing using AR indirect with displacement movea.l #5.start of table into A0 .+32767] is sign extended and added to the address register • Often used to access items in a table e.%D0 Memory ASCII_NUM 0x30 31 0x32 33 0x34 35 0x36 37 0x38 39 (16-bits wide) Note: the content of A0 has been changed! Example 4 .

%A5 LEA 12(%A0). A0 by 10) [A5] ← 0x0010ffff AR Indirect with postincrement Generation Assembler Syntax EA Mode Field EA Register Field Number of Extension Words EA = (An).%A5 [A0] ← ASCII_NUM [A5] ← 0x0010ffff [A5] ← [A0] [A5] ← [A0] + 12 [A0] ← [A0] + 10 (incr. not the contents of the location.Load Effective Address – calculates the effective address of an operand and loads it into an address register – operates on 32-bits and is thus an intrinsically longword op – a facilitator for setting up address register pointers. one of the most powerful instructions Note: It’s the address.%A0 MOVEA.%A5 LEA 10(%A0).%A5 C O M P A R E LEA (%A0).Instruction LEA LEA .L #0x0010ffff. An = An + size (An)+ 011 Register number 0 40 . that is transferred! LEA ASCII_NUM.%A0 LEA 0x0010ffff.

%d2 After D2 0xFEDCBA33 A2 0x00010001 After D2 0xFEDC3344 A2 0x00010002 After D2 0x33445566 A2 0x00010004 Same as register indirect. EA = (An) -(An) 100 Register number 0 42 .l (%a2)+.b move. Before: 0x10000 0x33 0x44 D2 0xFEDCBA98 0x10002 0x55 0x66 A2 0x00010000 41 AR Indirect with predecrement Generation Assembler Syntax EA Mode Field EA Register Field Number of Extension Words An = An – size.AR Indirect with postincrement move.%d2 (%a2)+. except the address register is automatically incremented by the data size (in bytes) after it is used to do the data operation specified in the instruction.w move.%d2 (%a2)+.

l -(%a2). Before: 0x0000FFFC 0x11 0x22 A2 0x00010000 0x0000FFFE 0x33 0x44 D2 0xFEDCBA98 43 10 words = 20 bytes 2010 = 1416 = 0x14 0x11000 0x12000 0x11012 0x12012 Example 5: Write program to move 10 consecutive words of data starting at memory location 0x011000 to a consecutive block of memory starting at memory location 0x012000.%d2 -(%a2).%d2 After D2 0xFEDCBA44 A2 0x0000FFFF After D2 0xFEDC3344 A2 0x0000FFFE After D2 0x11223344 A2 0x0000FFFC Same as register indirect.w move.%d2 -(%a2).b move. except the address register is automatically decremented by the data size (in bytes) before it is used to do the data operation specified in the instruction.AR Indirect with predecrement move. 44 . but in reverse order.

-(%A1)* Move data and in/decrement A0/A1 SUB.B #10. program MOVE. go to label LOOP TRAP #15 * Halt Simulator * Code segment to move 10 words * from (A0) to (A1) in reverse order 45 Memory ARRAY1 ARRAY2 Memory ARRAY1+8 ARRAY2+8 +16 +16 16-bits wide 16-bits wide Example 6: A Routine to add two arrays.W (%A0)+.Example 5: assembly lang. ARRAY1 and ARRAY2 and leave the result in ARRAY2.L #$11114.L #1. need to use extended precision arithmetic using ADDX (add with extend).%D0 * Decrement counter BNE LOOP * If D0 <> 0. Each array is comprised of five 64-bit words.%D0 * Initialize counter for loop MOVEA.L #$11000.%A0 * Initialize A0 with first mem location MOVEA. 46 .%A1 * Initialize A1 with second mem location LOOP MOVE.

set A0 up to point at ARRAY1 .-(%A1) adda.add most significant 32 bits with extend (X) bit .b lea lea again move.l %D4.l add.l #8.%D0 ARRAY1.%D4 %D1.%D1 (%A1)+.if counter not equal 0 go back and do again .%D2 .Example 6: assembly lang.store 32 least significant bits in ARRAY2 .%D4 %D3.set A1 up to point at ARRAY2 .-(%A1) move. program move.%A1 subq.decrement array element counter .move 32 most significant bits of ARRAY2 into D2 .l bne again … .move 32 least significant bits ARRAY2 into D4 .l %D2.%D2 (%A0)+.l #5.store 32 most significant bits in ARRAY2 .%A0 ARRAY2.move 32 least significant bits of ARRAY1 into D3 .move 32 most significant bits of ARRAY1 into D1 .else exit (continue with the rest of the program) 47 move.l move.l move.%D3 (%A1)+.l move.adjust A1 to point at the next 64 bit word .set D0 up as a counter to count 5 elements .add least significant bits bits leaving result in D4 .%A1 (%A0)+.l addx.