AFFILIATED INSTITUTIONS

ANNA UNIVERSITY CHENNAI : : CHENNAI 600 025 REGULATIONS - 2009 CURRICULUM I TO IV SEMESTERS (FULL TIME)

M.E. VLSI DESIGN
SEMESTER I SL. COURSE NO CODE THEORY 1 MA9226 2 VL 9211 3 AP9212 4 VL9212 5 VL9213 6 E1 PRACTICAL 7 VL9217 COURSE TITLE L T P C

SEMESTER II SL. COURSE NO CODE THEORY 1 AP9221 2 VL9221 3 AP9222 4 AP9224 5 E2 6 E3 PRACTICAL 7 VL9225

VLSI Design Lab II TOTAL

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Analysis and Design of Analog Integrated Circuits CAD for VLSI Circuits Computer Architecture and Parallel Processing Embedded Systems Elective II Elective III

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COURSE TITLE

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VLSI Design Lab I

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Applied Mathematics for Electronics Engineers DSP Integrated Circuits Advanced Digital System Design VLSI Design Techniques Solid State Device Modeling and Simulation Elective I

3 3 3 3 3 3

1 0 0 0 0 0 0 1

0 0 0 0 0 0 4 4

4 3 3 3 3 3 2 21

TOTAL

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0 18 L

T

P

C

3 3 3 3 3 3 0 18

0 0 0 0 0 0 0 0

0 0 0 0 0 0 4 4

3 3 3 3 3 3 2 20

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SL. COURSE NO CODE THEORY 1 E4 2 E5 3 E6 PRACTICAL 4 VL9234

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SEMESTER III
COURSE TITLE L T P C

Elective IV Elective V Elective VI Project Work (Phase I)

3 3 3 0

0 0 0 0

0 0 0 12

3 3 3 6

1

TOTAL

9

0

12

15

SEMESTER IV
SL. COURSE NO CODE PRACTICAL 1 VL9241 COURSE TITLE L T P C

Project Work (Phase II) TOTAL

0 0

0 0

24 24

12 12

REGULATIONS - 2009 CURRICULUM I TO VI SEMESTERS (PART TIME)

M.E. VLSI DESIGN

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COURSE SL. NO CODE COURSE TITLE THEORY 1 MA9226 Applied Mathematics for Electronics Engineers 2 AP9212 Advanced Digital System Design

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SEMESTER I L 3 3 3 0 TOTAL 9 T 1 0 0 0 1 P 0 0 0 4 4 C 4 3 3 2 12

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VL9212

VLSI Design Techniques VLSI Design Laboratory I

PRACTICAL 4 VL9225

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SEMESTER II SL. COURSE NO CODE THEORY COURSE TITLE L T P C

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ANNA UNIVERSITY CHENNAI : : CHENNAI 600 025

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AFFILIATED INSTITUTIONS

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Total no.of credits to be earned for the award of Degree=68

1 2 3

AP9221 VL9221 AP9224

Analysis and Design of Analog Integrated Circuits CAD for VLSI Circuits Embedded Systems VLSI Design Laboratory II TOTAL

3 3 3 0 9

0 0 0 0 0

0 0 0 4 4

3 3 3 2 11

PRACTICAL 4 VL9225

SEMESTER III
SL. COURSE CODE NO COURSE TITLE THEORY 1 VL 9211 Digital Signal Processing Integrated Circuits 2 VL9213 Solid State Device Modeling and Simulation 3 E1 Elective I L 3 T 0 0 0 0 P 0 0 0 0 C 3 3 3 9

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TOTAL

3 3 9

SEMESTER IV

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SL. COURSE NO CODE COURSE TITLE THEORY 1 AP9222 Computer Architecture and Parallel Processing 2 E2 Elective II

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L 3 3 TOTAL 3 9

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P 0 0 0 0

C 3 3 3 9

3

E3

Elective III

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SEMESTER V
SL. COURSE NO CODE THEORY 1 E4 Elective IV 2 E5 Elective V 3 E6 Elective VI Project Work (phase I) PRACTICAL 4 VL9234 COURSE TITLE L 3 3 3 0 T 0 0 0 P 0 0 0 C 3 3 3 6

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0 12

3

b lo g .TOTAL 9 0 12 15 SEMESTER VI SL. VLSI DESIGN m C 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Testing of VLSI Circuits Low Power VLSI Design VLSI Signal Processing Analog VLSI Design Design of Semiconductor Memories VLSI Technology Physical Design of VLSI Circuits Genetic Algorithms and their Applications Advanced Microprocessors and Microcontrollers Neural Networks and Its Applications ASIC Design Reliability Engineering Electromagnetic Interference and Compatibility in System Design Digital Speech Signal Processing DSP Processor Architecture and programming Introduction to MEMS System Design Special Elective tp :// an n au ni vp or 4 ta l. COURSE NO CODE COURSE TITLE PRACTICAL 1 VL9241 Project Work (Phase II) TOTAL L 0 0 T P C 12 12 0 24 0 24 ht SL. NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 COURSE CODE VL9251 VL9252 VL9253 VL9254 VL9255 VL9256 VL9257 VL9258 VL9259 AP9252 VL9261 NE9251 AP9256 VL9264 VL9265 VL9266 COURSE TITLE sp ot .E.co L 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIST OF ELECTIVES M.

UNIT V QUEUEING MODELS 9 Poisson Process – Markovian queues – Single and Multi-server Models – Little’s formula . New York (1985).. John Wiley and Sons. Mathematical methods and algorithms for signal processing. Prentice Hall of India Pvt. Poisson. Moon. George J. ht tp :// an n au 5 lo g L = 45: T=15.Probability function – moments – moment generating functions and their properties – Binomial.. 7th Edition... Asia. New Delhi (2007). 2002. Fundamentals of Queueing theory. H. Theory and applications. Klir and Yuan.co m . Geometric. 1997. Private Ltd. Total: 45 Hours sp ot .C. Uniform. UNIT II MATRIX THEORY 9 Some important matrix factorizations – The Cholesky decomposition – QR factorization – Least squares method – Singular value decomposition . Sterling. MA9226 ni vp or ta l. Gamma and Normal distributions – Function of a Random Variable. 4.b REFERENCES: 1. Exponential. Fuzzy sets and fuzzy logic. Donald Gross and Carl M. 3.. Miller & Freund’s Probability and Statistics for Engineers. UNIT III ONE DIMENSIONAL RANDOM VARIABLES 9 Random variables . 7th edition. Pearson Education.Toeplitz matrices and some applications. Prentice – Hall of India.A. 5. Richard Johnson. 2000.Machine Interference Model – Steady State analysis – Self Service queue. T. 2. B. Ltd. New Delhi. Harris. Operations Research. 2nd edition.K. UNIT IV DYNAMIC PROGRAMMING 9 Dynamic programming – Principle of optimality – Forward and backward recursion – Applications of dynamic programming – Problem of dimensionality. Taha. Pearson education editions.APPLIED MATHEMATICS FOR ELECTRONICS ENGINEERS LT P C 3104 UNIT I FUZZY LOGIC 9 Classical logic – Multivalued logics – Fuzzy propositions – Fuzzy quantifiers. W.. An introduction.

Sensitivity and noise. FIR filter structures. Barrie W. Mapping of analog transfer functions. 4. Lars Wanhammer. Keshab K. Mapping of analog filter structures. Filter structures. Pearson Education. UNIT III DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS 9 FIR filters.V. Multiprocessors and multicomputers. MOS transistors. Scaling of signal levels. Image coding. Coefficient sensitivity. Sampling of analog signals. “Discrete-time Signal Processing”. Standard DSP architecture. Basic shift accumulator. Reducing the memory size.co m Total: 45 Hours REFERENCES: 1. Second Edition. Measuring round-off noise. Redundant Number system. Jervis. “VLSI Digital Signal Processing Systems design and Implementation”. Mapping of DSP algorithms onto hardware. John Wiley & Sons. 3. IIR filters. Asia. UNIT IV DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES 9 DSP system architectures. Systolic and Wave front arrays. FIR chips. Multirate filters. Selection of sample frequency. Improved shift-accumulator. Finite word length effects -Parasitic oscillations. Integrated circuit design. FFT processor. “DSP Integrated Circuits”. Pearson Education. Bit-parallel and Bit-Serial arithmetic.Oppenheim et. Transfer functions. Interpolation with an integer factor L. Adaptive DSP algorithms. VLSI process technologies. Shared memory architectures.VL 9211 DSP INTEGRATED CIRCUITS LTPC 3003 UNIT I DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES 9 Standard digital signal processors. DSP systems.processing systems. Round-off noise. Layout of VLSI circuits. 6 . Application specific IC’s for DSP. ht tp :// an n au ni vp or ta l. FFT-The Fast Fourier Transform Algorithm. UNIT II DIGITAL SIGNAL PROCESSING 9 Digital signal processing. DFT-The Discrete Fourier Transform. Frequency response. Implementation based on complex PEs. 2000. Discrete cosine transforms. Ifeachor. Residue Number System. 1999 Academic press. New York 2. Emmanuel C. Shared memory architecture with Bit – serial PEs. Cordic algorithm. DCT processor and Interpolator as case studies. Signal. Trends in CMOS technologies. 1999. Ideal DSP architectures.Parhi. Sampling rate change with a ratio L/M. UNIT V ARITHMETIC UNITS AND INTEGRATED CIRCUIT DESIGN 9 Conventional number system. A.al. “ Digital signal processing – A practical approach”. Multirate systems. DSP system design. Specifications of IIR filters. Complex multipliers. MOS logic. Signal flow graphs.b lo g sp ot .

2002 Parag K.2006 ht 7 .2001 Parag K.Perry “VHDL programming by Example” Tata McGraw.Realization of combinational and sequential circuits using HDL – Registers – counters – sequential machine – serial adder – Multiplier. dynamic and essential hazards – data synchronizers – mixed operating mode asynchronous circuits – designing vending machine controller UNIT III FAULT DIAGNOSIS AND TESTABILITY ALGORITHMS 9 Fault table method-path sensitization method – Boolean difference method-D algorithm -Tolerance techniques – The compact algorithm – Fault in PLA – Test generation-DFT schemes – Built in self test UNIT IV SYNCHRONOUS DESIGN USING PROGRAMMABLE DEVICES 9 Programming logic device families – Designing a synchronous sequential circuit using PLA/PAL – Realization of finite state machine using PLD – FPGA – Xilinx FPGA-Xilinx 4000 UNIT V SYSTEM DESIGN USING VHDL 9 VHDL operators – Arrays – concurrent and sequential statements – packages.Roth Jr “Fundamentals of Logic Design” Thomson Learning 2004 Nripendra N Biswas “Logic Design Theory” Prentice Hall of India.AP9212 ADVANCED DIGITAL SYSTEM DESIGN LTPC 3003 UNIT I SEQUENTIAL CIRCUIT DESIGN 9 Analysis of clocked synchronous sequential circuits and modeling.State diagram. state table.2003 Charles H Roth Jr.Hill .Divider – Design of simple microprocessor tp :// an n au ni vp or ta l.design of asynchronous sequential circuit-Static.b lo g sp ot .”Digital System Design using VHDL” Thomson learning.co m Total = 45 HRS REFERENCES: 1 2 3 4 5 6 Charles H. 2004 Douglas L.Data flow – Behavioral – structural modeling – compilation and simulation of VHDL code –Test bench .Lala “Fault Tolerant and Fault Testable Hardware Design” B S Publications.Lala “Digital system Design using PLD” B S Publications. state table assignment and reduction-Design of synchronous sequential circuits-design of iterative circuits-ASM chart and realization using ASM UNIT II ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 9 Analysis of asynchronous sequential circuit – flow table reduction-races-state assignment-transition table and problems in transition table.

Stick diagram. power dissipation and design margining. Pearson Education. Shift registers. Inc. priority encoders. sp ot . “Verilog HDL”. Inverter ratio. 2002. 6. Principles of CMOS VLSI Design.Publications. Multipliers. 2nd Edition.Design equationsSecond order effects. ht 8 . Carry look ahead adders.Fabricius. “A Verilog HDL Primer”. MOS models and small signal AC characteristics. floor planning. tp :// an n UNIT V VERILOG HARDWARE DESCRIPTION LANGUAGE 9 Overview of digital design with Verilog HDL. CMOS logic structures . 2nd Edition.Bhasker. 2nd edition. Weste and Kamran Eshraghian.cross talk. Pucknell. gate level modelling. Inductance. modules and port definitions. High-speed adders. UNIT II INVERTERS AND LOGIC GATES 9 NMOS and CMOS Inverters. Decoders. Prentice Hall of India Publication. Clock distribution. behavioral modelling. Introduction to VLSI Design McGraw Hill International Editions. Charge sharing .VL9212 VLSI DESIGN TECHNIQUES LTPC 3003 UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY 9 NMOS and PMOS transistors. Test Bench. UNIT III CIRCUIT CHARACTERISATION AND PERFORMANCE ESTIMATION 9 Resistance estimation. switching times. au ni vp or ta l.E.2002.Uyemura “Introduction to VLSI Circuits and Systems”. Pearson Education.S.Scaling. 1995. 2004. Super buffers. hierarchical modelling concepts. John Wiley & Sons.b lo g UNIT IV VLSI SYSTEM COMPONENTS CIRCUITS AND SYSTEM LEVEL PHYSICAL DESIGN 9 Multiplexers. J. John P. data flow modelling.. 1990. Neil H. transistor sizing. B. 2001. 7. Physical design – Delay modelling . Eugene D. Basics of CMOS testing. Wayne Wolf “Modern VLSI Design System on chip. Basic CMOS technology. DC and transient characteristics . switching characteristics. Pearson Education ASIA. power distribution. 2000. Transmission gates. dynamic CMOS design.Body effect. Arithmetic circuits – Ripple carry adders. Driving large capacitance loads. “Basic VLSI Design”. comparators. 4. 2.co m Total: 45 REFERENCES: 1. Threshold voltage. Samir Palnitkar. 3. task & functions. Capacitance estimation. 5. Static CMOS design.

Capacitors. UNIT II NOISE MODELING 9 Noise sources in MOSFET. MOSAI model) MODELLING OF PROCESS VARIATION AND QUALITY ASSURANCE 9 Influence of process variation. Inductors. Automation of the tests UNIT V ht tp :// an n au ni vp or ta l. Enhanced model for effective DC and AC channel length and width. Thermal noise modeling. modeling second order effects of the drain current. modeling of device mismatch for Analog/RF Applications. Benchmark circuits for quality assurance. Nonquasi-static modeling. FjeldlyWayne Wolf. I-V model. gate tunneling current model. Flicker noise modeling.Advanced MOSFET modeling. modeling of charge storage effects. Equivalent circuit representation of MOS transistor. long channel drain current model. Capacitance models. High speed model. model for accurate distortion analysis. Layout-dependent parasitics model. Resistors. Yuhua Cheng and Tor A. High frequency behavior of MOS transistor and A. junction diode models.VL9213 SOLID STATE DEVICE MODELING AND SIMULATION LTPC 3003 UNIT I MOSFET DEVICE PHYSICS 9 MOSFET capacitor. Basic operation. Threshold voltage model. noise model. MOS model 9. RF modeling of MOS transistors. substrate current models. Channel charge model. model features. Trond Ytterdal. RF model. John Wiley & Sons Ltd. mobility model. UNIT IV OTHER MOSFET MODELS 9 The EKV model.co m TOTAL: 45 REFERENCES: 1. 9 . “Device Modeling for Analog and RF CMOS Circuit Design”.C small signal modeling. model parameter extraction. noise model temperature effects. Basic modeling.b lo g sp ot . nonlinearities in CMOS devices and modeling. Source/drain resistance model. modeling parasitic BJT. calculation of distortion in analog CMOS circuits UNIT III BSIM4 MOSFET MODELING 9 Gate dielectric model.

5. Modeling of Sequential Digital system using Verilog. 8.VL9217 VLSI DESIGN LAB I LTPC 0042 1. Simulation of NMOS and CMOS circuits using SPICE.b lo g sp ot . Modeling of MOSFET using C. Digital Filters in DSP Processor. Implementation of DSP algorithms using software package. 2. 3. Implementation of FFT. 6. Modeling of Sequential Digital system using VHDL. Implementation of MAC Unit using FPGA. Design and Implementation of ALU using FPGA. ht tp :// an n au ni vp or 10 ta l. 7. 4.co m .

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS LTPC 3003 UNIT I MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES 9 Depletion region of a PN junction – large signal behavior of bipolar transistorssmall signal model of bipolar transistor. Frequency response of integrated circuits: Single stage and multistage amplifiers. Holberg. Bipolar and MOS Analog Integrated circuit design”. source follower and Push pull output stages. 2. Modelling and Technology”. closed loop analysis of PLL. Hurst. Operational amplifier noise UNIT IV ANALOG MULTIPLIER AND PLL 9 Analysis of four quadrant and variable trans conductance multiplier. MOS Telescopic-Cascode Operational Amplifier – MOS Folded Cascode and MOS Active Cascode Operational Amplifiers AP9221 ht tp :// an n au ni vp or ta l.”Semiconductor Devices. John Wiley & sons.large signal behavior of MOSFET. 4. “CMOS Analog Circuit Design”. 2002. voltage references. Gray. 5. S. Meyer. Second Edition-Oxford University Press-2003 11 . Behzad Razavi. UNIT III OPERATIONAL AMPLIFIERS 9 Analysis of operational amplifiers circuit.2003. Prentice Hall of India pvt. “Principles of data conversion system design”.small signal model of the MOS transistors. Willey International. 2004. Output stages: Emitter follower.. Phillip E.Inc. Monolithic PLL design in integrated circuits: Sources of noise.Noise models of Integrated-circuit Components – Circuit Noise Calculations – Equivalent Input Noise Generators – Noise Bandwidth – Noise Figure and Noise Temperature UNIT V ANALOG DESIGN WITH MOS TECHNOLOGY 9 MOS Current Mirrors – Simple. UNIT II CIRCUIT CONFIGURATION FOR LINEAR IC 9 Current sources. with Cascode. “Analysis and design of Analog IC’s”.co m TOTAL: 45 REFERENCES: 1.Chand and company ltd.short channel effects in MOS transistors – weak inversion in MOS transistors. ltd. voltage controlled oscillator. Lewis.substrate current flow in MOS transistor. supply and temperature independent biasing techniques.b lo g sp ot . slew rate model and high frequency analysis. Grebene. Nandita Dasgupata.Allen Douglas R. Wilson and Widlar current source – CMOS Class AB output stages – Two stage MOS Operational Amplifiers. 2000 3. Fourth Edition. Amitava Dasgupta. Analysis of difference amplifiers with active load using BJT and FET. Cascode.

Gerez.Circuit representation .Review of VLSI Design automation tools .partitioning UNIT III FLOOR PLANNING 9 Floor planning concepts .Algorithmic Graph Theory and Computational Complexity .global routing .High level transformations.Types of local routing problems .2002.Placement algorithms .Combinational Logic Synthesis .algorithms for global routing. UNIT V MODELLING AND SYNTHESIS 9 High level Synthesis . John Wiley & Sons.Two Level Logic Synthesis.Hardware models .H. 2.A.co m TOTAL: 45 REFERENCES: 1. UNIT IV SIMULATION 9 Simulation .problem formulation . 2002.b lo g sp ot . ht 12 .Binary Decision Diagrams . N. UNIT II DESIGN RULES 9 Layout Compaction .placement and partitioning .shape functions and floorplan sizing .Review of Data structures and algorithms .Switch-level modeling and simulation . Sherwani.Area routing . "Algorithms for VLSI Physical Design Automation". S.Internal representation .Tractable and Intractable problems . "Algorithms for VLSI Design Automation". tp :// an n au ni vp or ta l.general purpose methods for combinatorial optimization.Assignment problem .Design rules .Simple scheduling algorithm .channel routing .Allocation assignment and scheduling .VL9221 CAD FOR VLSI CIRCUITS LTPC 3003 UNIT I VLSI DESIGN METHODOLOGIES 9 Introduction to VLSI Design methodologies .Gate-level modeling and simulation . Kluwer Academic Publishers.algorithms for constraint graph compaction .

1994.Conditions of parallelism. Wilkinson. “ Designing Efficient Algorithms for Parallel Computers”. Program flow mechanisms. Scalable. Pearson Education . cache memory organisations. McGraw Hill International. Multithreaded and data flow architectures. “Modern processor design . bus cache and shared memory . 6. au ni vp or ta l. Parallel program development and environments. Michael. Terence Fountain. 5. “ Computer Organization and Architecture”. M.the state of computing. UNIT IV PIPELINING AND SUPERSCALAR TECHNOLOGIES 9 Parallel and scalable architectures. Tata McGraw Hill 2003.AP9222 COMPUTER ARCHITECTURE AND PARALLEL PROCESSING LTPC 3003 UNIT I THEORY OF PARALLELISM 9 Parallel computer models . Macmillan Publishing Company.co m 9 tp :// an n TOTAL: 45 REFERENCES: 1. Parallel processing applications. MACH and OSF/1 for parallel computers.Shen. UNIT II PARTITIONING AND SCHEDULING 9 Program partitioning and scheduling. Architectural development tracks. Dezso Sima. UNIX.backplane bus systems. Principles of scalable performance . " Advanced Computer Architecture ". UNIT V SOFTWARE AND PARALLEL PROGRAMMING Parallel models. Pearson Education ht 13 . 2.b lo g sp ot . speedup performance laws. Multiprocessor and Multicomputers. Kai Hwang. 2001. Multiprocessors and Multicomputers and Multivectors and SIMD computers. Allen “Parallel Programming”. 2003. “Scalable parallel computing”. virtual memory technology. Tata McGraw Hill 1998. PRAM and VLSI models. Fundamentals of super scalar processors”. Peter Kacsuk. System interconnect architectures. 3. Quinn.performance matrices and measures.J. Multivector and SIMD computers. Kai Hwang. Barry. Program and network properties. 1990. superscalar and vector processors. sequential and weak consistency models. 4. William Stallings. 7. Languages and compilers. shared memory organisations. ”Advanced Computer architecture – A design Space Approach” . John P. memory hierarchy technology. scalability analysis and approaches. UNIT III HARDWARE TECHNOLOGIES 9 Processor and memory hierarchy advanced processor technology. McGraw Hill International.

Asia . “ Advanced computer architecture –A systems Design Approach”. 2002 8. 2003. “ Fundamentals of parallel Processing”. Jordan Gita Alaghband. 2003 9. Richard Y. PHI.co m . Harry F. ht tp :// an n au ni vp or 14 ta l. Pearson Education .b lo g sp ot .Kain.

Personal Digital Assistants. challenges in validating timing constraints in priority driven systems. Quality Assurance.System Architecture. Liu. Formalism for System DesignStructural Description. Off-line Versus On-line scheduling. Networks for embedded systems. Optimality of the Earliest deadline first (EDF) algorithm. 3. Designing Hardware and Software Components. G. weighted round robin Approach. Embedded system design process. Specification. Flow of Control. Input/output devices. Memory devices. Set-top Boxes. Design Example : Alarm Clock.Memory organization.W. Pearson Education Asia. McGraw-Hill. Characteristics of Embedded Computing Applications. 15 . Jane. System Analysis and Architecture Design. CAN Bus.S. Krishna and K. Design Example: Model Train Controller. Network-Based design. designing with microprocessor development and debugging. CPU Bus configuration. ARM processor.processor and memory organization. ht tp :// an n au ni vp or ta l. Architectural Design. effective release times and deadlines. Dynamic Versus Static systems. 2. Flow of Control. Requirement Analysis. Hybrid Architecture UNIT III NETWORKS 9 Distributed Embedded Architecture. SHARC processor. UNIT IV REAL-TIME CHARACTERISTICS 9 Clock driven Approach. Design Example: Telephone PBX. Allocation and scheduling.b lo g sp ot . C.I2C. “Real-Time Systems” . “Embedded System Design: A Unified Hardware/Software Introduction” . Priority driven Approach. UNIT V SYSTEM DESIGN TECHNIQUES 9 Design Methodologies. Specification. Shin.Communication Analysis. “Computers as Components: Principles of Embedded Computing System Design”. ARM Bus. Design Example: Elevator Controller. 1997 4.Requirements. Wayne Wolf. John Wiley & Sons. system performance Analysis. Component interfacing. parallelism with instructions. Challenges in Embedded Computing system design. Hardware platform design.Hardware Design and Software Design. Myrinet.AP9224 EMBEDDED SYSTEMS LTPC 3003 UNIT I EMBEDDED PROCESSORS 9 Embedded Computers. Behavioural Description. SHARC Bus. Morgan Kaufman Publishers. M. Data operations.Hardware and Software Architectures. Ink jet printer. UNIT II EMBEDDED PROCESSOR AND COMPUTING PLATFORM 9 Data operations. Ethernet. SHARC link supports. System Integration. Frank Vahid and Tony Givargis.co m TOTAL: 45 REFERENCES: 1. Internet. “Real-Time systems”.

ht tp :// an n au ni vp or 16 ta l. 6.) Implementation of 8 Bit ALU in FPGA / CPLD. 4.) Implementation of model train controller using embedded m . 3.) Implementation of 4 Bit Sliced processor in FPGA / CPLD.) Implementation of Elevator controller using embedded microcontroller.b lo g sp ot .VL9225 VLSI DESIGN LAB II LTPC 0042 1.) System design using PLL.) Implementation of Alarm clock controller using embedded microcontroller. 2. microcontroller.co 5.

VL9251 TESTING OF VLSI CIRCUITS LTPC 3003 UNIT I BASICS OF TESTING AND FAULT MODELLING 9 Introduction to testing – Faults in Digital Circuits – Modelling of faults – Logical Fault Models – Fault detection – Fault Location – Fault dominance – Logic simulation – Types of simulation – Delay models – Gate Level Event – driven simulation. 2002.Agrawal. M. A. “Essentials of Electronic Testing for Digital. 4. Lala. 2002. “Digital Circuit Testing and Testability”.L. UNIT III DESIGN FOR TESTABILITY 9 Design for Testability – Ad-hoc design – generic scan based design – classical scan based design – system level DFT approaches.Abramovici.Breuer and A. M. UNIT IV SELF – TEST AND TEST ALGORITHMS 9 Built-In self Test – test pattern generation for BIST – Circular BIST – BIST Architectures – Testable Memory Design – Test Algorithms – Test generation for Embedded RAMs. Prentice Hall International.Bushnell and V. 2002. UNIT II TEST GENERATION FOR COMBINATIONAL AND SEQUENTIAL CIRCUITS 9 Test generation for combinational logic circuits – Testable combinational logic circuit design – Test generation for sequential circuits – design of testable sequential circuits.co m .2002. Academic Press.K.D.L. UNIT V FAULT DIAGNOSIS 9 Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design – System Level Diagnosis. Total: 45 REFERENCES: 1. Friedman.A. 3. ht tp :// an n au ni vp or 17 ta l.b lo g sp ot . 2. Jaico Publishing House.D. Memory and Mixed-Signal VLSI Circuits”. Kluwer Academic Publishers. “Design Test for Digital IC’s and Embedded Core Systems”. M. “Digital systems and Testable Design”.Crouch. P.

Abdelatif Belaouar. 7. 5. Inter connect and layout design – Advanced techniques – Special techniques. James B. 3. Kluwer. 1998.H Lou.VL9252 LOW POWER VLSI DESIGN LTPC 3003 UNIT I POWER DISSIPATION IN CMOS 9 Hierarchy of limits of power – Sources of power consumption – Physics of power dissipation in CMOS FET devices – Basic principle of low power design. lo g sp ot .Kulo and J. J. UNIT III DESIGN OF LOW POWER CMOS CIRCUITS 9 Computer arithmetic techniques for low power system – reducing power consumption in memories – low power clock. Dimitrios Soudris. Gary Yeap. or ta l. “Designing CMOS Circuits for Low Power”.I. Wiley 1999. “Low power CMOS VLSI circuit design”. 4. UNIT II POWER OPTIMIZATION 9 Logic level power optimization – Circuit level low power design – circuit techniques for reducing power consumption in adders and multipliers. UNIT IV POWER ESTIMATION 9 Power Estimation technique – logic power estimation – Simulation power analysis – Probabilistic power analysis. “Low voltage SOI CMOS VLSI devices and Circuits”. ht tp :// an n au ni vp TOTAL: 45 18 . inc. Kluwer. Kaushik Roy and S.co m REFERENCES: 1.Kulo. A.Prasad.W. Costas Goutis. “Practical low power digital VLSI design”.Elmasry. Chirstian Pignet. Wiley. 2002. Kluwer. Mohamed.b UNIT V SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER 9 Synthesis for low power – Behavioral level transform – software design for low power. Kluwer. Shih-Chia Lin.1995.C. 2.Broadersen.Chandrasekaran and R. John Wiley and sons. “Low power digital CMOS design”. “Low voltage CMOS VLSI Circuits”.B. “Low power digital VLSI design”.P. 1995. 2000. 2001. 6.

bit-serial FIR filter. “ VLSI Digital Signal Processing Systems. ROUND-OFF NOISE. Clustered look-ahead pipelining. Design of Lyon’s bit-serial multipliers using Horner’s rule. scaling and round-off noise computation. Design and implementation “. U. Parallel processing of IIR filters. Asynchronous pipelining bundled data versus dual rail protocol. parallel carry-ripple and carry-save multipliers. Look-Ahead pipelining with power-of-2 decomposition. properties of unfolding. Parhi. wave pipelining. Data flow and Dependence graphs . Odd-Even merge-sort architecture.co m . Pipelining and Parallel processing for low power. modified Cook-Toom algorithm. WAVE AND ASYNCHRONOUS PIPELINING 9 Numerical strength reduction – subexpression elimination. DCT architecture. BIT-LEVEL ARITHMETIC ARCHITECTURES 9 Scaling and round-off noise – scaling operation. Loop bound. L: 45 REFERENCES: 1. PIPELINING AND PARALLEL PROCESSING OF IIR FILTERS 9 Fast convolution – Cook-Toom algorithm. iteration bound. Bit-level arithmetic architectures – parallel multipliers with sign extension. clock skew in edge-triggered single phase clocking. rank-order filters. CSD multiplication using Horner’s rule for precision improvement. combined pipelining and parallel processing of IIR filters. iterative matching. 2. UNIT IV SCALING. parallel rankorder filters. Pipelining and Parallel processing of FIR filters. Distributed Arithmetic fundamentals and FIR filters UNIT V NUMERICAL STRENGTH REDUCTION. sample period reduction and parallel processing application. PIPELINING AND PARALLEL PROCESSING OF FIR FILTERS 9 Introduction to DSP systems – Typical DSP algorithms. round-off noise. UNIT II RETIMING. 2-parallel fast FIR filter. Algorithmic strength reduction in filters and transforms – 2-parallel FIR filter. Longest path matrix algorithm. “ Digital Signal Processing with Field Programmable Gate Arrays”. ALGORITHMIC STRENGTH REDUCTION 9 Retiming – definitions and properties. 2004 ht tp :// an n au ni vp or 19 ta l. Interscience. Pipelined and parallel recursive filters – Look-Ahead pipelining in first-order IIR filters. SYNCHRONOUS. synchronous pipelining and clocking styles. two-phase clocking. UNIT III FAST CONVOLUTION.VL9253 VLSI SIGNAL PROCESSING LTPC 3003 UNIT I INTRODUCTION TO DSP SYSTEMS. Wiley. CSD representation. Second Edition. state variable description of digital filters. Meyer – Baese. Keshab K. multiple constant multiplication. Unfolding – an algorithm for unfolding. 2007. round-off noise in pipelined IIR filters.critical path. Springer.b lo g sp ot .

“Analog VLSI signal and Information Processing ". Low-Power Neural Networks-CMOS Technology and ModelsDesign Methodology-Networks-Contrast Sensitive Silicon Retina.NMOS and CMOS ".Floating . m TOTAL : 45 REFERENCES: 1. “Analog VLSI Design .Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS. 1998. ANALOG COMPUTERAIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT 9 Review of Statistical Concepts . OVER SAMPLED A/D CONVERTERS AND ANALOG INTEGRATED SENSORS 9 First-order and Second SC Circuits-Bilinear Transformation .France. UNIT II BASIC BICMOS CIRCUIT TECHNIQUES.Haskard. “Design of Analog-Digital VLSI Circuits for Telecommunication and signal Processing ". Mohammed Ismail.b lo g sp ot . VLSI Design Techniques for Analog and Digital Circuits ". ht tp :// an n UNIT IV DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS 9 Fault modelling and Simulation .co UNIT III SAMPLED-DATA ANALOG FILTERS. Phillip E.Statistical Circuit SimulationAutomation Analog Circuit Design-automatic Analog Layout-CMOS Transistor LayoutResistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout. Terri Fiez. 1994 20 . Humidity and Magnetic Sensors-Sensor Interfaces. Randall L Geiger. " Noel K.VL9254 ANALOG VLSI DESIGN LTPC 3003 UNIT I BASIC CMOS CIRCUIT TECHNIQUES. 2. UNIT V STATISTICAL MODELING AND SIMULATION. Mc Graw Hill International Company. Yannis Tsividis.Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test BusesDesign for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits. 4. 1990. Malcom R.Cascade Design-SwitchedCapacitor Ladder Filter-Synthesis of Switched-Current Filter. CONTINUOUS TIME AND LOW.VOLTAGESIGNAL PROCESSING 9 Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOSTransistor. au ni vp or ta l. 1994.Nyquist rate A/D ConvertersModulators for Over sampled A/D Conversion-First and Second Order and Multibit SigmaDelta Modulators-Interpolative Modulators –Cascaded Architecture-Decimation Filtersmechanical. CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING 9 Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks .Bipolar and Low-Voltage BiCMOS OpAmp Design-Instrumentation Amplifier Design-Low Voltage Filters.Statistical Device Modeling. Allen. Lan C. 3. Prentice Hall. McGraw-Hill International Editons.Gate. Jose E. Prentice Hall.Strader.May. Thermal.

VL9255 DESIGN OF SEMICONDUCTOR MEMORIES LTPC 3003 UNIT I RANDOM ACCESS MEMORY TECHNOLOGIES 9 Static Random Access Memories (SRAMs): SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-Bipolar SRAM Technologies-Silicon On Insulator (SOI) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs. Electrical Testing. Psuedo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing. UNIT V PACKAGING TECHNOLOGIES 9 Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening TechniquesRadiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing .co m . Pseudo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and TestingApplication Specific Memory Testing UNIT IV RELIABILITY AND RADIATION EFFECTS 9 General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for ReliabilityReliability Test Structures-Reliability Screening and Qualification.Radiation Dosimetry-Water Level Radiation Testing and Test Structures. AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE 9 RAM Fault Modeling.Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) EPROMs-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-Advanced Flash Memory Architecture. TESTING. UNIT II NONVOLATILE MEMORIES 9 Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) . RAM Fault Modeling. TOTAL: 45 ht tp :// an n au ni vp or 21 ta l. Electrical Testing. Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions. Random Access Memories (MRAMs)-Experimental Memory Devices. Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magnetoresistive. DRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application.b lo g UNIT III sp ot . Dynamic Random Access Memories (DRAMs): DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Strucutures-BiCMOS. MEMORY FAULT MODELING. Specific DRAMs.

Betty Prince. Tegze P. 2. ht tp :// an n au ni vp or 22 ta l.b lo g sp ot .co m .Sharma. Kluwer Academic publishers. 2002. Testing and Reliability ". Kluwer Academic publishers. " Semiconductor Memories Technology. 3.Haraszti.Prentice-Hall of India Private Limited. “ Emerging Memories: Technologies and Trends”. 2001. New Delhi. “CMOS Memory Circuits”. 1997. Ashok K.REFERENCES: 1.

EPITAXY AND OXIDATION 9 Electronic Grade Silicon. WAFER PREPARATION. 2.Bipolar IC Technology – IC Fabrication.1998. 2003.Implant equipment. Feature Size control and Anisotropic Etch mechanism. “ Basic VLSI Design”. Silicon Shaping. processing consideration. Flick’s one dimensional Diffusion Equation – Atomic Diffusion Mechanism – Measurement techniques . Douglas A. Oxidation of Poly Silicon. Mc. UNIT II LITHOGRAPHY AND RELATIVE PLASMA ETCHING 9 Optical Lithography. ht tp :// an n UNIT V ASSEMBLY TECHNIQUES AND PACKAGING OF VLSI DEVICES 9 Analytical Beams – Beams Specimen interactions . Thin Oxides. 4. Czochralski crystal growing.Hill Second Edition. UNIT III DEPOSITION.Graw. Vapor phase Epitaxy. relative Plasma Etching techniques and Equipments.Chemical methods – Package types – banking design consideration – VLSI assembly technology – Package fabrication technology. Amar Mukherjee.Range theory. Oxidation Techniques and Systems. Polysilicon. 3. S.VL9256 VLSI TECHNOLOGY LTPC 3003 UNIT I CRYSTAL GROWTH. Annealing Shallow junction – High energy implantation – Physical vapour deposition – Patterning.2000. Electron Lithography.M. UNIT IV PROCESS SIMULATION AND VLSI PROCESS INTEGRATION 9 Ion implantation – Diffusion and oxidation – Epitaxy – Lithography – Etching and Deposition.b lo g sp ot .”Modern VLSI Design”. Prentice Hall India. Models of Diffusion in Solids. plasma assisted Deposition. X-Ray Lithography. Growth Mechanism and kinetics. “VLSI Technology”. Plasma properties. ION IMPLEMENTATION AND METALISATION 9 Deposition process. Silicon on Insulators.co m . DIFFUSION.Sze. “Introduction to NMOS and CMOS VLSI System design Prentice Hall India. Molecular Beam Epitaxy.NMOS IC Technology – CMOS IC Technology – MOS Memory IC technology . REFERENCES: 1. TOTAL: 45 au ni vp or 23 ta l. Oxide properties. Epitaxial Evaluation. Oxidation induced Defects. Prentice Hall India. Ion Lithography. Redistribution of Dopants at interface. Pucknell and Kamran Eshraghian. Wayne Wolf . 2002.

“ Physical Design and Automation of VLSI systems”.One Step approach.Click Skew Problem.Linear Programming Approach Timing Driving Routing: Delay Minimization. Floor planning: Rectangular dual floor planning. Sarafzadeh.Single Layer Global Routing. The Benjamin Cummins Publishers. Routing in FPGA: Array based FPGA. Wong.placement by simulated annealingpartitioning placement.Other issues in minimization UNIT V SINGLE LAYER ROUTING.co m .line searching.simulated annealing.hierarchial approaches.K.Steiner trees Global Routing: Sequential Approaches.Row based FPGAs UNIT IV PERFORMANCE ISSUES IN CIRCUIT LAYOUT 9 Delay Models: Gate Delay Models.Buffered Clock Trees. Minimization: constrained via Minimizationunconstrained via Minimization.Wein Burger Arrays.Gate matrix layout.partition with capacity and i/o constrants. Kernighan-Lin HeuristicRatiocut.force directed method.Transistor chaining. Lorenzatti.Switch box routing.hierarchial approach.Delay in RC trees.Integer Linear Programming Detailed Routing: Channel Routing. Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates.Floor plan sizingPlacement: Cost function. TOTAL: 45 REFERENCES: 1.1D compaction.Wire length and bend minimization technique – Over The Cell (OTC) RoutingMultiple chip modules(MCM). Preas M.field programmable gate array(FPGA)-layout methodologiesPackaging-Computational Complexity-Algorithmic Paradigms UNIT II PLACEMENT USING TOP-DOWN APPROACH 9 Partitioning: Approximation of Hyper Graphs with Graphs.Programmable Logic Arrays. “An Introduction to VLSI Physical Design”. CELL GENERATION AND COMPACTION 9 Planar subset problem(PSP).Weight based placement. UNIT III ROUTING USING TOP DOWN APPROACH 9 Fundamentals: Maze Running. Mc Graw Hill International Edition 1995 2. C. ht tp :// an n au ni vp or 24 ta l.Models for interconnected Delay.module placement on a resistive network – regular placementlinear placement.Single Layer detailed Routing.Randomised Routing. Timing – Driven Placement: Zero Stack Algorithm.b lo g sp ot . 1998.multicommodity flow based techniques.2D compaction.VL9257 PHYSICAL DESIGN OF VLSI CIRCUITS LTPC 3003 UNIT I INTRODUCTION TO VLSI TECHNOLOGY 9 Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining.

CRC press. John R.”Genetic Algorithm for VLSI Design. Vellasco. Forrest H.R.Koza.E. May 1999. Marley Maria B. “Genetic Programming Automatic programming and Automatic Circuit Synthesis”.Bennett III.Mapping for FPGA. ht tp :// an n au ni vp REFERENCES: or 25 .1977. David Andre . Prentice Hall. Sue Ellen Haupt.MRudnick.partitioning-automatic placement. Layout and Test automation. 4. 1st Edition Dec 2001.VL9258 GENETIC ALGORITHMS AND THEIR APPLICATIONS LTPC 3003 9 UNIT I Introduction. Marley Maria Bernard Vellasco “Evolution Electronics: Automatic Design of electronic Circuits and Systems Genetic Algorithms”. 2. Macro Aurelio Pacheco. “Practical Genetic Algorithms” Wiley – Interscience. 3.Automatic test generationPartitioning algorithm Taxonomy-Multiway Partitioning UNIT III 9 Hybrid genetic – genetic encoding-local improvement-WDFR-Comparison of CasStandard cell placement-GASP algorithm-unified algorithm. Randy L.fitness function-GA vs Conventional algorithm. Morgan Kufmann. ta l.Layout and test Automation”. 1st Edition . Ricardo Sal Zebulum.co m Total = 45 1.b lo g sp ot . UNIT IV 9 Global routing-FPGA technology mapping-circuit generation-test generation in a GA frame work-test generation procedures.routing technology. Haupt.GA Technology-Steady State Algorithm-Fitness Scaling-Inversion UNIT II 9 GA for VLSI Design. Pinaki Mazumder.1998. UNIT V 9 Power estimation-application of GA-Standard cell placement-GA for ATG-problem encoding.

UNIT III HIGH PERFORMANCE RISC ARCHITECTURE – ARM 9 Organization of CPU – Bus architecture –Memory management unit . 1.b lo g sp ot . 7.Thumb Instruction set. Programming and Interfacing “ . UNIT II HIGH PERFORMANCE CISC ARCHITECTURE – PENTIUM 9 CPU Architecture.B.B. UNIT V PIC MICROCONTROLLER 9 CPU Architecture – Instruction set – interrupts. UNIT IV MOTOROLA 68HC11 MICROCONTROLLERS 9 Instruction set addressing modes – operating modes.addressing modes – Programming the ARM processor.Timers. 5.Peatman . PHI. Valvano "Embedded Microcomputer Systems" Thomson Asia PVT LTD first reprint 2001. 8.A/D Converter –PWM and introduction to C-Compilers.” Pearson Education .” The Intel Microprocessors Architecture . 1997.2002.Antonakos .Interrupsystem. John .H.Miller . “ The Pentium Microprocessor ‘’ Pearson Education .RTC-Serial Communication Interface – A/D Converter PWM and UART. 4.Breg.Inc. Prentice hall. Daniel Tabak .. 6.” An Introduction to the Intel family of Microprocessors ‘’ Pearson Education 1999. James L. 2003. ht tp :// an n au REFERENCES: ni vp or 26 ta l.co m . ‘’ ARM System –On –Chip architecture “Addision Wesley . Gene . ‘’ Advanced Microprocessors” McGraw Hill.pipelining –the instruction pipeline – pipeline hazards – instruction level parallelism – reduced instruction set –Computer principles – RISC versus CISC.Bus Operations – Pipelining – Brach predication – floating point unitOperating Modes –Paging – Multitasking – Exception and Interrupts – Instruction set – addressing modes – Programming the Pentium processor.” Micro Computer Engineering .I2C Interfacing –UART. James L. Antonakos . “ Design with PIC Microcontroller . 1995 2.ARM instruction set. 3. Barry. 2000. 1997.VL9259 ADVANCED MICROPROCESSORS AND MICROCONTROLLERS LTPC 3003 UNIT I MICROPROCESSOR ARCHITECTURE 9 Instruction Set – Data formats –Addressing modes – Memory hierarchy –register file – Cache – Virtual memory and paging – Segmentation. Steve Furber .

Memory Annihilation of Structured Maps in BAMS – Continuous BAMs – Adaptive BAMs – Applications ADAPTIVE RESONANCE THEORY: ht tp :// an n au ni vp or 27 ta l.EM Algorithm – Applications of EM Algorithm to HME Model NEURODYNAMICS SYSTEMS: Dynamical Systems – Attractors and Stability – Non-linear Dynamical SystemsLyapunov Stability – Neurodynamical Systems – The Cohen-Grossberg Theorem. UNIT IV 9 ATTRACTOR NEURAL NETWORKS: Associative Learning – Attractor Neural Network Associative Memory – Linear Associative Memory – Hopfield Network – Content Addressable Memory – Strange Attractors and Chaos . Support Vector Machines: Optimal Hyperplane for Linearly Separable Patterns and Nonseparable Patterns – Support Vector Machine for Pattern Recognition – XOR Problem .AP9252 NEURAL NETWORKS AND ITS APPLICATIONS LTPC 3003 9 UNIT I BASIC LEARNING ALGORITHMS Biological Neuron – Artificial Neural Model .Error Performance of Hopfield Networks .Applications of Hopfield Networks – Simulated Annealing – Boltzmann Machine – Bidirectional Associative Memory – BAM Stability Analysis – Error Correction in BAMs .∈-insensitive Loss Function – Support Vector Machines for Nonlinear Regression UNIT III 9 COMMITTEE MACHINES: Ensemble Averaging .Applications: XOR Problem – Image Classification.Learning in Radial Basis Function Networks .Beamforming – Memory – Adaptation .Boltzman Learning – Supervised and Unsupervised Learning – Learning Tasks: Pattern Space – Weight Space – Pattern Association – Pattern Recognition – Function Approximation – Control – Filtering . UNIT II 9 RADIAL-BASIS FUNCTION NETWORKS AND SUPPORT VECTOR MACHINES: RADIAL BASIS FUNCTION NETWORKS: Cover’s Theorem on the Separability of Patterns .Exact Interpolator – Regularization Theory – Generalized Radial Basis Function Networks .Boosting – Associative Gaussian Mixture Model – Hierarchical Mixture of Experts Model(HME) – Model Selection using a Standard Decision Tree – A Priori and Postpriori Probabilities – Maximum Likelihood Estimation – Learning Strategies for the HME Model .Types of activation functions – Architecture: Feedforward and Feedback – Learning Process: Error Correction Learning –Memory Based Learning – Hebbian Learning – Competitive Learning .co m .Statistical Learning Theory – Single Layer Perceptron – Perceptron Learning Algorithm – Perceptron Convergence Theorem – Least Mean Square Learning Algorithm – Multilayer Perceptron – Back Propagation Algorithm – XOR problem – Limitations of Back Propagation Algorithm.b lo g sp ot .

2003. and Mark Beale. Total: 45 ht tp :// an n au ni vp 1.Solving Noise-Saturation Dilemma – Recurrent On-center – Off-surround Networks – Building Blocks of Adaptive Resonance – Substrate of Resonance Structural Details of Resonance Model – Adaptive Resonance Theory – Applications UNIT V 9 SELF ORGANISING MAPS: Self-organizing Map – Maximal Eigenvector Filtering – Sanger’s Rule – Generalized Learning Law – Competitive Learning . Applications. New Delhi.b lo g sp ot . “Neural Networks: A Classroom Approach”. New Delhi. 2ed. Delhi. James A.co m REFERENCES: . or 28 ta l..Hagan. 2004. 2001. 4. Pearson Education (Singapore) Private Limited.Vector Quantization – Mexican Hat Networks Self-organizing Feature Maps – Applications PULSED NEURON MODELS: Spiking Neuron Model – Integrate-and-Fire Neurons – Conductance Based Models – Computing with Spiking Neurons. Howard B. Satish Kumar.Noise-Saturation Dilemma . Freeman and David M. 2003. Simon Haykin. “Neural Networks: A Comprehensive Foundation”. 3. 2. Skapura. Delhi. Martin T. “Neural Network Design”. Demuth. Tata McGraw-Hill Publishing Company Limited. Thomson Learning. “Neural Networks Algorithms. Addison Wesley Longman (Singapore) Private Limited. and Programming Techniques.

Prentice Hall PTR. F.placement physical design flow –global routing . System-on-a-Chip Design and Test.circuit extraction DRC.Altera MAX 5000 and 7000 . Rajsuman.Clock & Power inputs .Actel ACT .CFI design representation.Half gate ASIC -Schematic entry . Addison -Wesley Longman Inc. 3. 1999.FPGA partitioning . FPGA-Based System Design. 2004. Prentice Hall PTR. PLACEMENT AND ROUTING 9 System partition .automatic test pattern generation. FLOOR PLANNING.static RAM .Low level design language .Combinational Logic Cell – Sequential logic cell . 1997. 2003.Altera MAX DC & AC inputs and outputs .S .Transistor Parasitic Capacitance.PREP benchmarks .Transistors as Resistors ..detailed routing .EPROM and EEPROM technology . . M. ht 29 .b UNIT IV LOGIC SYNTHESIS.Xilinx EPLD . 2. From ASICs to SOCs: A Practical Approach. UNIT II PROGRAMMABLE ASICS.VL9261 ASIC DESIGN LTPC 3003 UNIT I INTRODUCTION TO ASICS. UNIT III tp :// an n au ASIC CONSTRUCTION.types of simulation -boundary scan test .Xilinx I/O blocks.partitioning methods . 2000. 5. Nekoogar. Timing Verification of Application-Specific Integrated Circuits (ASICs).co m TOTAL: 45 REFERENCES: 1.Altera MAX 9000 . PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY 9 Actel ACT -Xilinx LCA . R. Wayne Wolf. SIMULATION AND TESTING 9 Verilog and logic synthesis -VHDL and logic synthesis .CMOS transistors CMOS Design rules . CMOS LOGIC AND ASIC LIBRARY DESIGN 9 Types of ASICs .PLA tools -EDIF.Logical effort –Library cell design . Farzad Nekoogar and Faranak Nekoogar.Library architecture .Smith. 4. "Application Specific Integrated Circuits. CA: Artech House Publishers.Logic Synthesis .Altera FLEX –Design systems .special routing . Santa Clara.floor planning .J. PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC I/O CELLS 9 Anti fuse . lo g sp ot PROGRAMMABLE ASIC INTERCONNECT. Prentice Hall PTR.Data path logic cell .Xilinx LCA –Altera FLEX .Design flow .fault simulation . ni vp or UNIT V ta l.

John Wiley & Sons. John Wiley & Sons. Exploratory data analysis and proportional hazards modeling. Electronic system reliability prediction. Design analysis methods – quality function deployment. UNIT IV RELIABILITY TESTING AND ANALYSIS 9 Test environments. quality and safety. UNIT II RELIABILITY PREDICTION. specifying reliability. fault tolerance. 2. software structure and modularity.probability plotting techniques – Weibull. Lewis. hardware/software interfaces. State space Analysis. prediction and measurement.petric Nets. CUSUM charts. Reliability prediction. Klinger. Pareto analysis. reliability demonstration. Monte carlo simulation. software reliability.co m TOTAL: 45 REFERENCES: 1. New York. Reliability modeling.hazard. Hobbs. 4. Reliability in electronic system design. UNIT V MANUFACTURE AND RELIABILITY MAQNAGEMENT 9 Control of production variability. Production failure reporting. Patrick D.b lo g sp ot . MODELLING AND DESIGN 9 Statistical design of experiments and analysis of variance Taguchi method. organization for reliability. "AT & T Reliability Manual". 3. standard for reliability. 5th Edition. failure modes. "Accelerated Reliability Engineering . 1996. preventive maintenance strategy. extreme value . Safety margin and loading roughness on reliability. Block diagram and Fault tree Analysis . reliability and costs.T. failure reporting. 1998. Design for maintainability. Practical Reliability Engineering. Acceptance sampling. component types and failure mechanisms. UNIT III ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY 9 Reliablity of electronic components. software errors. New York.NE9251 RELIABILITY ENGINEERING LTPC 3003 UNIT I PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE 9 Statistical distribution . Von Nostrand Reinhold. Quality control and stress screening. O’Connor. David Newton and Richard Bromley. effects and criticality analysis. load strength analysis.HALT and HASS". Maintenance schedules. tp :// an n au ni vp or ta l. "Introduction to Reliability Engineering". 2002 David J. Fourth edition. 2nd Edition. 2000. Accelerated test data analysis. binomial data. Analysis of load – strength interference . Wiley International. statistical confidence and hypothesis testing . Menendez. reliability growth monitoring. testing for reliability and durability. Yoshinao Nakada and Maria A. ht 30 . Integrated reliability programmes . Gregg K.

EN. 5.. 3. Common mode and ground loop coupling . “Principles of Electromagnetic Compatibility”. EMI Rx and spectrum analyzer. UNIT IV EMC DESIGN OF PCBS 9 Component selection and mounting. C. PCB trace impedance. UNIT V EMI MEASUREMENTS AND STANDARDS 9 Open area test site.AP9256 ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN LTPC 3003 UNIT I EMI/EMC CONCEPTS 9 EMI-EMC definitions and Units of parameters.Paul. IEC. TOTAL: 45 1. Radiation Hazards. Grounding. Conducted and Radiated EMI Emission and Susceptibility. “Handbook of EMI/EMC” .White Consultant Incorporate. Bonding. Power distribution decoupling. Common ground impedance coupling . VIAs connection. Vol I-V. Inc. John Wiley and Sons. Grounding. Artech house. Newyork. Newyork.”Introduction to Electromagnetic Compatibility” . radiated and transient coupling. 1996. Measurements and Technologies”. UNIT II EMI COUPLING PRINCIPLES 9 Conducted. “Engineering EMC Principles. 1986. Filtering. Signal control.”Noise Reduction Techniques in Electronic Systems”. Isolation transformer. Tx /Rx Antennas. Don R. 2. John Wiley and Sons.b lo g sp ot . Field to cable coupling . FCC. Injectors / Couplers. Transient EMI.co m . Routing. Sensors. Cross talk control.P. IEEE Press. Differential mode coupling . 4. 1988. TEM cell. Zoning. Sources and victim of EMI. 1992. EMI test shielded chamber and shielded ferrite lined anechoic chamber.Kodali. Norwood. V. 1988. Civilian standards-CISPR.Ott.R. Bemhard Keiser.J. and coupling factors. UNIT III EMI CONTROL TECHNIQUES 9 Shielding. ht tp :// an n REFERENCES: au ni vp or 31 ta l. Near field cable to cable coupling. Transient suppressors. Military standards-MIL461E/462. ESD. Terminations. Cable routing. Power mains and Power supply coupling. Henry W. A Wiley Inter Science Publications. 3rd Ed. cross talk .

R. Music production – Auditory perception – Anatomical pathways from the ear to the perception of sound – Peripheral auditory system – Psycho acoustics UNIT II TIME DOMAIN METHODS FOR SPEECH PROCESSING 8 Time domain parameters of Speech signal – Methods for extracting the parameters Energy.Analysis synthesis systems. UNIT IV LINEAR PREDICTIVE ANALYSIS OF SPEECH 10 Formulation of Linear Prediction problem in Time Domain – Basic Principle – Auto correlation method – Covariance method – Solution of LPC equations – Cholesky method – Durbin’s Recursive algorithm – lattice formation and solutions – Comparison of different methods – Application of LPC parameters – Pitch detection using LPC parameters – Formant analysis – VELP – CELP. hidden Markov model – Music analysis – Pitch Detection – Feature analysis for recognition –Automatic Speech Recognition – Feature Extraction for ASR – Deterministic sequence recognition – Statistical Sequence recognition – ASR systems – Speaker identification and verification – Voice response system – Speech Synthesis: Text to speech. Quatieri – Discrete-time Speech Signal Processing – Prentice Hall – 2001. UNIT V APPLICATION OF SPEECH SIGNAL PROCESSING 10 Algorithms: Spectral Estimation. 4. L. I. voice over IP.co m .H. J. Singapore.Witten – – Principles of Computer Speech – Academic Press – 1982 ht tp :// an n au ni vp or 32 ta l. . Ben Gold and Nelson Morgan.Flanagan – Speech analysis: Synthesis and Perception – 2nd edition – Berlin – 1972 5. HOMOMORPHIC SPEECH ANALYSIS: Cepstral analysis of Speech – Formant and Pitch Estimation – Homomorphic Vocoders.W.b lo g sp ot . dynamic time warping.L.Schaffer – Digital Processing of Speech signals – Prentice Hall -1978 3. John Wiley and Sons Inc.VL9264 DIGITAL SPEECH SIGNAL PROCESSING LTPC 3003 UNIT I MECHANICS OF SPEECH 8 Speech production mechanism – Nature of Speech signal – Discrete time modelling of Speech production – Representation of Speech signals – Classification of Speech sounds – Phones – Phonemes – Phonetic and Phonemic alphabets – Articulatory features. Speech and Audio Signal Processing. 2004 2. REFERENCES: 1.Rabiner and R.Phase vocoder— Channel Vocoder. Average Magnitude – Zero crossing Rate – Silence Discrimination using ZCR and energy – Short Time Auto Correlation Function – Pitch period estimation using Auto Correlation Function UNIT III FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING 9 Short Time Fourier analysis – Filter bank analysis – Formant extraction – Pitch Extraction – Analysis by Synthesis.

Filter design UNIT IV ADSP PROCESSORS 9 Architecture of ADSP-21XX and ADSP-210XX series of DSP processors.Venkataramani and M.VL9265 DSP PROCESSOR ARCHITECTURE AND PROGRAMMING LTPC 3003 UNIT I FUNDAMENTALS OF PROGRAMMABLE DSPs 9 Multiplier and Multiplier accumulator – Modified Bus Structures and Memory access in PDSPs – Multiple access memory – Multi-port memory – VLIW architecture.Architecture of TMS320C6X .co m TOTAL: 45 REFERENCES: 1. 2. Code Composer studio . UNIT II TMS320C5X PROCESSOR 9 Architecture – Assembly language syntax . Operation – Block Diagram of DSP starter kit – Application Programs for processing real time signals. FFT calculation. Analog Devices.Operation – Block Diagram of DSP starter kit – Application Programs for processing real time signals – Generating and finding the sum of series. Motorola.Pipelining – Special Addressing modes in P-DSPs – On chip Peripherals.b lo g sp ot . ht 33 .Instruction sets . UNIT V ADVANCED PROCESSORS 9 Architecture of TMS320C54X: Pipe line operation.Pipeline structure.Bhaskar. “Digital Signal Processors – Architecture. Convolution of two sequences. 2003. New Delhi.Addressing modes – Groups of addressing modes. User guides Texas Instrumentation. Programming and Applications” – Tata McGraw – Hill Publishing Company Limited. UNIT III TMS320C3X PROCESSOR 9 Architecture – Data formats . B. tp :// an n au ni vp or ta l.Architecture of Motorola DSP563XX – Comparison of the features of DSP family processors.Addressing modes and assembly language instructions – Application programs –Filter design.Addressing modes – Assembly language Instructions .

Case studies – Capacitive accelerometer. Microaccelorometers and Micro fluidics. gap and finger pull up. Thermo mechanics – actuators.co m .” MEMS & Micro systems Design and Manufacture” Tata McGraw Hill. Stephen Santuria. ht tp :// an n au ni vp or 34 ta l. MEMS materials. Micro actuation. Artech House. New Delhi. MEMS scanners and retinal scanning display. Micro sensors.” The MEMS Handbook”.System design basics – Gaussian optics. Nadim Maluf. torsional deflection. resolution. Mohamed Gad-el-Hak. Electro static actuators. 4. CRC press Baco Raton. gap closers.2000. Feed back systems. Kluwer publishers. Circuit and system issues. TOTAL: 45 REFERENCES: 1.” Microsystems Design”. Stress. rotary motors. MEMS with micro actuators. 2002. . inch worms.” An introduction to Micro electro mechanical system design”.VL9266 INTRODUCTION TO MEMS SYSTEM DESIGN LTPC 3003 UNIT I INTRODUCTION TO MEMS 9 MEMS and Microsystems. Modelling of MEMS systems. Case studies. editor. Noise . Micro fabrication UNIT II MECHANICS FOR MEMS DESIGN 9 Elasticity. Electromagnetic actuators. Resonance. Comb generators. Bending of thin plates. Tai Ran Hsu. 2000. Miniaturization. 2000 3. Peizo electric pressure sensor. force and response time. matrix operations. UNIT V INTRODUCTION TO OPTICAL AND RF MEMS 9 Optical MEMS. Digital Micro mirror devices. electro static instability. case study – Capacitive RF MEMS switch. strain and material properties. performance issues. Mechanical vibration. Fracture and thin film mechanics. Surface tension. UNIT III ELECTRO STATIC DESIGN 9 Electrostatics: basic theory. bistable actuators. Typical products. CAD for MEMS.b lo g sp ot . 2. UNIT IV CIRCUIT AND SYSTEM ISSUES 9 Electronic Interfaces. RF Memes – design basics. Spring configurations.

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