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AN AREA-EFFICIENT LOW-POWER SC INTEGRATOR

FOR VERY HIGH RESOLUTION ADCS


Hashem Zare-Hoseini, M. Yaser Azizi and Omid Shoaei
IC Lab., Electrical & Computer Engineering Depament, University of Tehran, Iran
Emails: h.zhoseini@ece.ut.ir, yazizi@msn.com, oshoaei@ut.ac.ir

ABSTRACT PI

<&i.
In this paper a very area-efficient low-noise low-power '.
correlated double sampled integrator has been presented. A fully
differential class AB opamp with a preamplifier is designed with
gain of 85dB, bandwidth of I2 Mradls and overall input referred
noise floor of -171dB. For attenuating the integrator's opamp
"* L,
thermal noise, the input tnnswnductance is kept as large as
needed and also the bandwidth of the op-amp ir decreased as s.-s-n I.! ,-*.aPb..ee,
much as oossible without the need for larce - commsation R
capacitors as in the ordinary topologies are used. The integrator
is used in the fmnt-end of a 24 bit, forthmder single-loop Delta
Sigma modulator for a bandwidth of 1000 Radk. The integator
power consumption is only 2.8 mW with a single 3.0V supply in
I*
0.6pm CMOS technology.
Figure 1. (a) A conventional CDS integrator, (b) Contribution o f
1. INTRODUCTION its input switches in KTIC noise.
High order Deka Sigma (OS) modulators are the most suitable
analog to digital converters for low frequency, high-resohttion where OL, OSR and ydenote the overload factor, the
applications such as biomedical instmmentation and remde
oversamplmg ratio and the noise coefficient deanding on the
seismic monitoring [ I ] due to their linearity, robust analog
number of the contributing capacitors in the input referred KT/C
implementation and noise shaping (21.
noise respectively. Equation ( I ) shows that with an overload
The major constraint issue to obtain a resolution above 120dB in factor of about -1.24dB and y = 3, a C,equal to 0.9nF satisfies
SC modulators is noise including KTC, li/and op-amp thermal 24hit resolution. Also in equation ( I ) it is assumed that the op-
noise in the frontcnd of the modulators. For this reason and the amp thermal noise is as low as possible, below -171dB, to satisfy
linearity constraints. the major power consumption (about more 24hit resolution in a bandwidth of IWORadk [31. Moreoverthe
than 35%) of a high resolution DS m h l a t o r is due to the fmt CDS technique attenuates slrongly @-amp's offset and Ilf noise.
integrator [I] [Z]. In order to achieve a 24-bit resolution in the By using old CDS integrators such as the integrators used in [I]
IOOORadis bandwidth, a filly differential mohlator requires and [ 2 ] , the equation ( I ) obliges to use very large sampling and
sampling capacitors in the order of 0.9nF in the first integrator. integration capacitors due to the KT/Cnoise constaint. Fig. I(a)
This consequently in ordinary integrators leads to a very large shows a typical CDS integrator used in 121. During the sampling
area and power consumption in the fust opamp. Using four off- phase capacitor C, samples the thermal noise of the switch S I
chip capacitors for the first integrator still requires high power while in the integration phase it samples the thermal noise of the'
consumption in the tint amplifier and also causes the matching switch S1 as demonstrated in Fig. I@). It is clearly seen that
and parasitic capacitance problem. In the proposed COS keeping the input referred noise floor at a very low level e.g. -
(correlated double sampling) integrator two large capacitors are 171dB in our case, leads to use a large sampling capacitor and
well embedded to strongly attenuate the input KT/C noise consequently a large integration capacitor Ch. Due to the very
without using any large sampling or integrating capacitors. Also large amount of area and power consumption in the op-amp, it
using these large capacitors doesn't cause the matching and will be an unqtimized architecture to use the conventional CDS
parasitic capacitance problem. Therefore, it can be easily integrator strategies.
designed with a little power and area consumption. Moreover it
uses the preamplifier with a class AB configuration to redum the 3. SWITCHES NOISE
size of compensation capacitor. In the oresented integrator architecture, shown in Fic. 2, for
solving ;he KTIC noise problem, two large capacitors (en & Cj)
2. INTEGRATOR CONFIGURATION are well incorporated to decrease the noise of the input switches
For the fully differential DS modulator with the f r o n t a d as'much as needed. Thev are well suited where all switches that
btegrator, si& to noise ratio'is given by: contribute major KTIC noise meet them in their equivalent RC.
Therefore there is no need to use large sampling and mtegrating
. SNR = l0Log
0 . 5 ( 2 . O L .Vre/)'
y - kT/(C, . OSR )
I (1) capacitors. Moreover C,, & Cpcan be off-chip capacitors with no
matching and parasitic problem. The parasitic capacitors due to

0-7803-7979-9/03/$17.0002003 IEEE 365


Figure 2. The proposed very low-noise CDS integrator with the 0 , 2 1 4 5 1
F"qG". .lo'
small sampling and integrating capacitors.
Figure 3. The contributions of different sources in the
pads are in parallel with the inplt or the voltage references and output noise PSD of the integrator shown in Fig. (2). For each
clcarly have no effect. For attenuating the effects of the offset case, the normalized noise source is chosen.
and lifnoise, CDS is also used in this integrator. A precise
mntribution on the overall noise PSD. From the above
analysis for switches and op-amp noise power spectral density
discussion, it is clearly seen that the major conslraint is KTlC
(PSD) transfer function is performed. If S4NTF and S3NTF
represent the switch S4 and the switch S3 (in Fig. 2) noise PSD noise that leads to use a large C , and also a very IOWnoise op-
transfer funcnons, respectively, the analysis shows:
amp.
I
4. SETTLING NOISE
The settling noise in the sampling and integrating phases due to
the resistance of switches, the fmite gainhandwidth and the
slew-rate of the op-amp can be a big constraint in a very hiph-
resolution application.
Fig. 4 demonstrated the equivalent model of the inlegator of Fig.
2 in me sampling and integrating phase for settling analysis. In
the high-resolution applications, the integrator settles in fait
regime wherein the settling time consant ( T ) is smaller than an
whsR K = C, IC, and A represents the opamp fmite open-loop upper limit, and the slew-rate, S , is larger than a lower limit [SI.
paio. A similar analysis can be carried out for the offset and the Using class AB configuration guaranties that the slewing never
inpt-referred noise PSD transfer function of the opamp that occurs and the settling process is linear. Assuming the open loop
yislds: transfer function of the op-amp as a single pole response of iUle
A0
formA(jw) = =, input voltage sampled on
I+ K -K G - Z - '

OPNF =
I+-
R
(4) capacitor c, in the sampling phase with the transfer function of:
I f K
1+-- (1 + L I Z -'
A A

\ J
Farm the equations (2) and (3). it is clear that the switches S3
and S4 have no simificant effect on the total output noise PSD of
the integrator. Also, the equation (4) shows that CDS power
ban& fundion places double zems at DC frequency that
E l -
JwRoniCs
For A
c,~ >> I . ~ (5)
cancels out the offset and sub-tially attenuates the Ifnoise
mmponent. The effect of aliasing on the Ifnoise is not very
dramatic [4]because of its low comer frequency in the MOS
amplifiers that is lower enough than the sampling frequency. The where 0, is the opamp unity gain bandwimh.
contribution of the opamp thermal noise on the total output
noise PSD is significant because of its fold-over component. As In the integrating phase, the transfer function of the last sampled
it is seen by the equation (4). the CDS technique is not the voltage on c, and reference voltage are:
efficient technique for reducing opamp thermal noise [4]. The
output PSD of the integrator r m h m g from the switch S3, the
switch S4 and the opamp thermal noise PSD is shown in Fig. 3.
The plm+ result confrms the above discussion. As a result, a
very low noise o p m p is designed with a decreased bandwimh
10 around 6 times of the input signal bandwidth for reducing its

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Ssroplini Phase (1) 1alprafiomPh.sr (1) cI

v
Figure 4. The simplified equivalent transient models ofthe integrator shown in Fig. 2 in the sampling and the integrating phases.

allowable unity gain bandwidth demands a very large


compensation capacitor C, and C,, in the conventional two-stage
and single-stage topologies respectively. The same calculation as
&ne in equation (I), for the opamp used in the f K s i integrator of
a 24-bit modulator having a bandwidth of IOOORadis results in a
compensation capacitor of about 500pF with the assumption of
0, 6. O s ~ . ( 2 0 ,where
) 0,is the input signal bandwidth.

Adding a preamplifier to achieve these specifications with a


small compensation capacitor seems to be an attractive option.
The idea of adding a low gain preamplifier is used in [6] for a
high-speed low-power example. Besides a cascade stage used
there cannot be a good candidate because of its limited output
swing, the compensation topology and the non-linearity coming
from its slew rate limitation effect. Taking into account the abave
requirements and issues, a viable solution is to use a single-stage
It is apparent from equations (5). (6) and (7) that m the two class AB op-amp with a moderate gain preamplifier and using
phases, the equivalent time constant is due to the input equivalent the output capacitance forthe compensation as shown m Fig. 7(a)
RC and also the unity gain bandwidth o f the op-amp. Even for this really tweslage op-amp. The unity-gam bandwidth of
though making use of the fully differential approach significantly this op-amp is approximately given by:
reduces the error of the senling time because of the linear - g1. 'gm6
(8)
settling, the signal source input resistance is kept below lCQa I -
gm,.CO$
in sampling phase and also the large-size input switches are used
Targeting a very low thermal noise opamp imposes a very high
m our simulations. Moreover, the inverse of the quivalent time
constant of the op-amp should be at least six times of the m p t transistor transconductance (g,, ). However equation (8)
sampling frequency. shows that the compensation capacitor can be decreased with the
g m , / p , factor proportionally. Also, increasing gmnigme
5. OP-AMP CONFIGURATION increases the total input referred thermal noise as shown in Fig 6.
Considering noise, power, area and the bandwidth of the front- Talang into account the contribution of MI, M3 and M6 in the
end op-amp, designing such an op-amp with a little power and overall thermal noise, g,, is chosen 20 times bigger than ga6
area consumption is a difficult task because of a very large
compensation capacitance needed to reduce the amplifier to allow the reduction of the camansation capacitor
bandwidth. The merits of two-stage and single-stage amplifier proportionally and to set the operating point at the comer of the
topologies are examined. The unity gain bandwidth of limited noise floor shown in Fig. 6. It can also be observed that
conventional compensated techniques of a two-stage and a the reduction of the compensation capacitor happens in the
single-stage op-amp shown in Fig. 5 are about gm,lC,and
gm,ICmurespectively. Assuming that the thermal noise of our op-
amps is dominated by the noise of their input differential-pair,
the desired very low noise op-amp requires a very high inplf
transconductance (&I). As a result, achieving a minimum

2 Stage I Stage

Figure 5. The simplified equivalent mall-signal models for a Figure 6. The size of the cnmpenstion capacitor and the input
single-stage and a two-stage opamp. referred thermal noise floor vs. gm,l g m 6 .

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Figure 1. (a) The fully differential class AB opampI with a preamplifier, (b) Common-mode feedback circuit
cxpense of reduction in the achievable dc-gain. To improve the
dc-gain, the output resistance should be increased by using long
channel lransistors in the output stage of the main amplifier as
well as the common- mode feedback circuit shown in Fig. 7@).
A low quiescent current in the output branch is also required.
Due lo the low-frequency low-power fealure required in our
application, the input transistors MI and M2 are operating near
the sublhreshold region [7]. Noise on the bottom supply tail
appears as a commonmode input to the second stage of the op-
amp and is thus attenuated by the common-mode rejection of that
sfage. Also using the class AB configuration in our work
guaranties that the slew-rate never occurs and the settling process ~m ' , ' , " , , , ,
0 I m m m u o M s m I m m m , m
inr"."rrl*ii
is linear.
Figure 9. The output PSD of the modulator shown in Fig. 7 for a
6. SIMULATION RESULTS single-tone at o =300Rads.
The proposed CDS integrator is used in the f r o n t a d of the
single loop fanh+rder DS modulator s h a m in Fig. 8 . Taking achieve 24 bit resolution in a bandwidth of 1000 Radis with
into account most of the non-idealities, such as sampling jitter, oversampling ratio of 1024 and voltage references o f f I .S Volts.
clock feed-through, charge injection, KT/C noise, op-amps' fmite The integrator h a s a very low op-amp thermal and KT/C noi:s, -
gain, bandwidth, slew-rate and limited swing, exhaustive 171db. with no need to large sampling and integrating capacilors.
behavioral simulations that are close models of HSPICE Using a single-stage class AB configuration with a moderate ;gain
simulations a n performed. After behavioral simulations in preamplifier enables us to achieve 85dB dc-gain in a bndwimh
MATLAB, HSPICE transistor level simulations of the circuit of 1 2 M d s with an only 25pF compensation capacitor.
level of Fig. 8 have been performed in a 0 . 6 process~ using
references voltage of f1.5 Volts. The w t p t power spectral 8. REFERENCES
density for a single tone input source is shown in Fig. 9. With the [I] R. M. Naiknaware and T. Fiez, "142dB A I ADC with a
overloadfactorof-I.24dB. the signal tonoise ratio is 1 4 4 dB in lOOnV LSB in a 3V CMOS Process," IEEE,ClCC 20W.
a bandwidth of 1000RadkThe power consumption of the whole [2] P.Bendiscioli, et al., "Design o f a 20 bit, 25mw fourth Order,
mcduhtor is about 8.5mW while the first integrator only Single -Loop Sigmadelta Modulator,'' Proceeding of E E€,
mnsumes 2.8mW. ICECS'97,Cairo, Egyppt, pp.1454-1457, 1997.
[3] H. Zare-Hoseini, et al. "A 144dB. 8.5mW Fourth-Order,
7. CONCLUSION Single Loop Delta-Sigma Mcdulatoi' To be presented at
This paper presents a very low-noise, low-power low-ana CDS VLSI-TSA,Taiwan, 2603.
integrator u x d in the f r o n t a d of a forth order modulator to [4] C. C. Enz and G. C. Temes. "Circuit Techniques for
Reducing the Effect of op-amp Imperfections: Autozeroing,
Conelated Double Sampling, and Chopper Stabilization,"
Pmceedings of the IEEE, vol. 84, no. 11, November 1996.
[5] S . Rabii, and B. A. Wooley, "A 1.8-V Digital-Audio Sigma-
Delfa Modulator in 0.8-pm CMOS," IEEE J. Solid-!itate
Circuits, Vol. 32, No. 6, June 1997.
[6] T. B. Cho, and P. R. Gray, "A lob, 20 Msampleis, 3SmW
Pipeline A/D Converter," IEEE JSSC, Vol. 30,No. 3, 1995.
[7] D. Johns, and K. Martin, "Analog lnteglated Circud design,"
John Wiley& Sons, 1997,ISBN 0471-14448-7.

Figure 8. ? l e forth ordersingle loop single bit modulator.

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