ANJUMAN COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR

DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION ENGG.

CAT - I : 16th AUGUST, 2018

Sem : 7 Section: A Course Code : BEETE704 Total Marks : 30 Time : 1.5 hour

Program : B.E. ETC Course Name : Advanced Digital System Design

CO: Course Outcome number (1-6), Level: Revised Bloom’s Taxonomy Level (1-6)

Answer any one (10 Marks)

Q.
CO Level Question
No.
1 2 1 Explain various levels of abstraction in VHDL (10)

1 2 2 Expain VHDL development flow with suitable flow chart (10)

Answer any one (10 Marks)

A:2 A. Explain various data objects in VHDL with suitable

examples (4)
2 B:3 3 B. Develop VHDL code for a 3:8 decoder using selected signal
assignment statement (6)
A:2 A. Write a short note on (i) Entity (ii) Architecture (4)
2 4 B. Develop VHDL code for 8:3 Priority Encoder using
B:3 conditional signal assignment statement (6)

Answer any one (10 Marks)

A:3 A. Develop VHDL code for Ripple Carry Adder circuit using
3 5 generate statement (5)
B:3 B. Develop the test bench for 4:1 multiplexer (5)
A:3 A. Write the structural description of 16:1 mux using 4:1 mux
using VHDL (5)
3 6
B:3
B. Develop VHDL Code for BCD to 7-Segment Decoder (5)

ALL THE BEST

 ANJUMAN COLLEGE OF ENGINEERING & TECHNOLOGY, NAGPUR
DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION ENGG.
CAT - I : 16th AUGUST, 2018

Sem : 7 Section: A Course Code : BEETE704 Total Marks : 30 Time : 1.5 hour

Program : B.E. ETC Course Name : Advanced Digital System Design

CO: Course Outcome number (1-6), Level: Revised Bloom’s Taxonomy Level (1-6)

Answer any one (10 Marks)

Q.
CO Level Question
No.
1 2 1 Explain various levels of abstraction in VHDL (10)

1 2 2 Expain VHDL development flow with suitable flow chart (10)

Answer any one (10 Marks)

A:2 A. Explain various data objects in VHDL with suitable

examples (4)
2 B:3 3 B. Develop VHDL code for a 3:8 decoder using selected signal
assignment statement (6)
A:2 A. Write a short note on (i) Entity (ii) Architecture (4)
2 4 B. Develop VHDL code for 8:3 Priority Encoder using
B:3 conditional signal assignment statement (6)

Answer any one (10 Marks)

A:3 A. Develop VHDL code for Ripple Carry Adder circuit using
3 5 generate statement (5)
B:3 B. Develop the test bench for 4:1 multiplexer (5)
A:3 A. Write the structural description of 16:1 mux using 4:1 mux
using VHDL (5)
3 6
B:3
B. Develop VHDL Code for BCD to 7-Segment Decoder (5)

ALL THE BEST