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Allen and Holberg - CMOS Analog Circuit Design Page I.

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I. INTRODUCTION

Contents

I.1 Introduction
I.2 Analog Integrated Circuit Design
I.3 Technology Overview
I.4 Notation
I.5 Analog Circuit Analysis Techniques

Allen and Holberg - CMOS Analog Circuit Design Page I.0-2
Organization

Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS

Chapter 7 Chapter 8 Chapter 9
CMOS Simple CMOS High Performance
Comparators Opamps Opamps
COMPLEX

CIRCUITS

Chapter 5 Chapter 6
CMOS CMOS
Subcircuits Amplifiers
SIMPLE

Chapter 2 Chapter 3 Chapter 4
CMOS CMOS Device Device
Technology Modeling Characterization
DEVICES

Introduction

Allen and Holberg - CMOS Analog Circuit Design Page I.2-1

I.1 - INTRODUCTION

GLOBAL OBJECTIVES
• Teach the analysis, modeling, simulation, and design of analog circuits
implemented in CMOS technology.
• Emphasis will be on the design methodology and a hierarchical
approach to the subject.

SPECIFIC OBJECTIVES
1. Present an overall, uniform viewpoint of CMOS analog circuit design.
2. Achieve an understanding of analog circuit design.
• Hand calculations using simple models
• Emphasis on insight
• Simulation to provide second-order design resolution
3. Present a hierarchical approach.
• Sub-blocks Blocks Circuits Systems
4. Examples to illustrate the concepts.

Allen and Holberg .2-1 I.CMOS Analog Circuit Design Page I.2 ANALOG INTEGRATED CIRCUIT DESIGN ANALOG DESIGN TECHNIQUES VERSUS TIME FILTERS AMPLIFICATION Passive RLC circuits Open-loop amplifiers 1935-1950 Active-RC Filters Feedback Amplifiers Requires precise definition of time constants (RC Requires precise definition products) of passive components 1978 Switched Capacitor Switched Capacitor Filters Amplifiers Requires precise C Requires precise C ratios and clock ratios 1983 Continuous Time Continuous Time Filters Amplifiers Time constants are Component ratios adjustable are adjustable 1992 ? Digitally assisted analog circuits ? .

2-2 DISCRETE VS.CMOS Analog Circuit Design Page I. and Implementation extraction Parasitics Not Important Must be included in the design Simulation Model parameters well Model parameters vary known widely Testing Generally complete Must be considered testing is possible before the design CAD Schematic capture. simulation.Allen and Holberg . capacitors. layout and routing Components All possible Active devices. PC board simulation. Schematic capture. verification. and resistors . extraction. layout LVS. INTEGRATED ANALOG CIRCUIT DESIGN Activity/Item Discrete Integrated Component Accuracy Well known Poor absolute accuracies Breadboarding? Yes No (kit parts) Fabrication Independent Very Dependent Physical PC layout Layout.

Allen and Holberg .CMOS Analog Circuit Design Page I.2-3 THE ANALOG IC DESIGN PROCESS Conception of the idea Definition of the design Comparison Comparison with design Implementation with design specifications specifications Simulation Physical Definition Physical Verification Parasitic Extraction Fabrication Testing and Verification Product .

CMOS Analog Circuit Design Page I.Allen and Holberg .binary signals time have two amplitude states Designed at the circuit level Designed at the systems level Components must have a continuum Component have fixed values of values Customized Standard CAD tools are difficult to apply CAD tools have been extremely successful Requires precision modeling Timing models only Performance optimized Programmable by software Irregular block Regular blocks Difficult to route automatically Easy to route automatically Dynamic range limited by power Dynamic range unlimited supplies and noise (and linearity) .2-4 COMPARISON OF ANALOG AND DIGITAL CIRCUITS Analog Circuits Digital Circuits Signals are continuous in amplitude Signal are discontinuous in and can be continuous or discrete in amplitude and time .

Allen and Holberg - CMOS Analog Circuit Design Page I.3-1

I.3 TECHNOLOGY OVERVIEW
BANDWIDTHS OF SIGNALS USED IN SIGNAL PROCESSING
APPLICATIONS

Video

Acoustic
Seismic imaging

Sonar Radar

Audio AM-FM radio, TV

Telecommunications Microwave

1 10 100 1k 10k 100k 1M 10M 100M 1G 10G 100G
Signal Frequency (Hz)

Signal frequency used in signal processing applications.

Allen and Holberg - CMOS Analog Circuit Design Page I.3-2

BANDWIDTHS THAT CAN BE PROCESSED BY PRESENT-
DAY TECHNOLOGIES

BiCMOS

Bipolar analog

Bipolar digital logic

MOS digital logic

MOS analog

Optical

GaAs

1 10 100 1k 10k 100k 1M 10M 100M 1G 10G 100G
Signal Frequency (Hz)
Frequencies that can be processed by present-day technologies.

Allen and Holberg - CMOS Analog Circuit Design Page I.3-3

CLASSIFICATION OF SILICON TECHNOLOGY

Silicon IC Technologies

Bipolar Bipolar/MOS MOS

Junction Dielectric PMOS
Isolated Isolated CMOS (Aluminum NMOS
Gate)

Aluminum Silicon Aluminum Silicon
gate gate gate gate

asymmetric Good Implementation Power Dissipation Moderate to high Low but can be large Speed Faster Fast Compatible Capacitors Voltage dependent Good AC Performance DC variables only DC variables and Dependence geometry Number of Terminals 3 4 Noise (1/f) Good Poor Noise Thermal OK OK Offset Voltage < 1 mV 5-10 mV .2-0.5-0.3-4 BIPOLAR VS.Allen and Holberg .CMOS Analog Circuit Design Page I.6 V 0.4 mS (W=10L) Analog Switch Offsets.8-1 V Saturation Voltage 0. MOS TRANSISTORS CATEGORY BIPOLAR CMOS Turn-on Voltage 0.8 V gm at 100 A 4 mS 0.2-0.3 V 0.

Allen and Holberg .3-5 WHY CMOS??? CMOS is nearly ideal for mixed-signal designs: Dense digital logic High-performance analog DIGITAL ANALOG MIXED-SIGNAL IC .CMOS Analog Circuit Design Page I.

enhance. VBS 0 ment.CMOS Analog Circuit Design Page I.n-channel. bulk at most positive supply .Allen and Holberg .4-1 I. enhance- ment. VBS 0 ment. enhance- ment.4 NOTATION SYMBOLS FOR TRANSISTORS Drain Drain Gate Bulk Gate Source Source/bulk n-channel. enhance. bulk at most negative supply Drain Drain Gate Bulk Gate Source Source/bulk p-channel.p-channel.

- VCVS VCCS I1 I1 Rm I 1 Ai I 1 CCVS CCCS .CMOS Analog Circuit Design Page I.Allen and Holberg .4-2 SYMBOLS FOR CIRCUIT ELEMENTS Operational Amplifier/Amplifier/OTA + - V I + + AvV1 G mV1 V1 V1 .

4-3 Notation for signals Id id ID iD time .CMOS Analog Circuit Design Page I.Allen and Holberg .

8 Geometrical Considerations .7 ESD Protection II.0-1 II.1 Basic Fabrication Processes II.2 CMOS Technology II.3 PN Junction II.6 Latchup Protection II.4 MOS Transistor II.CMOS Analog Circuit Design Page II.Allen and Holberg .5 Passive Components II. CMOS TECHNOLOGY Contents II.

0-2 Perspective Chapter 10 Chapter 11 D/A and A/D Analog Systems Converters SYSTEMS Chapter 7 Chapter 8 Chapter 9 CMOS Simple CMOS High Performance Comparators Opamps Opamps COMPLEX CIRCUITS Chapter 5 Chapter 6 CMOS CMOS Subcircuits Amplifiers SIMPLE Chapter 2 Chapter 3 Chapter 4 CMOS CMOS Device Device Technology Modeling Characterization DEVICES .Allen and Holberg .CMOS Analog Circuit Design Page II.

• Characterize passive components compatible with basic technologies. • Understand the limits and constraints introduced by technology. • Provide a background for modeling at the circuit level. .0-3 OBJECTIVE • Provide an understanding of CMOS technology sufficient to enhance circuit design.Allen and Holberg .CMOS Analog Circuit Design Page II.

8 mm 125-200 mm n-type: 3-5 -cm p-type: 14-16 -cm .BASIC FABRICATION PROCESSES BASIC FABRTICATION PROCESSES Basic Steps Oxide growth Thermal diffusion Ion implantation Deposition Etching Photolithography Means by which the above steps are applied to selected areas of the silicon wafer.1-1 II. Silicon wafer 0.CMOS Analog Circuit Design Page II.Allen and Holberg .5-0.1 .

1-2 Oxidation The process of growing a layer of silicon dioxide (SiO 2)on the surface of a silicon wafer. Original Si surface tox SiO 2 0. Thicker oxides (>1000 Å) are grown using wet oxidation techniques.44 tox Si substrate Uses: Provide isolation between two layers Protect underlying material from contamination Very thin oxides (100 to 1000 Å) are grown using dry-oxidation techniques. .CMOS Analog Circuit Design Page II.Allen and Holberg .

1-3 Diffusion Movement of impurity atoms at the surface of the silicon into the bulk of the silicon .CMOS Analog Circuit Design Page II. High Low Concentration Concentration Diffusion typically done at high temperatures: 800 to 1400 C.from higher concentration to lower concentration. Infinite-source diffusion: N 0 ERFC t1<t2<t3 N(x) N B t1 t2 t3 Depth (x) Finite-source diffusion: N0 Gaussian t1<t2<t3 N(x) NB t1 t2 t3 Depth (x) .Allen and Holberg .

1-4 Ion Implantation Ion implantation is the process by which impurity ions are accelerated to a high velocity and physically lodged into the target. Unique doping provile available with buried concentration peak. Concentration peak N(x) NB 0 Depth (x) . thus it is useful for field-threshold adjustment.Allen and Holberg . Can implant through surface layers. This step is done at 500 to 800 C. Path of impurity atom Fixed atoms Impurity final resting place Anneal required to activate the impurity atoms and repair physical damage to the crystal lattice.CMOS Analog Circuit Design Page II. Lower temperature process compared to diffusion.

Allen and Holberg .CMOS Analog Circuit Design Page II.1-5 Deposition Deposition is the means by which various materials are deposited on the silicon wafer. Examples: Silicon nitride (Si3N4) Silicon dioxide (SiO2) Aluminum Polysilicon There are various ways to deposit a meterial on a substrate: Chemical-vapor deposition (CVD) Low-pressure chemical-vapor deposition (LPCVD) Plasma-assisted chemical-vapor deposition (PECVD) Sputter deposition Materials deposited using these techniques cover the entire wafer. .

a Mask Film c b Underlying layer .1-6 Etching Etching is the process of selectively removing a layer of material.Allen and Holberg .CMOS Analog Circuit Design Page II. There are basically two types of etches: Wet etch. uses chemically active ionized gasses. uses chemicals Dry etch. and film to substrate) film etch rate Sfilm-mask = mask etch rate Desire perfect anisotropy (A=1) and invinite selectivity. the etchant may remove portions or all of: the desired material the underlying layer the masking layer Important considerations: Anisotropy of the etch lateral etch rate A = 1 . When etching is performed.vertical etch rate Selectivity of the etch (film toomask.

Hard bake 6.Allen and Holberg . Develop (remove unwanted photoresist) 5.1-7 Photolithography Components Photoresist material Photomask Material to be patterned (e.CMOS Analog Circuit Design Page II. SiO2) Positive photoresist- Areas exposed to UV light are soluble in the developer Negative photoresist- Areas not exposed to UV light are soluble in the developer Steps: 1. Expose the photoresist to UV light through photomask 4.g. Soft bake 3. Remove photoresist . Apply photoresist 2.. Etch the exposed layer 7.

CMOS Analog Circuit Design Page II.Allen and Holberg .1-8 Photomask UV Light Photomask Photoresist Polysilicon .

CMOS Analog Circuit Design Page II.Allen and Holberg .1-9 Polysilicon Photoresist Photoresist Polysilicon Polysilicon Positive Photoresist .

2-1 II. both of them of high quality due to a planarization step. • Good latchup protection .Allen and Holberg . • Optimal threshold voltages of both p-channel and n-channel transistors • Lightly doped drain (LDD) transistors prevent hot-electron effects.CMOS TECHNOLOGY TWIN-WELL CMOS TECHNOLOGY Features • Two layers of metal connections.CMOS Analog Circuit Design Page II.2 .

substrate (c) p.substrate (b) n.field implant Pad oxide (SiO2) Photoresist Si3N4 Photoresist n-well p.substrate (d) Figure 2.CMOS Analog Circuit Design Page II.substrate (a) Si3N4 SiO2 n-well p.1-5 The major CMOS process steps. .2-2 n-well implant Photoresist SiO2 Photoresist p.Allen and Holberg .field implant Si3N4 Photoresist n-well p.

substrate (h) Figure 2.Allen and Holberg .2-3 Si3N4 FOX FOX n-well p.CMOS Analog Circuit Design Page II.substrate (f) SiO2 spacer Polysilicon Photoresist FOX FOX n-well p. .substrate (e) Polysilicon FOX FOX n-well p.1-5 The major CMOS process steps (cont'd).substrate (g) n+ S/D implant Polysilicon Photoresist FOX FOX n-well p.

S/D LDD implant Polysilicon Photoresist FOX FOX n-well p.substrate (l) Figure 2. .Allen and Holberg .CMOS Analog Circuit Design Page II.2-4 n.substrate (j) n+ Diffusion p+ Diffusion Polysilicon FOX FOX n-well p.substrate (i) LDD Diffusion Polysilicon FOX FOX n-well p.1-5 The major CMOS process steps (cont'd).substrate (k) n+ Diffusion p+ Diffusion Polysilicon BPSG FOX FOX n-well p.

CMOS Analog Circuit Design Page II.2-5 CVD oxide. Spin-on glass (SOG) Metal 1 BPSG FOX FOX n-well p.substrate (n) Metal 2 Metal 1 Passivation protection layer BPSG FOX FOX n-well p.1-5 The major CMOS process steps (cont'd).Allen and Holberg .substrate (m) Metal 2 Metal 1 BPSG FOX FOX n-well p.substrate (o) Figure 2. .

Allen and Holberg .CMOS Analog Circuit Design Page II.2-6 Silicide/Salicide Purpose • Reduce interconnect resistance. .1-6 (a) Polycice structure and (b) Salicide structure. Polysilicide Polysilicide Metal Silicide FOX FOX (a) (b) Figure 2.

Doped atoms near the metallurgical junction lose their free carriers by diffusion. semicon- ductor ductor iD +vD - xd xp xn x 0 1. Equilibrium conditions are reached when: Current due to diffusion = Current due to electric field .Allen and Holberg . As these fixed atoms lose their free carriers.3-1 II.3 . 3. they build up an electric field which opposes the diffusion mechanism.CMOS Analog Circuit Design Page II. 2.PN JUNCTION CONCEPT Metallurgical Junction p-type semiconductor n-type semiconductor iD +vD - Depletion region p-type n-type semicon.

semi- con.CMOS Analog Circuit Design Page II. con- ductor ductor iD +vD - Impurity concentration ( cm-3 ) ND x 0 -N A Depletion charge concentration ( cm-3 ) qN D xp x 0 xn -qNA Electric Field (V/cm) x Eo Potential (V) o vD x xd .Allen and Holberg .3-2 PN JUNCTION CHARACTERIZATION xd xp xn p-type n-type semi.

Allen and Holberg .3-3 SUMMARY OF PN JUNCTION ANALYSIS Barrier potential- kT NAND NAND o = q ln = V t ln ni2 ni2 Depletion region widths- 2 si( o-v D)N A xn = qND(NA+ND) 1 x 2 si ( o-v D)N D N xp = qND(NA+ND) Depletion capacitance- siqNAND 1 Cj0 Cj = A 2(NA+ND) = o-vD o -vD Breakdown voltage- si(NA+ND) 2 BV = 2qN N Emax A D .CMOS Analog Circuit Design Page II.

CONTINUED Current-Voltage Relationship- vD Dppno D n n p o iD = Is exp .1 where Is = qA + Vt Lp Ln 25 20 iD 15 Is 10 5 0 -5 -4 -3 -2 -1 0 1 2 3 4 vD/Vt 10 x1016 8 x1016 16 iD 6 x10 Is 4 x1016 2 x1016 0 -40 -30 -20 -10 0 10 20 30 40 vD/Vt .3-4 SUMMARY .CMOS Analog Circuit Design Page II.Allen and Holberg .

4 .2x10-7 meters = 0.Allen and Holberg .MOS TRANSISTOR ILLUSTRATION Bulk Source Gate Drain .4-1 II.02 m TYPES OF TRANSISTORS iD Depletion Enhancement Mode Mode vGS VT (depletion) VT (enhancement) .W th id lW ne Polysilicon an Ch Fig. L p-substrate (bulk) tOX = 200 Angstroms = 0.3-4 p+ n+ n+ n-channel Channel Length.CMOS Analog Circuit Design II. 4.

all transistors are enhancement mode.Allen and Holberg .CMOS Analog Circuit Design II. .3-1 Physical structure of an n-channel and p-channel transistor in an n-well technology. Normally. P-well process • Inverse of the above.substrate Figure 2.4-2 CMOS TRANSISTOR N-well process p-channel transistor n-channel transistor Polysilicon L SiO2 L ) ) (p + (n + +) n+) W W p in ( in ( rce rce s ou s ou d ra d ra n+ p+ FOX n-well p.

4-3 TRANSISTOR OPERATING POLARTIES Polarity of Polarity of Type of Device Polarity of vDS vGS and V T vBULK + + n-channel. enhance- ment. enhance. VBS 0 ment. bulk at most negative supply Drain Drain Gate Bulk Gate Source Source/bulk p-channel. VBS 0 ment. bulk at most positive supply . enhancement Most positive + - p-channel. enhance. - p-channel. + n-channel. enhancement Most negative .n-channel. enhance- ment. depletion Most negative .CMOS Analog Circuit Design II.p-channel.Allen and Holberg . depletion Most positive SYMBOLS FOR TRANSISTORS Drain Drain Gate Bulk Gate Source Source/bulk n-channel.

4-1 MOS capacitors.substrate (b) Figure 2.Allen and Holberg .5 . (a) Polysilicon-oxide-channel. . (b) Polysilicon-oxide-polysilicon.substrate (a) Polysilicon top plate Polysilicon bottom plate FOX Inter-poly SiO2 p.PASSIVE COMPONENTS CAPACITORS oxA C = tox Polysilicon-Oxide-Channel Capacitor and Polysilicon-Oxide-Polysilicon Capacitor Metal SiO2 Polysilicon top plate Gate SiO2 FOX FOX p+ bottom-plate implant p.CMOS Analog Circuit Design II.5-1 II.

M1. second.5-2 Metal-Metal and Metal-Metal-Poly Capacitors M3 M2 T M1 B Poly M3 T M2 T B M1 M2 B M1 B T Poly M2 T M1 B Figure 2. M2.CMOS Analog Circuit Design II. .4-2 Various ways to implement capacitors using available interconnect layers. and third metal layers respectively. Cdesired Top plate parasitic Bottom plate parasitic Figure 2.Allen and Holberg .4-3 A model for the integrated capacitors showing top and bottom plate parasitics. and M3 represent the first.

6-2 Components placed in the presence of a gradient. .5-3 PROPER LAYOUT OF CAPACITORS Use “unit” capacitors Use “common centroid” Want A=2*B Case (a) fails Case (b) succeeds! (a) A1 A2 B (b) A1 B A2 y x1 x2 x3 Figure 2. (a) without common- centroid layout and (b) with common-centroid layout.Allen and Holberg .CMOS Analog Circuit Design II.

Allen and Holberg .5-4 NON-UNIFORM UNDERCUTTING EFFECTS Random edge distortion Large-scale distortion Corner-rounding distortion .CMOS Analog Circuit Design II.

5-5 VICINITY EFFECT C A B C A B Figure 2.Allen and Holberg . (b) Improved matching achieved by matching surroundings of A and B .CMOS Analog Circuit Design II.6-1 (a)Illustration of how matching of A and B is disturbed by the presence of C.

Allen and Holberg .CMOS Analog Circuit Design II.5-6 IMPROVED LAYOUT METHODS FOR CAPACITORS Corner clipping: Clip corners Street-effect compensation: .

.5-7 ERRORS IN CAPACITOR RATIOS Let C1 be defined as C1 C1A C1P and C2 be defined as C2 C2A C2P CXA is the bottom-plate capacitance CXP is the fringe (peripheral) capacitance CXA >> CXP The ratio of C2 to C1 can be expressed as C2P 1+C C2 C2A + C2P C2A 2A C1 = C1A + C1P C1A C1P 1+C 1A C2A C2P C1P (C1P)(C2P) 1 + C1A C2A .Allen and Holberg .CMOS Analog Circuit Design II.C1AC2A C2A C2P C1P 1 + C1A C2A .C1A Thus best matching is achieved when the area to periphery ratio remains constant.C1A .

5 fF/ m2 0.8 m Technology) Capacitor Range of Values Relative Temperature Voltage Absolute Type Accuracy Coefficient Coefficient Accuracy Poly/poly 0.05% 50 ppm/ C 50 ppm/V 10% capacitor MOM 0.02-0.8-1.0 fF/ m2 0. Typical capacitor performance (0.CMOS Analog Circuit Design II.2-2.05% 50 ppm/ C 50 ppm/V 10% capacitor MOS 2.03 fF/ m2 1.5-8 CAPACITOR PARASITICS Top Plate Top plate parasitic Desired Capacitor Bottom plate Bottom Plate parasitic Parasitic is dependent upon how the capacitor is constructed.Allen and Holberg .5% 10% capacitor .

well p. (a) Diffused (b) Polysilicon (c) N-well .4-4 Resistors.well p.substrate (b) Metal n+ FOX FOX FOX n.5-9 RESISTORS IN CMOS TECHNOLOGY Metal SiO2 p+ FOX FOX n.substrate (c) Figure 2.substrate (a) Metal Polysilicon resistor FOX p.Allen and Holberg .CMOS Analog Circuit Design II.

0.05% 50 ppm/ C 50ppm/V 10% capacitor MOS 2.0 fF/ m 2 0.05% 50 ppm/ C 50ppm/V 10% capacitor MOM 0.Allen and Holberg .5-10 PASSIVE COMPONENT SUMMARY (0.4% 1500 ppm/ C 100ppm/V 30% N-well 1-2k /sq.8 m Technology) Component Range of Values Matching Temperature Voltage Absolute Type Accuracy Coefficient Coefficient Accuracy Poly/poly 0.03 fF/ m2 1.5 fF/ m2 0. 0.5% 10% capacitor Diffused 20-150 /sq.8-1.2-2. Poly resistor 20-40 /sq.CMOS Analog Circuit Design II. 0.4% 1500 ppm/ C 200ppm/V 35% resistor Polysilicide R 2-15 /sq.02-0.4% 8000 ppm/ C 10k ppm/V 40% resistor .

5-1 Substrate BJT available from a bulk CMOS process.well WB Collector (p.5-2 Minority carrier concentrations for a bipolar junction transistor.CMOS Analog Circuit Design II. .Allen and Holberg . Depletion regions p n p Emitter Base Collector Carrier concentration ppE nn(x) ppC pn(0) NA npE(0) ND NA pn(x) npE pn(wB) ppC x x=0 x=wB Figure 2.substrate) Figure 2.5-11 BIPOLARS IN CMOS TECHNOLOGY Metal Emitter (p+) Base (n+) FOX FOX FOX n.

6 . n-well p-substrate RP- (a) VDD RN.LATCHUP VDD S G D=B S G D=A Well tie Substrate tie p+ FOX n+ n+ FOX p+ p+ FOX n+ Q2 Q1 RN. (b) Equivalent circuit of the SCR formed from the parasitic bipolar transistors.Allen and Holberg . . Q2 A Q1 B RP- (b) Figure 2.6-1 II.5-3 (a) Parasitic lateral NPN and vertical PNP bipolar transistor in CMOS integrated circuits.CMOS Analog Circuit Design II.

5-4 Preventing latch-up using guard bars in an n-well technology .substrate Figure 2.CMOS Analog Circuit Design II.Allen and Holberg .6-2 PREVENTING LATCHUP p-channel transistor n-channel transistor n+ guard bars p+ guard bars VDD VSS FOX n-well p.

(a) Electrical equivalent circuit (b) Implementation in CMOS technology .Allen and Holberg .7 .5-5 Electrostatic discharge protection circuitry.ESD PROTECTION VDD p+ – n-well diode Bonding To internal gates Pad p+ resistor n+ – substrate diode VSS (a) Metal n+ FOX p+ FOX n-well p-substrate (b) Figure 2.CMOS Analog Circuit Design II.6-1 II.

..........................8 ............................ spacing of gate to edge of AA (transistor length dir.............. Polysilicon Capacitor top plate 4A.... extension of gate beyond AA (transistor width dir................ N-Well...... AA-p external to n-Well.........................................3 3.....................) ............. Active Area (AA) 2A........ Contacts . spacing ............................. 10 2D.................. Double-Polysilicon...Allen and Holberg ..................2 5..............3 2E......... 4 Spacing to Well 2B................2 3E... spacing of polysilicon to AA (over field)...... width...) .... AA-p contained in n-Well... AA-n external to n-Well................GEOMETRICAL CONSIDERATIONS Design Rules for a Double-Metal............................................... width .... AA-n contained in n-Well...... width........ spacing ....CMOS Analog Circuit Design II....................................... spacing to inside of polysilicon gate (bottom plate).......................... 12 2............4 Spacing to other AA (inside or outside well) 2F........ spacing ........................1 3D............ width ............................................................... 6 1B............... N-Well 1A........... Polysilicon Gate (Capacitor bottom plate) 3A............................................8-1 II. 3 3C............... AA to AA (p or n)........................4 4................ 2 3B................... 2 4C. Minimum Dimension Resolution ( ) 1... Bulk CMOS Process............................1 2C................... 2 4B....................................................

................................................. 2x2 5B.............................. spacing polysilicon contact to AA ............... spacing to AA........... width.........................................................2 6....................................2 5G. size .................................. spacing to metal circuitry ..... spacing ..................................................... spacing to polysilicon gate ............................................ enclosure by Metal-1........... 4 5C....................2 5D...... polysilicon overlap of contact................................... metal overlap of contact ............ 3 6B........................................................... spacing ..... spacing .............. Via 7A................. 3x3 7B... capacitor top plate overlap of contact................. 4 7C..1 8...............................................................................................2 5E........................... spacing .......................................1 7D..........8-2 5A................... width......................... spacing to polysilicon gate ................. Metal-1 6A....................1 5F........ size ...... 24 8D...... 24 ............................... AA overlap of contact ................................................................................CMOS Analog Circuit Design II.........Allen and Holberg .. 3 7......2 5H...................... enclosure by Metal-2................................. 24 8E.................................. Metal-2 8A........... 3 Bonding Pad 8C.......................... 4 8B..............................

....8 9C.8-3 9.......... bonding-pad opening .... Passivation Opening (Pad) 9A...... 40 Note: For a P-Well process........Allen and Holberg .... bonding-pad opening enclosed by Metal-2 .... ........100 m x 100 m 9B....... bonding-pad opening to pad opening space .......... exchange p and n in all instances.....CMOS Analog Circuit Design II.........

CMOS Analog Circuit Design II.8-4 1B 1A 2E 2B 2A 2F 2C 2D 3C 3A 3E 3D 3B Figure 2.6-8(a) Illustration of the design rules 1-3 of Table 2.6-1.Allen and Holberg . .

6-1.6-8(b) Illustration of the design rules 4-5 of Table 2. .Allen and Holberg .8-5 4C 4B 4A 5C 5A 5B 5D 5E 5F 5G 5H Figure 2.CMOS Analog Circuit Design II.

8-6 7A 7B 6B 7C 6A 7D 8A 8B 9B 9A 9C N-WELL N-AA P-AA POLYSILICON POLYSILICON METAL-1 CAPACITOR GATE METAL-2 PASSIVATION CONTACT VIA Figure 2.6-8(c) Illustration of the design rules 6-9 of Table 2.Allen and Holberg .6-1. .CMOS Analog Circuit Design II.

6-3 Example layout of an MOS transistor showing top view and side view at the cut line indicated. .CMOS Analog Circuit Design II.8-7 Transistor Layout Metal FOX FOX Active area Polysilicon drain/source gate Contact L Cut W Active area drain/source Metal 1 Figure 2.Allen and Holberg .

6-4 Example layout of MOS transistors using (a) mirror symmetry.8-8 SYMMETRIC VERSUS PHOTOLITHOGRAPHIC INVARIANT (a) (b) Figure 2.Allen and Holberg . and (b) photolithographic invariance.CMOS Analog Circuit Design II. PLI IS BETTER .

CMOS Analog Circuit Design II. .8-9 Resistor Layout Metal FOX FOX Substrate Active area (diffusion) Contact Active area or Polysilicon W Cut L Metal 1 (a) Diffusion or polysilicon resistor Metal FOX FOX FOX Substrate Active area (diffusion) Well diffusion Active area W Well diffusion Contact Cut Metal 1 L (b) Well resistor Figure 2.Allen and Holberg .6-5 Example layout of (a) diffusion or polysilicon resistor and (b) Well resistor along with their respective side views at the cut line indicated.

8-10 Capacitor Layout Polysilicon 2 Metal FOX Substrate Polysilicon gate Polysilicon gate Polysilicon 2 Cut Metal 1 (a) Metal 3 Metal 2 Metal 1 FOX Substrate Metal 2 Metal 1 Metal 3 Metal 3 Via 2 Via 2 Metal 2 Cut Via 1 Metal 1 .CMOS Analog Circuit Design II.Allen and Holberg .