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Electronics Circuit

Analysis and Design

Metal Oxide Semiconductor Field-Effect
MOSFET (metal-oxide semiconductor field-effect
transistor, pronounced MAWS-feht ) is a special type
of field-effect transistor that works by electronically
varying the width of a channel along which charge
carriers flow.
The wider the channel, the better the device
conducts. The charge carriers enter the channel at
the source , and exit via the drain . The width of the
channel is controlled by the voltage on an electrode
called the gate , which is located physically between
the source and the drain and is insulated from the
channel by an extremely thin layer of metal oxide.
Mode of Operation
Depletion Mode - When there is no voltage on
the gate, the channel exhibits its maximum
conductance. As the voltage on the gate
increases (either positively or negatively,
depending on whether the channel is made of
P-type or N-type semiconductor material), the
channel conductivity decreases.
Enhancement Mode - When there is no
voltage on the gate, there is in effect no
channel, and the device does not conduct. A
channel is produced by the application of a
voltage to the gate. The greater the gate
voltage, the better the device conducts.
Types and Symbol
Depletion Type – a MOSFET that can Enhancement Type – a MOSFET that can
operate in depletion or enhancement operate in enhancement mode only.
Depletion Type MOSFET (n-Channel)
A slab of p -type material is formed from a silicon
base and is referred to as the substrate. It is the
foundation on which the device is constructed. In
some cases the substrate is internally connected to
the source terminal.
The gate is also connected to a metal contact surface
but remains insulated from the n -channel by a very
thin silicon dioxide layer. SiO2 is a type of insulator
referred to as a dielectric , which sets up electric
fields within the dielectric when exposed to an
externally applied field. The fact that the SiO2 layer is
an insulating layer means that there is no direct
electrical connection between the gate terminal
and the channel of a MOSFET.
Basic Operation And Characteristics
If the gate-to-source voltage is set to 0 V by the
direct connection from one terminal to the
other, and a voltage VDD is applied across the
drain-to-source terminals, the result is an
attraction of the free electrons of the n-channel
for the positive voltage at the drain. The result
is a current similar to that flowing in the
channel of the JFET. In fact, the resulting
current with VGS = 0 V continues to be labeled
The transfer curve is defined by Shockley’s
However, if VGS is set at a negative voltage such as -1 V. The
negative potential at the gate will tend to pressure
electrons toward the p -type substrate (like charges repel)
and attract holes from the p -type substrate (opposite
charges attract).
Depending on the magnitude of the negative bias
established by VGS , a level of recombination between
electrons and holes will occur that will reduce the number
of free electrons in the n -channel available for conduction.
The more negative the bias, the higher is the rate of
recombination. The resulting level of drain current is
therefore reduced with increasing negative bias for VGS.
For positive values of VGS , the
positive gate will draw additional
electrons (free carriers) from the p
-type substrate due to the reverse
leakage current and establish new
carriers through the collisions
resulting between accelerating
particles. As the gate-to-source
voltage continues to increase in
the positive direction, the drain
current will increase at a rapid rate
for the reasons listed above.
Sketch the transfer characteristics for an n -channel depletion-type MOSFET with IDSS = 10 mA
and VP = -4 V.
Depletion-Type MOSFET (p-Channel)
The construction of a p -
channel depletion-type
MOSFET is exactly the reverse
of that of n-channel MOSFET.
The terminals remain as
identified, but all the voltage
polarities and the current
directions are reversed. The
drain characteristics would
appear exactly as in n-channel,
but with VDS having negative
values, ID having positive
values, and VGS having the
opposite polarities.
Depletion-Type MOSFET Biasing
The similarities in appearance between the transfer curves of JFETs and depletion-type MOSFETs
permit a similar analysis of each in the dc domain. The primary difference between the two is
the fact that depletion-type MOSFETs permit operating points with positive values of VGS and
levels of ID that exceed IDSS . In fact, for all the configurations discussed thus far, the analysis is
the same if the JFET is replaced by a depletion-type MOSFET.
For the n -channel depletion-type MOSFET,

a. IDQ and VGSQ using graphical and

mathematical method
b. VDS
a. Graphical a. Mathematical
Repeat the previous example using graphical method with RS = 150 ohms
For the n -channel depletion-type MOSFET,

a. IDQ and VGSQ using graphical and

mathematical method
b. VD
a. Graphical b. Mathematical
Enhancement-Type MOSFET
Although there are some similarities in construction and mode of operation
between depletion-type and enhancement-type MOSFETs, the characteristics of
the enhancement-type MOSFET are quite different from anything obtained thus
far. The transfer curve is not defined by Shockley’s equation, and the drain
current is now cut off until the gate-to-source voltage reaches a specific
Basic Construction (n-channel)
A slab of p -type material is formed from a silicon base and
is again referred to as the substrate. The substrate is
sometimes internally connected to the source terminal,
whereas in other cases a fourth lead (labeled SS) is made
available for external control of its potential level. The
source and drain terminals are again connected through
metallic contacts to n -doped regions, but note the absence
of a channel between the two n -doped regions. This is the
primary difference between the construction of depletion-
type and enhancement-type MOSFETs—the absence of a
channel as a constructed component of the device. The SiO2
layer is still present to isolate the gate metallic platform
from the region between the drain and source, but now it is
simply separated from a section of the p -type material.
Basic Operation and Characteristic
For an n -channel enhancement-type MOSFET, both VDS
and VGS must have a positive voltage in order for it to
operate. A positive bias on VDS will not immediately result
to a flow of carriers due to the absence of the channel,
which can only by attained by a bias voltage at the gate-to-
source terminal. The positive potential at the gate will
pressure the holes in the p -substrate along the edge of the
SiO2 layer to leave the area and enter deeper regions of the
p -substrate. The SiO2 layer and its insulating qualities will
prevent the negative carriers from being absorbed at the
gate terminal. As VGS increases in magnitude, the
concentration of electrons near the SiO2 surface increases
until eventually the induced n -type region can support a
measurable flow between drain and source.
The level of VGS that results in the significant increase in
drain current is called the threshold voltage and is given
the symbol VT . As VGS is increased beyond the threshold
level, the density of free carriers in the induced channel
will increase, resulting in an increased level of drain
current. However, if we hold VGS constant and increase
the level of VDS, the drain current will eventually reach a
saturation level. The leveling off of ID is due to a
pinching-off process depicted by the narrower channel
at the drain end of the induced channel.
The saturation level for VDS is related to the level of
applied VGS by

For values of VGS less than the threshold level, the

drain current of an enhancement-type MOSFET is 0
For levels of VGS > VT, the drain current is related to
the applied gate-to-source voltage by the following
nonlinear relationship:

To draw the transfer
curve, draw a horizontal
line from the origin to VT,
since at VGS < VT, ID = 0 A.
Next, a level of VGS
greater than VT can b
substituted to the
transfer equation to
acquire a corresponding
value for ID .
p-Channel Enhancement-Type
The construction of a p -channel enhancement-type MOSFET is exactly the
reverse of n-channel enhancement-type MOSFET. That is, there is now an n -
type substrate and p -doped regions under the drain and source connections.
The terminals remain as identified, but all the voltage polarities and the current
directions are reversed. The transfer characteristics will be the mirror image
(about the ID axis) of the transfer curve
n-channel enhancement-type MOSFET,
with ID increasing with increasingly
negative values of VGS beyond VT .
Enhancement-Type MOSFET Biasing
First and foremost, recall that for the n -channel
enhancement-type MOSFET, the drain current is zero
for levels of gate-to-source voltage less than the
threshold level VGS(Th). For levels of VGS greater than
VGS(Th), the drain current is defined by

Since specification sheets typically provide the

threshold voltage and a level of drain current (ID(on)) and
its corresponding level of VGS(on), two points are defined
Feedback Bias
A popular biasing arrangement for enhancement-type MOSFETs.
The resistor RG brings a suitably large voltage to the gate to drive
the MOSFET “on.”
The current through RS is the source current IS, which is equal to ID.
The equation for VGS can be obtained by applying Kirchhoff’s voltage
For the mathematical approach, the expression of ID will be a
quadratic equation.
For the graphical approach, we need to establish the load line first to
determine the quiescent point.
Determine IDQ and VDSQ for the enhancement-type MOSFET
Graphical Mathematical
Voltage-Divider Bias
A second popular biasing arrangement for the enhancement-type
MOSFET. The fact that IG = 0 mA results in the following equation
for VGG as derived from an application of the voltage-divider rule.
Determine IDQ, VGSQ, and VDS for the network.
Graphical Mathematical