Sequential Verilog slides in digital systems

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Sequential Verilog slides in digital systems

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Edge-sensitive always block

Verilog for flip-flops

No-blocking assignments

Verilog for asyn and syn reset

Verilog for registers

Shift register

Counter

Bus structure

Verilog for Latch

Clk D Q( t + 1) module D_latch (D, Clk, Q);

0 x Q( t ) input D, Clk;

1 0 0

1 1 1 output Q;

reg Q;

if (Clk)

Clk Q

Q = D;

endmodule

No else clause

Sensitivity list should include D and Clk

always block (overview)

Level-sensitive always block

always @ (signal1 or signal2)

Used for combinational circuits and Latches

Edge-sensitive always block

always @ (posedge clk)

– Response to positive edge of clk signal

always @ (negedge clk)

– Response to negative edge of clk signal

Used for sequential circuits and flip-flops

D flip-flop

D Q module flipflop (D, Clock, Q);

input D, Clock;

Clock Q

output Q;

reg Q;

Sensitivity list contains only Clock Q = D;

Why?

endmodule

Assignments (overview)

Continuous assignments – fixed connection

assign f1 = a && b;

assign f2 = ~ f1;

Blocking assignments – evaluate in order

= in always block

begin

Q1 = D; // new Q1 will be used in evaluating all subsequent statements in this block

Q2 = Q1; // new Q1 goes to Q2, so Q2 is equal to D.

end

No-blocking assignments – evaluate in parallel

<= in always block

begin

Q1<= D;

Q2<= Q1; // old Q1 goes to Q2

End

The order of statements doesn’t matter

Note: Logical and Bitwise Operators

A logical operator interprets its operands as either true or false and always

evaluate to a 1-bit true or false result. A bitwise operator interprets its operands

as vectors and returns a vector.

Verilog supports the following logical operators:

! - Negation (takes 1 operand)

&& - And (takes 2 operands)

|| - Or (takes 2 operands)

If the operand supplied to a logical operand is equal to zero, it is interpreted as

false. Any non-zero operand is interpreted as true. The logical operation is

performed on the operand(s) and a 1-bit value is returned.

Verilog supports the following bitwise operators:

~ - Negation (takes 1 operand)

& - And (takes 2 operands)

| - Or (takes 2 operands)

^ - Xor (takes 2 operands)

^~ - Xnor (takes 2 operands)

~^ - Xnor (takes 2 operands)

Blocking and non-blocking assignments

Initially, Q1=10, Q2=0 Initially, Q1=10, Q2=0

begin begin

Q1 = Q2 ; Q1 <= Q2;

Q2 = Q1 ; Q2 <= Q1;

end end

After one clk positive edge After one clk positive edge

What happens

if we change the

Q1=0, Q2=0 Q1=0, Q2=10 order of two statements?

Q1=Q2 Q1,Q2 exchange

Blocking assign

module example7_3 (D, Clock, Q1, Q2);

input D, Clock;

output Q1, Q2;

reg Q1, Q2;

D D Q Q1

begin

Q1 = D; D Q Q2

Q2 = Q1; Q

end

endmodule

Two cascaded flip-flops

No-blocking assignments

input D, Clock;

output Q1, Q2;

reg Q1, Q2;

Q1 Q2

begin Clock Q Q

Q1 <= D;

Q2 <= Q1;

end

endmodule

Blocking Example

module example_blocking (x1, x2, x3, Clock, f, g);

input x1, x2, x3, Clock;

output f, g;

reg f, g;

x3

begin

g

f = x1 & x2; x1

x2

D Q

g = f | x3; Q

end

D Q f

endmodule

Clock Q

No Blocking Example

module example_noblocking (x1, x2, x3, Clock, f, g);

input x1, x2, x3, Clock;

output f, g;

reg f, g;

x3

always @(posedge Clock) D Q g

begin Q

g <= f | x3; x1

D Q f

x2

end

Clock Q

endmodule

Recommendations

It is better to use blocking assignments when

describing combinational circuits

It is better to using no-blocking assignments to

describe sequential circuits

T flip-flop

T Q( t + 1)

0 Q( t )

module tff(t, clk,q);

1 Q( t )

input t, clk;

(b) Truth table

output q;

reg q;

case(t)

T Q

0: q <= q;

Q 1: q <= ~q;

endcase

(c) Graphical symbol

endmodule

Flip-flop with clear capability

module flipflop (D, Clock, Resetn, Q);

input D, Clock, Resetn;

output Q;

reg Q;

if (!Resetn)

Q <= 0;

else

Q <= D;

endmodule

Flip-flop with clear capability

module flipflop (D, Clock, Resetn, Q);

input D, Clock, Resetn;

output Q;

reg Q;

if (!Resetn)

Q <= 0; Clear

D Q Q

D

else

Clock Q Q

Q <= D;

endmodule

N-bit register

module regn (D, Clock, Resetn, Q);

parameter n = 16; D[n-1] Q[n-1]

input [n-1:0] D; D Q

input Clock, Resetn;

output [n-1:0] Q;

reg [n-1:0] Q;

D Q

always @(negedge Resetn or posedge Clock)

if (!Resetn)

Q <= 0;

else

Q <= D; D[0]

D Q Q[0]

endmodule

Clock

4-bit shift register

module muxdff (D0, D1, Sel, Clock, Q); module shift4 (R, L, w, Clock, Q);

input D0, D1, Sel, Clock; input [3:0] R;

output Q; input L, w, Clock;

reg Q; output [3:0] Q;

wire [3:0] Q;

always @(posedge Clock)

if (!Sel) muxdff Stage3 (w, R[3], L, Clock, Q[3]);

Q <= D0; muxdff Stage2 (Q[3], R[2], L, Clock, Q[2]);

else muxdff Stage1 (Q[2], R[1], L, Clock, Q[1]);

Q <= D1; muxdff Stage0 (Q[1], R[0], L, Clock, Q[0]);

endmodule endmodule

Q

D

clock

sel Circuit ?

0 1

D0 D1

4-bit shift register

module shift4 (R, L, w, Clock, Q); 4

R Q[3]

input [3:0] R;

input L, w, Clock; w

output [3:0] Q; Clock Q[0]

reg [3:0] Q;

always @(posedge Clock)

L

if (L)

Q <= R;

else Comments:

begin 1) This is a behavioral description

Q[0] <= Q[1]; 2) Only Clock is included in always list

3) Control signal L is used in if statement

Q[1] <= Q[2];

Q[2] <= Q[3];

Q[3] <= w;

end

endmodule

N-bit shift register

module shift4 (R, L, w, Clock, Q); module shiftn (R, L, w, Clock, Q);

parameter n = 16;

input [3:0] R;

input [n-1:0] R;

input L, w, Clock; input L, w, Clock;

output [3:0] Q; output [n-1:0] Q;

reg [3:0] Q; reg [n-1:0] Q;

always @(posedge Clock) integer k;

if (L)

Q <= R; always @(posedge Clock)

else if (L)

begin Q <= R;

else

Q[0] <= Q[1];

begin

Q[1] <= Q[2]; for (k = 0; k < n-1; k = k+1)

Q[2] <= Q[3]; Q[k] <= Q[k+1];

Q[3] <= w; Q[n-1] <= w;

end end

endmodule endmodule

Up-counter

module upcount (Resetn, Clock, E, Q);

input Resetn, Clock, E;

output [3:0] Q;

reg [3:0] Q;

if (!Resetn)

Q <= 0;

else if (E)

Q <= Q + 1;

endmodule

Comments: asynchronous reset; counting if enable (E) is high.

Up-counter with parallel load

module upcount (R, Resetn, Clock, E, L, Q);

input [3:0] R;

input Resetn, Clock, E, L;

output [3:0] Q;

reg [3:0] Q;

if (!Resetn)

Q <= 0;

else if (L)

Q <= R;

else if (E)

Q <= Q + 1;

endmodule

Up-counter simulation

Frequency Divider by N

module clock_div(SlowClock, Reset, Clock);

input Reset, Clock;

output SlowClock;

reg SlowClock;

reg [19:0] ClockDiv;

parameter Maxcount = 4;

always @ (posedge Clock or negedge Reset)

if(!Reset)

begin

ClockDiv <= 0;

SlowClock <= 0;

end

else if (ClockDiv == Maxcount)

begin

SlowClock <= 1;

ClockDiv <=0;

end

else

begin

SlowClock <= 0;

ClockDiv <= ClockDiv+1;

end

endmodule

Simulation result

Bus structure for digital systems

Data

Extern

Bus

Clock

R1 R2 Rk

Control circuit

Function

2-bit bus connecting: 2 registers

Swapping operation

(2)

R1 R2

(1)

temporary storage

R3

Verilog for swapping

Data

regn Extern

Bus

Clock

R1 R2 Rk

trin

R1in R1out R2in R2out Rkin Rkout

shiftr

Control circuit

Function

N-bit register module

module regn (R, Rin, Clock, Q);

parameter n = 8;

input [n-1:0] R;

input Rin, Clock;

output [n-1:0] Q; R Q

reg [n-1:0] Q;

regn

Clock

always @(posedge Clock)

if (Rin)

Q <= R;

Rin

endmodule

Tri-state module

module trin (Y, E, F);

parameter n = 8;

input [n-1:0] Y;

input E;

output [n-1:0] F; Y F

wire [n-1:0] F; trin

assign F = E ? Y : 'bz;

E

endmodule

Control circuit module

module shiftr (Resetn, w, Clock, Q);

parameter m = 4;

input Resetn, w, Clock;

output [1:m] Q;

reg [1:m] Q;

integer k;

if (!Resetn) Q[1] Q[2] Q[3] Q[4]

Q <= 0;

w

else

begin

for (k = m; k > 1; k = k-1)

Q[k] <= Q[k-1];

Q[1] <= w;

end

endmodule

A digital system for swap

module swap (Data, Resetn, w, Clock, assign Rin[1] = RinExt[1] | Q[3];

Extern, RinExt, BusWires); assign Rin[2] = RinExt[2] | Q[2];

assign Rin[3] = RinExt[3] | Q[1];

input [7:0] Data; assign Rout[1] = Q[2];

input Resetn, w, Clock, Extern; assign Rout[2] = Q[1];

input [1:3] RinExt; assign Rout[3] = Q[3];

output [7:0] BusWires;

tri [7:0] BusWires; regn reg_1 (BusWires, Rin[1], Clock, R1);

wire [1:3] Rin, Rout, Q; regn reg_2 (BusWires, Rin[2], Clock, R2);

wire [7:0] R1, R2, R3; regn reg_3 (BusWires, Rin[3], Clock, R3);

shiftr control (Resetn, w, Clock, Q); trin tri_ext (Data, Extern, BusWires);

defparam control.m = 3; trin tri_1 (R1, Rout[1], BusWires);

trin tri_2 (R2, Rout[2], BusWires);

trin tri_3 (R3, Rout[3], BusWires);

endmodule

Q[1]: R2out , R3in

Q[2]: R1out , R2in

Q[3]: R3out , R1in

Swap based on multiplexers

Bus

R1 R2 Rk

Clock

Data

S0

Multiplexers

Sj – 1

Control circuit

Swap using multiplexers

regn reg_1 (BusWires, Rin[1], Clock, R1);

module swapmux (Data, Resetn, w, Clock,

regn reg_2 (BusWires, Rin[2], Clock, R2);

RinExt, BusWires);

regn reg_3 (BusWires, Rin[3], Clock, R3);

input [7:0] Data;

input Resetn, w, Clock;

always @(Q or Data or R1 or R2 or R3)

input [1:3] RinExt;

begin

output [7:0] BusWires;

if (Q == 3'b000) BusWires = Data;

reg [7:0] BusWires;

else if (Q == 3'b100) BusWires = R2;

wire [1:3] Rin, Q;

else if (Q == 3'b010) BusWires = R1;

wire [7:0] R1, R2, R3;

else BusWires = R3;

end

shiftr control (Resetn, w, Clock, Q);

defparam control.m = 3;

endmodule

assign Rin[1] = RinExt[1] | Q[3];

assign Rin[2] = RinExt[2] | Q[2];

assign Rin[3] = RinExt[3] | Q[1];

Q[1]: R2out

Q[1]: R2out , R3in

Q[2]: R1out

Q[2]: R1out , R2in Q [1:3]: Q[1], Q[2], Q[3] Q[3]: R3out

Q[3]: R3out , R1in

Simulation

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