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EE457 Digital Integrated Circuits Fall 2009

Instructor: Aleksey Pinkhasov


Email Apinkhasov@ccny.cuny.edu
Phone: (908) 668-5000 x5701
For Emergencies ONLY: (646) 234-1082
Office Hours: via email and after class
Required Text: Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic,
Digital Integrated Circuits A Design Perspective, 2nd edition

Exams: There will be Two Midterms and One Final (There may be occasional quizzes)

Grading Policy: Homework 10%


Project 30%
Midterm 1 30%
Final 30%

Chapter 1: INTRODUCTION
1.2 Issues in Digital Integrated Circuit Design
1.3 Quality Metrics of a Digital Design
1.3.1 Cost of an Integrated Circuit
1.3.2 Functionality and Robustness
1.3.3 Performance
1.3.4 Power and Energy Consumption
Chapter 3: THE DEVICES
3.1 Introduction
3.2 The Diode
3.3 The MOS(FET) Transistor
3.4 A Word on Process Variations
3.5 Perspective: Technology Scaling
Chapter 4: THE WIRE
4.1 Introduction
4.2 A First Glance
4.3 Interconnect Parameters — Capacitance, Resistance, and Inductance
4.4 Electrical Wire Models
Chapter 5: THE CMOS INVERTER
5.1 Introduction
5.2 The Static CMOS Inverter — An Intuitive Perspective
5.3 Evaluating the Robustness of the CMOS Inverter: The Static Behavior
5.4 Performance of CMOS Inverter: The Dynamic Behavior
5.5 Power, Energy, and Energy-Delay
Chapter 6: DESIGNING COMBINATIONAL LOGIC GATES IN CMOS
6.1 Introduction
6.2 Static CMOS Design
6.4 Perspectives
Chapter 7: DESIGNING SEQUENTIAL LOGIC CIRCUITS
7.1 Introduction
7.2 Static Latches and Registers
7.3 Dynamic Latches and Registers
7.4 Alternative Register Styles*
7.5 Pipelining: An approach to optimize sequential circuits
7.6 Non-Bistable Sequential Circuits
7.7 Perspective: Choosing a Clocking Strategy

CHAPTER 10: TIMING ISSUES IN DIGITAL CIRCUITS


10.1 Introduction
10.2 Timing Classification of Digital Systems
10.2.1 Synchronous Interconnect
10.2.2 Mesochronous interconnect
10.2.3 Plesiochronous Interconnect
10.2.4 Asynchronous Interconnect9
10.3 Synchronous Design — An In-depth Perspective
10.3.1 Synchronous Timing Basics
10.3.2 Sources of Skew and Jitter
10.3.3 Clock-Distribution Techniques
10.3.4 Latch-Based Clocking *
10.4 Self-Timed Circuit Design*
10.4.1 Self-Timed Logic - An Asynchronous Technique
10.4.2 Completion-Signal Generation
10.4.3 Self-Timed Signaling
10.4.4 Practical Examples of Self-Timed Logic
10.5 Synchronizers and Arbiters*
10.5.1 Synchronizers—Concept and Implementation
CHAPTER 11: DESIGNING ARITHMETIC BUILDING BLOCKS
11.1 Introduction
11.2 Datapaths in Digital Processor Architectures
11.3 The Adder
11.3.1 The Binary Adder: Definitions
11.3.2 The Full Adder: Circuit Design Considerations
11.3.3 The Binary Adder: Logic Design Considerations
11.4 The Multiplier
11.4.1 The Multiplier: Definitions
11.4.2 Partial-Product Generation
11.4.3 Partial Product Accumulation
11.4.4 Final Addition
11.4.5 Multiplier Summary
11.5 The Shifter
11.5.1 Barrel Shifter
11.5.2 Logarithmic Shifter
11.6 Other Arithmetic Operators
CHAPTER 12: DESIGNING MEMORY AND ARRAY STRUCTURES
12.1 Introduction
12.1.1 Memory Classification
12.1.2 Memory Architectures and Building Blocks
12.2 The Memory Core
12.2.1 Read-Only Memories
12.2.2 Nonvolatile Read-Write Memories
12.2.3 Read-Write Memories (RAM)
12.2.4 Contents-Addressable or Associative Memory (CAM)
12.3 Memory Peripheral Circuitry
12.3.1 The Address Decoders
12.3.2 Sense Amplifiers
12.3.3 Voltage References
12.3.4 Drivers/Buffers
12.3.5 Timing and Control
12.4 Memory Reliability and Yield
12.4.1 Signal-To-Noise Ratio
12.4.2 Memory yield
12.5 Power Dissipation in Memories
12.5.1 Sources of Power Dissipation in Memories