You are on page 1of 15

25 VESA Local Bus VLB

The VES.4 10~4 bus, or VLB for short, has been designed as much nwre of a local bus than its
later competitor, the PCI. It is dire&y connected to the local CPU bus of a i386, i4t36 or Pentium
(from specification 2.0 onwards). In this way, it uses bus cycles that are largely the same as those
of the 80x86 process0IS. Note, however, that the cycles even within the 80x86 family can vary,
for example, the i366 does not include a burst cycle. To begin with, I would like to introduce
a few of the distinguishing features of this bus system:
no decoupling of processor and expansion bus,
other bus systems can be conn&ed through their own bridge,
VLB runs with the bus frequency of the processa: maximum 66 MHz on-board or 40 MHz
(specification 1.0) and 50 MHz @ecitication 2.0) in a slot,
32-bit standard bus width with a maximum 133 Mbytes/s (specification 1.01 and 160 Mbytes/s
(specification 2.0) transfer rate,
expansion to 64 bits with a maximum 267 Mbytes/s transfer rate @citication 2.01,
burst transfers of up to four cycles maximum, .*
nudtimaster capabilitie%,
only a single host CPU,
separate address and data lines for simultaneous transfers of address and data bytes,
combined VLB/ISA slots,
processor dependent specification for the 80x86 family,
supporting of dynamic changes of the clock frequency,
simpler and therefore cheaper solution than PCI, but in end effect somewhat less powerful.
maximum of three VL busmasters in addition to the VL bus controller of each VLB sub
supporting of write-back caches.

25.1 VLB Bus Structure

You can see the concept layout of the VL bus system in Figure 25.1. As in the PC1 bus, the VL
bus is situated between the processor and memory system and the standard expansion bus.
From the illustration, you can clearly see that the VL bus is not so strictly dwoupled from the
processor system on the one side and the standard expansion bus on the other, as in PCI. The
VL bus can include up to three VL bus units, which can be inserted in the corresponding VL
slots on the motherboard. In Figure 25.1, you c?n schematically see the layout of a system using
a VL bus. The VLB subsystem is controlled by a VL bus controller, which generates all the
necessary address, data and control signals for the local bus, or acts on them accordingly.
. &ke the miorrhannel slots, the VL slots have a 116 pole mounting (however, four are used for
the coding bridge). The main difference isJhat each VLB slot lies 5 mm behind the slot of a
standard expansion bus. In this way, a VL bus adapter can not only use the signals and contaCtS
of the VL bus but, with the corresponding geometry, it can also use the standard slot, if heceS-
say. As in the PC1 bus, the standard bus width is 32 bits, but it can be halved to 16 bits. For
this, the addressed VL unit must set the LBS16 (Local Bus Size 161 signal to a low level. With the
VESA Local Bus WE! 645

’ new specification 2.0, an expansion of the VL bus to 64 bits is planned. For this, a further 37
signals are necessary, which must be transferred through the existing contacts (multiplexing). A
VLB unit can request a &bit cycle using the LBs&2 signal.
~ F VL bus runs at the external clock frequency of the CPU. Thus, f386SX/DX, i4&5SX/DX and
1486DX2 processors supply the VL bus with differing frequendes. The VL bus is laid out in such
! a way that it can be operated with a maximum of 66 MHz. However, this is only possible if no
j,hlb us slots are included and the VL units are tntegr&d directly onto the motherboard.
Damping, signal reflections and the capacity of the VL bus slot impede such a high frequency.
For this reason, using expansion slots, the VL bus runs with a maximum of 50 MHz -even this
.:. is six times that of EISA. In too highly clocked CPUs, a frequency divider reduces the clock
speed supplied. This also applies to i386 CPUs, because the VL bus mrw with a lx-clock speed
and all 386s are supplied with a 2x-clock signal.
: The integrated bus buffer of the VL bus makes it possible to perform write accesses to VL units
:‘at 33 MHz without wait cycles; like the PC1 bus, the VESA lwal bus also catis out write
posting. During read accesses, these buffers do not give any advantage, therefore read accesses
‘, axe ?lwpys accomplished with a wait state. The VL bus spedfication also makes provision for
9 bunt’mcde. like that of the i4B6, and so implements the necessary control signals BRDY and
iBLAST. In specification 1.0. only a wad burst was implemented (because the 286 can also only
a We burst mode for cache line fills). The new spxffication 2.0 also make it possible for continual
f,mite operations to be performed using a burst. This is mainly included for CpUs or I,%caches
.: that use a write-back strategy. In this way, the shortest write burst thus runs 2-1-1-1 (maximum
646 Chaoter 25

of four transfers, no wait cycles; note that the i4B6 cannot perform a write burst). The theoretical
data transfer rate with a data bus width of 32 bits at 50 MHz (the maximum for VL slots) during
a mite is thus 32 bits. 50 q 106 s-’ I 4/5 = 160 Mbytes/s. For the first transfer of a read operation
an additional wait cycle is necessary; the burst thus runs 3-l-l-l and the data transfer rate sinks
to 133 Mbytes/s. An expansion to 64 bits gives almost twice the rate, namely 267 Mbytes/s for
a write burst and 222 Mbytes/s for a read burst. The multiplexing of the most significant data
double word prevents a hue doubling of the bus bandwidth. Naturally, VL units can also
request additional wait cycles, for instance, if no access to the video RAM is currently possible
due to a memory refresh of the adapter, or the electron beam does not perform a return. For this
purpose. the VL bus includes the two signals LRDY (Iwrl bus rmdy) and BRDY (burst ready).

I_ogically, the three possible VL units are subdivided into a so-called Laxal Busmaster (LBM) and
a Local Bus Target (LB’l?. An LBM can -as in an EISA or MCA busmaster - independently take
control of the VL bus and initiate a data transfer. An LBT, on the other hand, is not capable of
doing this, and only controls the VL bus during the data transfer; it cannot produce any bus
signals itself (except LRDM. The transfer of the bus control is accomplished by the VL bus
controller, which is usually integrated on the moth&&d and performs arbitration in a similar
way to that in the EISA or microchannel. The different units on the motherboard and in the slots
are assigned different priorities. If a unit with a high priority has control of the bus, a unit with
a lower priority cannot take over control. In addition to the VL bus controller, three other VL
busmasters are provided. Naturally, more VLB subsystems can be integrated onto a single
motherboard. The quantity of slots and external busmasters increases accordingly.

25.2 Bus Cycles

If the CPU (or a VL busmaster) addresses a unit to perform a bus cycle, the addressed VLB unit
has a maximum of 20 N to react and to activate its corresponding LDEV (local device) signal.
This is an indication to the VL bus controller that the requested bus cycle can be performed. In
total, eight types of aoxss are possible which, in the-case of the 80x86 CPLJs, can be differen-
tiated by the control sjgnals M/W (memory/IO), D/c (data/command) and W/Ii (write/read):
- INTA sequence (@I)
- instruction fetching (1W)
- halt/special cycle for i486 (Wl)
- halt/shutdown for i386 (101)
- I/O read access (010)
- memory read access (110)
- I/O write access (011)
-‘. memory write access (111).
. _
The type of special cycle for an i486, and also the differentiation between a halt and a shutdow
cycle in an i386, is achieved with the byte-enable signals m in exactly the same way as in the
applicable CPU, The VL bus cycles for single transfers and liTA sequences follow exactly f
same rules and phases as for an i386 or i4B6 CPU. Details concerning this can be found In
Sections 4.2 and 9.7. Therefore, here l would only like to explain the VLB burst cycles. I should
VESA Local Bus VLB 647

I also mention that all I/O accesses to an ISA busmaster are switched through to the VL bus, but
3 sw always performed as only Bbit accesses.
5 Burst Cycles
Every burst cycle is initiated by an adds phase, during which address pins .&%-A2 hansfer
an address and the m pins all send cxut a sienal with a low Iwel. BLAST is held at a high
level until the last data tksfer has begun. The-VL bus uses a burst cycle cwmspondi,,g to the

i4% read burst. This was also the only possible burst for VLB boards according to sp&ticstion
1.0. The addressed unit returns an active BRDY for wq data tmnskr. A m&mum of 16
bytes, that is, four double words, can be transferred in a burst. Then, one 01 mmv data phases
d follow the address phase, during which the data pins Dx kansfer data and the % pins tans-
.e il fer the byte-enable sign&. An active BRDY during a read access indicates that the tqet has
d trsn_sferwd the data on lines D31-W (32 bits). Thus, in its function, BRDY corresponds to
1s BRDY known fmm the i4t36 CPU. The VLB read transfer burst is kt performed (no wait cycles)
IS .; as i) 3-l-l-l burst. _.
In specification 2.0, VESA has also specified a burst write transfer. It is canisd wt in exactly the
ts ;
same way as a burst read transfer except, naturally, in the other dkclion. In addition to the
address on A31-AZ, the initiator also sends out data on D31-W. By using the bus buffer of
z *
the VL bus, write pasting can be pwfomwd so that in mmt suitable case5 a 2-1-1-I burst wars.
, Cthemx .>the burst cycles of the VL bus are not espxially interesting; they follow the same
signal sequence as in the MB6 burst mode (you can find all important details in %&on 9.7.1).
+ If a VLB mitster wisha to stop burst cycks, it must set the BLAST signal to a low level imms-
diately after activation of m. The target will then only pwfonn single transfers.
lit %-bit Transferr
- -
11. only address signals A31-AZ and byteenable signals BFZ-BE0
-. end in the VLB slots. The i386SX
‘” ; CPU with a &bit data bus, on the other hand, has signals BLE (BusJcw- Enable)
- and m (Bus
“- High Enable) and address bus bit Al. To produce byte-enabksignsis B&BE0 in the VLB slots
- -
1): .’ horn the CPU signals BLE, BHE and Al, the VL bus contmller for an i386SX system must
” Wrm the following lo;c combinations (or equivalent): .
&=AI 0~ B L E
Zi=~loR BFF
’:~ == ZOR B L E
(Note: 7ii corresponds to the negative value of Al.)
h addition. the i386 and also the i486 can be operated with ; width of &bib+ Note, however,
4 that * i486 dws n& perform write data duplication of the most significant data word (D31-
vll D16) in the least significant data word (D15-DO) of the second I&bit psti~cle. In addition, the
he i@%CPU always reads in the mmt significant data word through data l&D31~D15 and not
he *.&the i3% through D15-DO, if a 32-bit access is split into two l&bit scc&s using &% (VL
? bus) or % (i386/i486). The VL bus mntmller must handle the diffknces in b-zhavlour of the
>ld 1 hM processors accordingly.
648 Chapter 25

M-bit Transfers

In specification 2.0, an optional expansion of the VL data bus to 64 bits is also included, without
the need to enlarge the VLB slot or to increase the quantity of contacts.

The expansion is achieved by multiplexing the additional data and control signal pins required
with already existing pins (see Figure 25.4). The 64-bit transfer should, above all, aid burst cycles
(the multiplexing and the associated lengthening of a single transfer cycle would almost reabsorb
the gain from the wider bus). 1 would like to use two illustrations to explain the multiplexing
system and the sequence of M-bit transfer’s: Figure 25.2 shows a 64-bit single write transfer,
Figure 23.3 a 64-bit burst read cycle.

For a H-bit single write transfer, the address and control signals are first sent out on the bus
and the VLB controller adivata the address strobe signal m. Then, the controller sends out
the request signal LB%4 with a low level toindicate to the target that a .+-bit transfer shoutd
be performed. The addresed target intercepts the request and reacts with an ~ signal to
indicate to the VL bus controller that it has remgnized itself as the target of the cycle. Thlhe target
. %o sends b&k an active ACK64 if it can perform a f&bit transfer. That is the case here- The
‘write data is prepared at the start of the second LCLK. For this, the VLB controller sends #“?
the least significant double word D31-DO on the data bus. In addition, A31-A2, M/a; W!*
and BESBEO are invalidated and, in their place, the -_most significant data double word oh*
D32 and also the corresponding byte-enable signals BE7-BE4 are provided. The target takes the
64 bits and retum~ an LRDY (and an RDYRTN also) in order to coinplete the single tTanSfer
VESA Local Bus “LB 649

go7~ ytble
cycle Here, the entire operation has taken two LCLK cycles and, thus, represents the quickest
smgle transfer of the VL bus. If the 64 bits were to be transferred in two separate 3%
L ht cycles, four LCLK cycles would be necessary. For this reason, the transfer rate for single
6 transfers in 64-bit mode increases by a factor of two. With slower chips, or a very high CF’U
clock frequency, the addressing phase and also the data phase can take longer (wait states); the
transfer bandwidth is the? clearly lower.

? A burst cycle in &bit mode is initiated in the same way as a single transfer cycle. In the 64-
!: bit VLB read transfer burst shown
- in- Figure 25.3, the VLB controller lint sends out the address,
- and- corresponding BE&BE0 signals. At the start of the second LCLK cycle, in addition
i to BF3-BEO, the byte-enable signals m-BE4 for the most significant double word D6.PD32
$‘a4 also prepared. They are always at a low level, because this is after all a bunt cycle. Only in
‘-the last transfer is it possible for one m or more also to have a high level. The second LCLK
zi9’de T required for the change in direction of the transfer on the combined address/data bus
and W/R, SO that data can be read after the address has been given out. Thus,
transferred at the start of the third LCLK cycle at the earliest. The VLB controller
that it wishes to perform a burst, in_ that it pulls the -BLAST signal to a high level,
&we the target reacts with the activation of LDEV and ACK64. The target shows, by return-
“g the BRDY signal in place of LRDY, that it can perform the required bunt. Directly before
the sending back of the last BRDY signal. the VL bus controller decreases the‘m signal to
650 Chapter 25

a low level to complete the burst. The complete read burst in this particular case has taken sip
LCLK cycles. Here also, under optimum conditions (a 3-l-l-l read bunt with an addressirg
and direction changing phase each of only one LCLK clock cycle) a doubling of the tramter
bandwidth is possible, as compared that of a normal 3%bit VL data bus.

Supporting of Write-back Caches

Specification 1.0 only included the supporting of write-through caches in the VLB system. It is
then always necessary to activate the snoop signal LEADS &cdl external address strobe), if a
read or I/O cycle occurs. In this way, a snoop cycle is automatically initiated for all except the
currently active busmaster. In specification 2.0, the supporting of write-back caches is now also
included. Thus, inquiry cycles must also be performed for write accesses, but not for I/O cycles
(because otherwise it is possible for an unnecessary tits-back to be sent out, even though the
address of a unit in the non-cachable l/O address area is indicated). The WBACK signal is used
for this. An active WBACK signal with a low level indicates that the inquiry cycle sent out with
a read or write access to a cachable memory address a&a has resulted in a hit of a modified line
of a write-back cycle in an external cache (this is not necessary for non-c&able sections or areas
that do not support a write-through strategy). The external cache could be the Ll-cache of B
different busmaster (for example, the CPU, if the current busmaster is not the CPU) or the LZ-
cache of a cache subsystem.

If the VL bus contmUer activatestie WBACK signal, the access of the active busmaster must
be intermpted so that the modified line can be written back to the main memory first. The VLB
controller then disconnects the current busmaster from the VL bus (backoff) and informs the
CPU of the role of the active busmaster. The CPU can now write back the modified line. Finally.
the VL bus controller takes away control of the VL bus from the CPU and returns it back to the
previously interrupted busmaster. The reactivated busmaster repeats the same bus cycle which
previously led to the inquiry hit in the CPU cache. Now, WBACK is no longer activated be
cause the applicable cache line has been written back. Naturally, in addition to an Ll CPU ache.
an L2sache with a writ-back strategy and a mrresp6hding design can lead to the activation of
WBACK and, therefole, initiate the operation described.

25.3 Bus Arbitration

The VL bus supports up to three Local.Busn&ters (LBM). The arbitration protocol is very
simple: control of the VL bus is handed over in accordance with~_ a set priority; the arbitration
signals LREQ<x> and LGNTu> are used for this purpose. One LREQ/LGNT pair is included
’ iti every VLB slot a>. An LBM with a high priority can snatch control of the bus from an LBM
with a lower priority, but not the other way around. If an LBM wishes to take control of the bus,
it activates its LREQ signal. If no LBM with a higher priority currently has control, then the
VLB controller reach with an LGNT and so hands over control of the bus. To make the bus
available again, the currently active LBM deadivates its LREQ signal and the bus connOl COP
firms this, in that it also increases the LGNT signal to a high level.
VESA Local Bus VLB 651

If an LBM wishes to take control of the bus while another bus controller has control, it must also
activate its LREQ signal first. It is then decided whether the new requesting LBM has a higher
priority than the currently active LBM. If this is not the case, the VLB controller denies the
transfer request and keeps the LGNT signal inactive. If, an the other hand, the new wquesting
LBM has a higher priority, then the VLB controller deactivates the corresponding LGNT signal
to indicate to the currently active LBM that it must hand over control of the bus. The active LBM
finishes the current operation and deactivates its LREQ signal. The way is then clear for tmns-
fening control of the VI. bus to the requesting busmaster with a higher priority and so the VLB
controller activates the corresponding LGNT signal. If the new nester has finished its activities
and has deactivated its LREQ signal. the VLB mntroUer can hand back control of the bus to the
previously interrupted LBM.

25.4 DMA

If you consider the Layout of the VLB slots &ction 25.7) and.the spffified VLB signals &ction
25.9). you can see that here also, as in the FCI, no Direct Memory Access (DMA) is provided.
The main difference to PC1 is the fact that a VLB adapter usually uses an ISA or EISA slot as
well and, therefore, also uses the (E)ISA control signals (incidentally, in the case of VLB, this
also justifies the title &cal bust). VLB adapters generally include the signals DRBQx and
DACKx. Thus, a DMA access in the style of an AT or EISA PC is still possible. However, it is
then carried out by the (E)ISA bus and not the VL bus, with all limitations regarding the data ’
transfer rate, etc. Naturally, a VLB unit located in the memory address area of the CPU or the
DMA controller can represent the target of a DMA transfer which is controlled by the DMA .
controller on the motherboard, or a busmaster on an expansion card. This, however, has nothing
to do with the VL bus; it only concerns the addressing of a unit in the memory address area
(which can be achieved equally as well through the (EJISA bus). If a VLB unit uses only the VL
bus to perform a data transfer, then it must represent a VL busmaster which can fully control
the VL bus. This strategy normally pennits a far greater data transfer rate than the classic DMA
technique, because the VL busmaster can use the wide (32 6ib or even 64 bits) and fast (up to
50 MHz in the slots) VL bus’in burst mode. The necessary bus arbitration is performed by means
of il VL bus controller as in FCI. Thus, in the VL bus also, the concept of the direct memory
access is replaced by the more flexible, and more powerful, external busmaster principle.

25.5 Interrupts ‘,
Only a single interrupt pin is included in the VLB specitication, namely IRQ9. It is level trig-
gered, active at a high level and is directly connected to IRQ9 of the (E)lSA bus.
If the Vi
- bus is integrated into a micrcwhannel system, then the VLB IRQ9 is connwted to the
M CA IRQ9 through an inverter. Normally, the VLB adapter 31~0 uses the existing ISA, EISA or
&A slot, so that sufficient interrupt linff are available. It is, of course, theoretically possible
fOr a manufacturer to deliver a pure VLB adapter without contacts for the (E)ISA bus or
~croch.wmel. For such stnnddlone VLB adapters, you do not need to concern yourself about
652 Chapter 25

whether they are used in an (E)ISA.or a microchannel system - after all, the VLB part is alwa! s
the same. The only problem is that along with the standard slot, the interrupt pins also dls-
appear. For this reason, the VLB specification includes the Intermpt IRQ9, to give stand-alone
adapters at least one possible hardware interrupt.

25.6 l/O Address Space

As a local bus for iX%/i4% and I’entium CF’Us, in accordance with its specification, the VL bus
supports a 64k I/O address area with 8, I& or 3%bit ports. In general, because the VI. bus
represents the expansion of an ISA/EISA or MCA system, the affected pats also have the
corresponding registers. You wilI find all valid I/O addresses and the corresponding layout in
Chapters 21 (ISA), 22 (EISA) and 23 (MCA). The VLB specification dog not provide n set
configuration register at a clearly predefined I/O address. Often, however, such registers are
available depending on the manufacturer, so that in the setup, for example, you can input the
quantity of VLB wait states or the VLB clock frequency. Also note that unlike PCI, no special
VLB BIOS is provided, thus, the VL bus is designee? as a local system for an IBMampatible
personal computer with an 80x86 processor.

25.7 VLB Slots

As already explained, the VL slots have a II&pole standard microchannel mounting. Each lies
behind a standard expansion bus slot so that a VL bus adapter can also use the signals and
contacts of the standard slots (and this usua”y enables them to have access to the hardware
interrupts). In the new specification 2.0, with its expansion of the VL bus to 64 bits, the 37 new
signals necessary are multiplexed with the address signals through the existing contacts. YOU
can see the geomehy and layout of the VLB slots in Figure 25.4.
The quantity of VLB slots is only restricted by their load capacity. For this reason, it is not
absolutely necessary for a VLB system actually to-include slots. The VLB units can als0 k
integrated onto the,motherbaard. However, this solution would, certainly in most cases, Nn
contrary to the target of greater flexibility. Usually, a VLB subsystem with a maximum of
40 MHz would include two or three VLB slots, a VLB subsystem operating with the full 50 MHz
would contain one or two slots.

25.8 VLB Adapters

The VL bus is mainly sold as an expansion of ISA motherboards. In this way, the flexibility Of
I ‘& ISA bus isretained. The I&bit data bus is completely sufficient for most applications (such
Bs serial and parallel interface, floppy drives, etc.). Only the few units with a very high transfer
rate (like graphic adapters, hard disks) are sewed by the faster VL bus. For this reason, you get
very gwd value for money in the form of a flexible (ISA) but nevertheless fast (VL bus) s?Stem-
The VESA lwal bus is also a very good compromise between technical and financial reStTaintS
and a higher transfer speed. 1
VE5A Local Bus VLB 653

-‘so. that
a VLB adapter can use both the ISA (or EISA/MCA also) and the VLB part of a slot, two
$’ atmct contact strips are normally included. The somewhat ulargen> strip with considerably
‘p thicker contacts represents the ISA oart. the tiiieree‘mntacts raresent the VLB section. If vou
?. have an adapter rbr a VtB/MCA slot in front”of you, the twb contact strips appear &ilar
2’ (because the VLB slot still represents a siandard MCA slot with resped to the contact geometry).
& DffeFntly coded b;dges, however, prevent the incorrect installation of such an adapter.
C~“tray to PCI, VLB does not require a different type of board. Despite this, for example, it is,
possible to use energy saving adapters which operate internally with 3.3 V. It is only necessary
:for all the signal levels and signal flows to satisfy the VLB specification. A JTAG boundary scan
i kt is also not provided, and so no pins are implemented for it,
654 Chapter 25 \

25.9 VLB Signals

Here, I would like to explain the VLB contacts and the meaning of their corrqxmding signals.
As VLB, like PCI, supports busmasters on the VLB adapters, all pins are bidirectional. To show
the data and signal flows more clearly, I have assumed that the CPU (or another unit on the
motherboard) represents the current busmaster for the given transfer direction. The pins are
listed alphabetically in 3%bit and 64-bit groups. Note that, contrary to PC], no physically separ-
ate 64-bit section is provided. In its place,- the necessary
- signals are multiplexed with the address
signals A31-AZ, M/n, W/fi, ID4 and BE3-BEO. In addition, a VLB adapter can also use the
ISA or EISA signals of the corresponding ISA or EISA adapter.

25.9.1 Standard 32-bit Section

A32-A2 (0)
Pins AZl-A23, A%A26, A28-A34, A3&A37, B21,823r.B2g, B30-B31, B33-B37, B3%B40

These 30 address pins form the VLB address bus. Each VLB operation (single or bunt transfer)
starts with an addressing phase during which the pins A3-A2 transfer an address. The VLB
dws not support parity formation for the address bus.

ADS (0)
Pin A45

By an active address strobe signal with a low level, the VL bus control indicates the start of a
bus cycle. A31-A2 then lead with a valid address.
- -
BF3-BE0 (0)
Pins A39, A41-A42, A44

The byte-enable signals are transferred on these four pi=. An active BEx signal with a low level
indicates that the corrqmnding eight data lines will deliver a valid byte.

Pin 852

An active burst last signal with a low level indicates that the current burst cycle will be com-
pleted with the next BRDY signal, that is, the cur&t transfer is the last transfer of a VLB burst.

BRDY (I) 1
nn 851

The burst ready signal ends the current burst transfer. To complete the whole burst cycle
consisting of an addressing phase and four subsequent data phases, BLAST must also be active.
The LRDY signal is provided for single transfer cycles, thus VLB carries opt an i486-compatible
VESA Local BUS VLB 655

D31-DO (110)
pins AI-AZ, A&A9, All, AK?-A16, AM-A20, Bl-B5, B7-88, BID-B13, BlL?-B19

These 32 address pins fom the VL.B data bus. The byte-enable signals set which of the four data
by& in a data transfer actually tnnsfer valid values. VLB does not support parity formation for
the data bus.

XM-ID0 (0)
Pins AWA.56, B53-BS4

These five pins send identification signals to the VLB targets to establish the type and speed of
the CPU, and also the burst capabilities and the possible bus width (16 to fflbits). They are
typically sensed invnediately after a reset; the BIOS or the VL bus ccn,tmller of the VLB sub
system are ContigUrea accordingly. The signals on ID4-ID0 have the following meanings:

Burst capability
Burst possible
Read burst 16; 32 bits
No burst 16. 32 biU
NO burst 16. 32 bits
Reserved Reserve.2
Readlwrite burst 16, 32. 64 bits

lRQ9 (I)
This pin operates as a level-higgered interrupt pin with an active high level. It is directly
cawxted to IRQ9 of the ISA bus. IRQ9 is also prnviaed to enable adapters to issue hardware
interrupts, which the corresponding ISA or EISA slot and its signals do not use. Usually, VLB
atlap@ issue intem_pts through the ISA or ElSA contact strips.
. _
Pin A58
If a unit performs a cache invalidation cycle on the CPU, it activates the local external address
I strobe signal. Every VL busmaster (that is, not the CPU) Sets LEADS to a low (active) level, if
656 Chapter 25

it performs a memory access. In this way, a” invalidation cycle is automatically initiated. As a

result, the CPU can react with an active WBACK signal if the inquby has led to a hit of a
modified line in the write-back cache. The CPU the” immediately issues a write-back cycle and
the VL busmaster must wait for the completion of the wit&ack operation.

LBS16 fI,
If the addressed VLB target operate with a width of only 16 bits, it must activate the local bus
size 16 signal. The VL bus controller the” perfornw the corresponding number of 16bit accesses
in place of the fewer 32-bit accesses.

LCLK (0)
This pin indicates the local clock speed for all VLB transfers. According to the specification, it
the CPU is supplied with a &clock cycle (like a” f??%DX/SX, for example), then PCLK must
be divided by two in order to pmduce LCLK. LCLK always represents a lx-clock signal.

LDEVoo (I)
Pin A49
If a VLB target reog”izes that it represents the target of the current address (and M/m), it
aclivates the local device signal to inform the VL bus mntmller that it is the target. Only if a
target actually activates LDEV does the VI, bus contmller send the associated cycle on the VL
expansion bus.

Pin A48
The local ready signal indicates that the target of a cycle has completed the request. iRDy is
only used for single transfer cycles, the separate signal BRDY is provided for burst cycles. Thus.
VLB performs i4S6-rompatible bursts.

LREQce-, LGNTa> (I, 0)

Pins A50, A52
If a VL busmaster in slot x requests control of the VL bus, it activates the local request signal.
r’ If the VL bus controller can hand over mnti of the VL bus to the questing busmaster after
a” arbitration phase, it reacts by sending out the corresponding active local bus grant signal
; with a low level.
. 1
. km, D/c, W/ii (0, 0, 01
Pins 844, B45,B43
The signals Memory/IO, Data/Command and Write/Read indicate the type of bus cycle. With this,
the possible combinations of M/m, D/T and W/E have the following associated meanings:
- VESA Local Bus VLB 657


For an iM-compatible VL bus cycle, the byte-enable signals BE?-BE0 also indicate the type of
special cycle as in the i486. This is similar to the halt/shutdown condition of an f386mmpatible
bus cycle.

Pin 848
The VLB mntroller transfers the ready return signal at this pin to all VL busmasters and VL
targets. RDYRTN indicates that a VLB cycle has been completed. For VLB frquendes over
33 MHZ. RDYRTN can precede the LRD\i signal by one LCLK cycle (in this context, note the
it local bus setup in the BIOS).
If ..
1st RESET (01
i An active reset signal with a low level resets all connected VLB units.
it PinA
z ; The write-back signal is produced by the VLB controller and instructs a VL busmaster to inter-
: rupt the current bus cycle. In this way, snooping cycles are supported which lead to a hit in one
f of the caches in a multi-cache system initiating a write-back cycle.

: 25.9.2 64-bit Expansion

’ Contrary to the PC1 local bus, no separate 64-bit expansion is provided in the VESA local bus.
“Tlw expansion of the data bus to 64 bits included in specification 2.0 is achieved by multiplexing
: the most significant data double word D6.%D32 on the existing address pins A31-A2 and also
’ M/i6 and W/W.
;’ ACK64 (1)
; Pin A54
i, An active acknowledge &l-bit transfer signal with a low level indicates that the addressed VLB
j”p” can perform the requested M-bit transfer.
‘. .
Ia:ea (0)
’ Pins A39, A41-A42, A44
- -
Thffebyte-enable signals are, like BF.&BEO,
- - transferred on these four pins. In a similar way to
BE.%BEO, the byte-enable signals BE7-BE4 indicate which bytes of the ma significant DW
%ction of the &I-bit data bus transfer authentic values.
658 Chapter 25

D63-D32 (l/O)
Pins A21423, AZ5426, A28434, A36437, B21,823_828,03HI31, 833-837, 63%B40,843,
These 32 data pins form the expansion of the data bus to 64 bits. iBs64 and ACK64 must both
be active before a 64-bit transfer can be performed.

LB%4 (0)
Pin 841
The VL bus controller or the acttve VL busmaster activates the local bus size 64 signal, in order
to indicate to the target that it wishes to perform a M-bit transfer.

. ..