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A Appendix 7SJ64

7SJ642∗–∗F/G

Q1 IA
Q2 R1
BO1
Q3 R2
IB BO2
Q4 BO3 R3
Q5 R4
IC
Q6
Q7 R5
I4 BO4
Q8 R6

R15 Va R7
BO5
R8
R17 Vb
R18 Vc J1 (–)
R16 J2 (+)
R13 V4
*) J3
R14 BO6
F5 J4
BI1 BO7
F6 BI2 K18
F7 BI3 BO8
F8 BI4 K17
F9 BI5 BO9
F10
R9 J7
BI6 B10
R10 J9
B11
J8
R11 BI7
R12 J11
BO12
J12
K1 BI8
K2 BI9
K3 BI10
K4 BI11 Live status F3 1)
K6
Jumper: 1–2 NO
BI12 contact 1 F4
K7 Jumper ) (NO, NC) 2–3 NC
BI13
K8 BI14 +
K9 Power (~ )
F1
BI15
K5 supply - F2
K10 BI16
K11 BI17
Assignment of Pins of Interfaces,

K12 BI18
refer to Table 3-35 and 3-36 in

K13 BI19 Additional Port D


K14
K15 BI20 Rear Service Port
K16 C
Subsection 3.2.1

Rear SCADA Port B

Time Synchronization A

Front PC Port

)
*High-duty relays
Earthing at the Interference suppression
Rear Wall capacitors
MP, 22 nF, 250 V
Serial Operating Interface
(to panel or door)

Figure A-43 General diagram 7SJ642∗–∗F/G (panel surface mounting without operator panel)

468 7SJ62/63/64 Manual


C53000-G1140-C147–1

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