2138 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO.

6, NOVEMBER 2007

A Novel Switching Sequence Design for

Five-Level NPC/H-Bridge Inverters With Improved
Output Voltage Spectrum and Minimized
Device Switching Frequency
Zhongyuan Cheng, Member, IEEE, and Bin Wu, Senior Member, IEEE

Abstract—This paper presents a novel switching sequence

design for the space-vector modulation of high-power multi-
level converters. The switching sequences are optimized for the
improvement of harmonic spectrum and the minimization of
device switching frequency. Compared to other commonly used
switching sequences, the output spectrum of the proposed design
shows higher inverter equivalent switching frequency. Meanwhile,
the device switching frequency is reduced by using a flexible
switching pattern. The proposed switching sequence has been
simulated and experimentally tested on a 5-level neutral point
clamped H-bridge based inverter. The results from both simu-
lations and experiments consistently verify the above-mentioned
features.
Index Terms—Multilevel power converter, power conversion Fig. 1. Topology of a 5-level NPC/H-bridge inverter.
harmonics, space vector modulation (SVM), switching loss.

I. INTRODUCTION supplied by isolated dc sources to . In practice, the dc

sources are often composed of multipulse diode rectifiers.
Space vector modulation (SVM) with 7-segment switching

M ULTILEVEL power topologies are increasingly used

in high power medium voltage drives [1], [2]. One of
the popular converter topologies is three-level neutral point
clamped (NPC) inverter. Using 5500 V switching devices such
as IGCTs and IGBTs, the three-level NPC inverter can operate
with a line-to-line output voltage up to 4160 V without con-
necting switching devices in series. If a higher output voltage is
required, one of the viable methods is to increase the number of
inverter voltage levels. By combining the NPC and H- bridge
topologies, a five-level NPC/H-bridge topology was proposed
in 1990 [3] and then utilized by MV drive manufacturers [4].
As shown in Fig. 1, each phase of the inverter consists of two
NPC arms. One arm is connected to the output terminal and
the other is connected to the neutral point . The H-bridges are
Manuscript received November 16, 2006; revised February 20, 2007. The au-
thors would like to thank the Nature Sciences and Engineering Research Council
of Canada (NSERC) for the financial support of this work. This paper was pre-
sented in part at the 37th IEEE Power Electronics Specialists ConferenceJeju,
Korea, June 2006. Recommended for publication by Associate Editor P. M. Bar-
bosa.
Z. Cheng is with Rockwell Automation Canada, Cambridge, ON N1R 5X1
Canada (e-mail: gcheng@ra.rockwell.com).
B. Wu is with Ryerson University, Toronto, ON M5B 2K3 Canada (e-mail:
bwu@ee.ryerson.ca).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2007.909244
0885-8993/$25.00 © 2007 IEEE
sequences is commonly used for 2- and 3-level topologies [1],
[2], [5]–[7]. However it is difficult to implement the 7-segment
SVM for the NPC/H-bridge topology for two reasons. The first
reason is that the space vector diagram of the NPC/H-bridge
inverter is much more complex than that of 3-level inverters.
The vector diagram of the NPC/H-bridge inverter contains
125 switching states and 61 space vectors, comparing to 27
switching states and 19 space vectors for three-level inverters.
This causes two-fold difficulties for SVM: heavy real-time
computation load and overwhelming complexity of switching
sequence design. The computation load has been successfully
reduced in various ways by simplifying the required calcula-
tions to locate the reference vector and calculate the duty cycles
[8]–[10]. There are numerous publications [6], [7], [11]–[14]
on the application aspects such neutral voltage stabilization,
over-modulation, common mode voltage reduction, SVM for
some special topologies or control schemes. However, fewer
authors address the switching sequence design for multilevel
topologies [15]–[17]. Effective 7-segment switching sequence
for multilevel topologies, such as NPC/H-bridge, remains a
challenge. Secondly, special consideration should be taken to
balance the switching loss of the arms. Therefore the modula-
tion scheme used for NPC/H-bridge inverters in commercial
products is multilevel sinusoidal-PWM (SPWM) [4].
The main focus of this paper is on the switching sequence
design for multilevel topologies. The design of a novel flex-
CHENG AND WU: A NOVEL SWITCHING SEQUENCE DESIGN FOR FIVE-LEVEL NPC/H-BRIDGE INVERTERS 2139

ible three-segment switching sequence for the five-level

NPC/H-bridge inverter is presented. The proposed modulation
scheme can be used to improve the output voltage spectrum
while minimizing the device switching frequency. Extensive
simulations and experiments are carried out to verify the per-
formance of the proposed design. Although the design was
initiated for the NPC/H-bridge inverter, it is generic for any
multilevel converter topology.

II. INVERTER EQUIVALENT SWITCHING FREQUENCY

AND EXTRA SWITCHINGS

A. Inverter Equivalent Switching Frequency

Before elaborating the proposed switching sequence, three
important frequencies in SVM are defined: Fig. 2. Sector I of a 5-level inverter space vector diagram.
SVM sampling frequency : the reciprocal of the SVM
sampling period . It is equivalent to the carrier frequency
in SPWM schemes.
Device switching frequency : the switching fre-
quency of the active devices. For multilevel inverters, it
happens quite often that the devices operate at different
switching frequencies. The average device switching
frequency is defined as the total number of
switchings of all active devices per second divided by the
number of devices. For a given topology, the ideal average
device switching frequency is the average
devices switching frequency assuming there are no switch-
Fig. 3. (a) 7-segment sequence. (b) 3-segment sequence.
ings between the boundaries of two adjacent switching
sequences. In other words, all switchings are caused by
changes of switching states within a sampling period. In rather than 96 individual triangles. The switching states associ-
reality, the actual average device switching frequency, ated with four triangles are also shown in the diagram. When the
, is often higher than . reference vector is located in triangle (called active
Inverter equivalent switching frequency : the fre- triangle hereafter), the SVM sampling period can be split by the
quency of the center of the first sideband in the spectrum switching states at the vertices of the triangle. These switching
of the line-to-line voltage. It is the equivalent switching states can then be arranged in time domain to form a seven-seg-
frequency seen by the load. This parameter can be used to ment switching sequence such as
evaluate the harmonic performance of an SVM algorithm. ,
For a given multilevel topology, is related to . or a three-segment sequence such as
Obviously, a higher inverter equivalent switching frequency , as shown in Fig. 3(a) and (b), respectively. To
is desirable for better waveforms while a lower device switching minimize the device switching frequency, a general constraint
frequency is desirable for switching loss reduction. must be satisfied for switching sequence design: the transition
from one switching state to the next involves only two switches
B. Three- and Seven-Segment Switching Sequences in the same inverter arm, one being switched on and the other
In space vector modulation, the reference vector is synthe- switched off [1].
sized by the nearest three stationary vectors. The whole sam- The ideal average device switching frequency can be deduced
pling period is assigned to different switching states according from Fig. 3. For the 7-segment sequence, each phase has one
to the duty cycles calculated from the “volt-second” balance complete switching action (an “on” transition and an “off” tran-
principle [1], [2], [5]–[10]. sition) per sampling period, and each transition involves two ac-
Fig. 2 shows a sector in the space vector diagram for the tive switching devices. With 24 active devices in the topology,
5-level NPC/ H-bridge topology. The sector is meshed by 16 the ideal average device switching frequency for the 7-segment
equilateral triangles. The design of switching sequence can SVM is
be significantly simplified by classifying the triangles into
(1)
four types: , and [10]. Types and contain
odd number of switching states while and contain Similarly, the ideal average device switching frequency for
even number of switching states. and triangles stand the 3-segment SVM is
upward and and downward. With this classification, the
switching sequence can be designed for only four triangle types (2)
2140 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

For the 7-segment SVM, each phase obtains a complete dis- ending state of the first sequence, . Minimization
crete sample in a sampling period as shown in Fig. 3(a). Thus, of extra switching is essentially to minimize the difference
the inverter equivalent switching frequency is equal to , between switching states and .
that is It can be achieved by making flexible selection of the next
leading state based on the historical informa-
(3) tion of . Knowing the previous ending state
, the detailed design procedure of the flexible
For the 3-segment SVM, each phase obtains a complete 3-segment switching sequence is as follows.
sample every two sampling periods, and therefore the inverter Step 1: Selection of Next Leading State: For any switching
equivalent switching frequency is state , define its state value
(4) (5)

It can be observed from (3) and (4) that with the same de-
vice switching frequency, the inverter equivalent switching fre- Let us also define two parameters to describe the switching
quency of 3-segment SVM is 50% higher than that of 7-segment state transition: total state-value change and phase state-
SVM. value change

C. Extra Switchings (6)

Detailed research indicates that the 7-segment switching se-
(7)
quence has the following constraints [1], [10].
1) In any active triangles, the switching sequence must start
Then the leading state of the second switching sequence can
from a vertex with more than one redundant switching
be selected by the following steps:
state. This has specific meaning when some redundant
1) find the subset of switching states with minimal from
switching states are dropped deliberately for simplicity.
all the switching states of the next active triangle. This cri-
A common way to drop the redundant switching states is
terion effectively minimizes extra switchings. If there is
to use only the middle states [10], [17]. For a vertex with
more than one state in the subset, then;
even number of switching states, only two middle states
2) choose the states with minimum from the subset. This
are used, while for a vertex having odd number of states,
criterion is to limit the change of voltage levels thus avoid
only one middle state is selected. Thus, the 7-segment
unreasonable large voltage transition in the waveform.
sequence can only start from vertices with even number
Generally the leading state can be singled out by these two
of switching states.
steps. If there is still more than one state, then;
2) At the end of the sampling period, the sequence must
3) select the state with least state value for the completeness
switch back to the starting vertex because the last switching
of the algorithm.
state is always the same as the first switching state.
Fig. 4 shows two examples of selecting the next leading state.
Those two constrains make the 7-segment sequence less flex-
In the figure the reference vector is moving into Triangle 14
ible: when two consecutive reference vectors are located in dif-
from Triangle 6. Case 1: the switching sequence in Triangle 6
ferent triangles, extra switchings may happen at boundaries. It
ended up with [2,0, 1]. The state [2,1, 1] in Triangle 6 will be
can be shown that extra switchings will cause an increase in de-
immediately selected by Step (1). Case 2: the ending state was
vice switching frequency by an amount given by ,
in Triangle 6. States [2,1, 2] and [1,0, 2] will be
where is the fundamental frequency. The extra switchings are
the subset after Step (1). Further by Step (2), [1,0, 2] will be
more likely to happen at higher modulation index or lower sam-
singled out and the transition is limited to one voltage level.
pling frequency, especially for high-power converters, where
Step 2: Design of Switching Sequence: For convenience, the
the switching frequency of the converter is normally around
middle states of a triangle are numbered as through in de-
500 Hz for the minimization of switching losses [1], [5]. On the
scending order of state values. For example in shown in
other hand, three-segment switching sequences are free of these
Fig. 2, State corresponds to the switching state [2,1, 2] and
constraints. In what follows, a flexible 3-segment switching se-
to . This numbering system brings remarkable
quence is proposed for the minimization of the extra switchings
convenience to the implementation of the algorithm because the
for multilevel converters, which will lead to minimal switching
state values of the switching states in the same triangle are al-
losses.
ways consecutive integers.
Fig. 5 shows the 3-segment sequences when the active tri-
III. DESIGN OF THREE-SEGMENT SWITCHING SEQUENCE angle is Type . In the diagram, each arrow-headed line runs
Consider the transition between two sampling periods. through three switching states, forming a 3-segment sequence.
The switching sequence of the first sampling period is For example, if the leading state is , then switching sequence
and is . Three kinds of switching sequences are
the second sequence is available for . One of the three sequences, or their reversals,
. Extra switching occurs when the leading state will be adopted depending on the leading state. The 3-segment
of the second sequence, , is not the same as the sequences can also be designed for to in a similar way.
CHENG AND WU: A NOVEL SWITCHING SEQUENCE DESIGN FOR FIVE-LEVEL NPC/H-BRIDGE INVERTERS 2141

Fig. 4. Example of the selection of leading state. Case 1: ending state is

0 0 0
[2,0, 1]. Case 2: ending state is [2; 1; 2].
Fig. 6. Example of the proposed 3-segment switching sequence without extra
switchings when V crosses triangle boundaries.

TABLE I
DECODERS FOR FIVE-LEVEL NPC/H-BRIDGE INVERTER

Fig. 5. Switching sequence for T .

Fig. 6 shows an example of the proposed 3-segment switching

sequence without extra switchings when crosses triangle
boundaries. Consider the proposed 3-segment SVM with
, , where is the fundamental frequency
and is the normalized modulus of the reference vector. Note:
There are three sampling points , , and in the sector. The 1) Decoding scheme is similar for phase b and c.
3-segment switching sequences can be obtained by following 2) V and V are the arm voltage normalized by half dc link voltage.
the proposed design procedure. The results are illustrated by 3) For NPC/H-bridge inverter, S = V 0 V (refer to Fig. 1).
dashed lines with circled switching states in the figure. The
switching sequence can also be expressed by Step 3: Decode of the Switching Sequence: If the switching
states are viewed as digital codes, the modulator can be treated
switching sequence @ A: as a decoder translating the codes into gating signals. For ex-
; ample, if the code is [2, 2, 2], it should be decoded in such
switching sequence @ B: a way that switches , , , , , , ,
; and , , , , and shown in Fig. 1 are turned on,
switching sequence @ C: and the other switches are turned off.
. The decoder generates gating signals for all of the five pos-
sible code values: 2, 1, 0, 1 and 2. Code “1,” “0,” or “ 1”
It can be clearly observed that there are no extra switchings can be generated by different circuit states. Impropriate decoder
when the reference vector moves across the boundaries of the design results 1) unreasonable voltage step changes, such as
triangles. In addition, each transition within a sampling period from “1” to “ 1” in the same inverter arm, which involve two
involves only one voltage step change realized by turning one voltage step changes and may cause commutation failure and
switch on and the other off in the same inverter arm. The general high , and 2) unbalanced switching, which causes uneven
constraint for switching sequence design is satisfied. device switching loss and heating.
2142 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

Fig. 7. Balanced gating pattern by swapping decoding schemes.

Fig. 9. Simulated spectrum of line-to-line voltage of NPC/H-bridge in-

verter with 3-segment SVM. (m = 0:87, f = 60 Hz, f =f = 42,
f = 630 Hz): (a) spectrum over 0–12.5 kHz and (b) spectrum
over 0–5 kHz.

Fig. 8. Simulated waveforms of NPC/H-bridge inverter with 3-segment SVM.

(m = 0:87, f = 60 Hz, f =f = 126, f = 630 Hz).

There are two different circuit states corresponding to code

“1” or “ 1”, and three circuit states for “0”. Altogether, 12
decoding schemes can be identified for the NPC/H-bridge
topology. It has been found that two of these decoding schemes
can satisfy the general constraint for switching pattern design
mentioned earlier in Section II-B. Table I illustrates the details
of these two decoding schemes.
It should be pointed out that the conduction angle of the
switching devices in the NPC inverters may not be equal,
leading to unequal conduction losses [1]. This problem can be
effectively solved by using the proposed two decoding schemes
alternatively. Fig. 7 shows a balanced gating pattern of the top
and bottom switches of phase when the decoding schemes
are swapped every three fundamental cycles. In addition, this Fig. 10. Simulated spectrum of line-to-line voltage of NPC/H-bridge in-
arrangement also makes the switching frequency of each device verter with 7-segment SVM. (m = 0:87, f = 60 Hz, f =f = 42,
f = 630 Hz) (a) spectrum over 0–12.5 kHz, (b) spectrum over
the same. As a result, the switching losses are also evenly 0–5 kHz.
distributed among all active switches.

IV. SIMULATION RESULTS respectively. The inverter equivalent switching frequency of

Fig. 8 shows the simulated voltage waveforms for the five-
level NPC/H-bridge inverter with the flexible 3-segment SVM,
where is half of the total dc link voltage. The line-to-neutral
voltage has five voltage levels and the line-to-line voltage
is of nine voltage levels.
To compare with the conventional 7-segment SVM, the
spectrum and actual device switching frequency are checked
with various modulation indices and SVM sampling fre-
quency . For fair comparison, the same ideal average device
switching frequency is used for the two schemes
under investigation.
Figs. 9 and 10 are the spectra of the output line-to-line
voltage with 3-segment and 7-segment switching sequences
the 3-segment SVM is higher. By comparing Figs. 9(a) and
10(a), which show the spectra over a wide frequency range
(up to 12.5 kHz), the inverter switching frequencies of the 3-
and 7-segment SVM are 3780 and 2520 Hz, respectively. The
inverter switching frequency of the 3-segment SVM is 1.5 times
that of the 7-segment SVM, which is consistent with (3) and
(4).
Lower order harmonics can be further compared in Figs. 9(b)
and 10(b), which give the spectra over a narrower band
(0–5 kHz). The proposed 3-segment switching sequence gener-
ates the low order harmonics with much lower magnitude.
Fig. 11 shows a comparison of actual device switching
frequencies of the proposed 3-segment and
CHENG AND WU: A NOVEL SWITCHING SEQUENCE DESIGN FOR FIVE-LEVEL NPC/H-BRIDGE INVERTERS
Fig. 11. Actual average device switching frequency
(f = 630 Hz).
Fig. 12. Simulated results of 9-level CHB topology with 3-segment SVM.
(m = 0:87, f = 60 Hz, f =f = 252, f
line-to-neutral voltage, (b) line-to-line voltage, and (c) spectrum of line-to-line
voltage.
conventional 7-segment SVM schemes. It can be clearly ob-
served that the normalized actual device switching frequency
of the proposed switching sequence is
lower than that of the 7-segment sequence. The actual device
switching frequency is reduced by 30–90 Hz, or 4.8% to 14.3%
of 630 Hz. This implies that the use of the proposed flexible
3-segment SVM scheme can reduce the switching losses of the
inverter. This conclusion also holds for the inverter operating
at other switching frequencies.
The proposed 3-segment SVM is virtually applicable to any
multilevel topology. For example, it can be used for cascaded
H-bridge (CHB) based inverters. Fig. 12 shows the simulated
results of the application to a 9-level CHB based inverter. It
is clear from Fig. 12(a) and (b) that the line-to-neutral voltage
waveforms contains nine levels and the line-to-line voltage is
of fifteen levels. The inverter equivalent switching frequency
can be calculated by (4), and can also be identified from
Fig. 12(c), which is 7560 Hz, 12 times the ideal device switching
frequency of 630 Hz.
2143
versus m .
Fig. 13. Block diagram of the experiment setup.
V. EXPERIMENT RESULTS
A 10-kVA five-level NPC/H-bridge based prototyping
converter system was built to verify the performance of the
proposed flexible 3-segment SVM. The block diagram of
the setup is shown in Fig. 13. The power circuit consists of
an NPC/H-bridge based inverter powered by dual 18-pulse
transformers and diode rectifiers [18]. The control is based
on the dSpace Rapid Control Prototyping system. Twelve
gating signals are generated on pins for the 12
top and bottom IGBTs. These signals are reshaped, amplified,
isolated by an interface board. Another 12 complementary
= 630 Hz): (a)
gating signals are also generated by the interface board. All
the 24 gating signals are passed to 12 gating boards to control
the IGBTs. The collector-to-emitter voltages of all IGBTs are
monitored. In case of abnormal operation, an error signal will
be sent to to forbid the gating signals. Both 3-segment
and 7-segment switching sequences are implemented on this
prototype to compare the performance of the algorithms.
Fig. 14 shows the waveform and spectra of the output voltage
of the NPC/H-bridge inverter with flexible 3-segment SVM at
60-Hz fundamental frequency. It is clear in Fig. 14(b) that the
inverter equivalent switching frequency is 3780 Hz, or .
The spectra show that contains triplen harmonics, which do
not appear in the line-to-line voltage due to the three-phase
balance.
To compare harmonic performance, Fig. 15 shows the
spectrum resulted from the 7-segment SVM with the same
. Compared to Fig. 13(b), the most distinct
difference is the center of the first sideband is 2520 Hz, which
is also the inverter equivalent switching frequency . It is
clear that the inverter equivalent switching frequency is 50%
higher for the flexible 3-segment SVM. This is a very desirable
feature of the proposed SVM scheme. The increasing in
can make motor currents less distorted if the inverter is used in
drive applications, or output filter size smaller if the inverter
2144
Fig. 14. Experiment waveforms (3-segment SVM, f = 60 Hz). (a) Upper
trace: v ; bottom trace: v . (b) Upper trace: spectrum of v ; bottom trace:
spectrum of v .
Fig. 15. Experimental spectrum (7-segment SVM, f = 60 Hz). (Upper trace:
spectrum of v ; bottom trace: spectrum of v ).
is employed for other industrial applications that require a
sinusoidal output voltage.
It should be noted that the experimental waveforms and
spectra given in Figs. 14 and 15 are very consistent with the
simulated results shown in Figs. 8–10.
Fig. 16 shows the spectrum of the output voltages when
and . The spectra obtained by
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007
Fig. 16. Experimental spectra of output voltage. (f = 3 Hz,
f = 90 Hz and m = 0:87): (a) 3-segment SVM,
f = 36f , (b) 7-segment SVM, f = 12f . (Upper traces: spectrum of
v ; bottom traces: spectrum of v ).
3-segment SVM are shown in Fig. 16(a), where the sidebands
can be clearly identified. The inverter equivalent switching fre-
quency is 540 Hz. Fig. 16(b) shows the spectra obtained by
conventional 7-segment SVM, the inverter equivalent switching
frequency is 360 Hz, which is 2/3 of that of the 3-segment
SVM. It can be concluded that proposed flexible 3-segment
SVM scheme works well at very low frequencies. In fact, this
scheme can be applied to any fundamental frequencies of the
inverter.
VI. CONCLUSION
This paper presents a novel flexible 3-segment switching se-
quence for five-level NPC/H-bridge and other multilevel con-
verter topologies. Compared with the conventional 7-segment
SVM scheme, the proposed SVM scheme has the following fea-
tures.
1) Better harmonic spectrum of the line-to-line voltage. The
inverter equivalent switching frequency is 50% higher than
that of the 7-segment sequence. Shifting the center of the
dominant harmonics to higher frequency leads to the re-
duction of stator current THD if the inverter is used in drive
systems or the reduction of filter physical size if the inverter
is employed in other industrial applications where a sinu-
soidal output voltage is required.
CHENG AND WU: A NOVEL SWITCHING SEQUENCE DESIGN FOR FIVE-LEVEL NPC/H-BRIDGE INVERTERS
2) Lower device switching frequency. With an ideal device
switching frequency of 630 Hz, the actual device switching
frequency is reduced by 4.8% to 14.3% due to the mini-
mization of extra switchings. This has a positive influence
on the reduction of the switching losses and the improve-
ments of inverter’s energy efficiency in high power appli-
cations.
3) A special decoding scheme for switching loss balance
among inverter arms. The flexible 3-segment SVM scheme
is generally applicable to any multilevel converters. When
it is used in NPC/H-bridge topology, a special decoding
scheme has been developed to balance the gating patterns,
leading to balanced switching loss among the inverter
arms.
Finally, the performance of the proposed flexible 3-segment
SVM scheme has been verified by experiments on a 10-kVA
five-level NPC/H-bridge prototyping inverter system.
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Zhongyuan Cheng (M’96) received the M.A.Sc
degree in electrical and computer engineering from
Ryerson University, Toronto, ON, Canada, in 2005
and the Ph.D. degree in electrical engineering from
Huazhong University of Science and Technology,
Wuhan, China, in 1995.
In 2006, he joined Rockwell Automation Canada,
Cambridge, ON, Canada, as a Senior Design Engi-
neer. He is currently working on medium-voltage
drive topology and control. His research interests
include pulse width modulation, power converter
topology and design techniques for high-power medium-voltage drives.
Bin Wu (S’89–M’92–SM’99) received the M.A.Sc.
and Ph.D. degrees in electrical and computer engi-
neering from the University of Toronto, Toronto, ON,
Canada, in 1989 and 1993, respectively.
After being with Rockwell Automation Canada
as a Senior Engineer, he joined Ryerson University,
Toronto, where he is currently a Professor in the
Department of Electrical and Computer Engineering
and an NSERC/Rockwell Industrial Research Chair
in Power Electronics and Ac Drives. He has pub-
lished over 120 technical papers and the book High
Power Converters and AC Drives (New York: IEEE/Wiley, 2007). He holds
five U.S. patents with another nine patents pending. His research interests
include high-power converter topologies, variable-speed drives, renewable
energy systems, FACTS, and advanced controls.
Dr. Wu is the recipient of the Gold Medal of the Governor General of
Canada, the Premier’s Research Excellence Award, the Ryerson Sarwan Sahota
Distinguished Scholar Award, the NSERC Synergy Award for Innovation,
and the Ryerson Research Chair Award. He is an Associate Editor of the
IEEE TRANSACTIONS ON POWER ELECTRONICS and a Registered Professional
Engineer in the Province of Ontario, Canada.