You are on page 1of 1

# Computer Engineering 111

## Problem Set #2B

back side will not be checked). Use only black and/or blue ballpoint pen. Show your
complete solution and indicate your final answer. Due on 16 October 2018, 2PM (to be
collected at start of class).

Problem #1. Given the circuit below, with the corresponding propagation delay:

## Gate Fan-in tp,LH tp,HL

(f)
AND 2 0.15 + 0.037L 0.16 + 0.017L
AND 3 0.20 + 0.038L 0.18 + 0.018L
NAND 2 0.15 + 0.037L 0.16 + 0.017L
INV 1 0.02 + 0.038L 0.05 + 0.017L
OR 2 0.12 + 0.037L 0.20 + 0.019L
OR 3 0.12 + 0.038L 0.34 + 0.022L
XOR 2 0.13 + 0.038L 0.45 + 0.025L
Note: L is the equivalent total load of the gate/s
being driven.

INV ➔L=1
AND/NAND ➔ L = f
OR/NOR ➔ L = 1 + 2(f – 1)
XOR ➔ L = 2 + 2(f – 1

a. Identify the critical path and determine the maximum logic delay
b. What is the minimum logic delay to F1? to F2?
c. Consider the following delay parameters of a D-Flipflop: tp,LH = 0.53ns, tp,HL =
0.56ns, tSU = 0.3ns, tH = 0.14ns. Determine the maximum frequency of operation if
all inputs come from a D-Flipflop output and all outputs are fed into a D-Flipflop

Problem #2. Consider the following simple processor, consisting of a pipelined data path
and a finite-state machine based controller. RF, PR, and IR denote edge-triggered flip-flops,
while DP1, DP2 and FSM denote logic modules. Minimum and maximum delays of the
modules are shown in the table next to the Figure. You may ignore the delays of the
interconnect as well as the delays of the registers. The ’s at the clock inputs of the registers
denote the absolute skew between the clock source and the register.

DP1 3 10
DP2 2 8
FSM 1 5

## a. Derive the constraints on the clock skew and

clock period
b. Assuming you are free to set the values of the
skews, determine the minimum possible clock
period
c. What values of the skews will this minimum
period be achieved