You are on page 1of 12

Edward J.

Nowak, Ingo Aller,

Thomas Ludwig, Keunwoo Kim,
Rajiv V. Joshi, Ching-Te Chuang,
Kerry Bernstein, and Ruchir Puri


nnovative device architectures will be necessary to continue thereby demonstrating its compatibility with today’s planar

I the benefits that previously accrued through rote

scaling. Double-gate CMOS (DGCMOS) offers distinct
advantages for scaling to very short gate lengths. Further-
more, adoption of gate dielectrics with permittivity substan-
tially greater than that of SiO2 (so-called “high-k materials”)
CMOS design methodology and automation techniques.

CMOS technology scaling has traversed many anticipated barri-
may be deferred if a DGCMOS architecture is employed. Previ- ers over the past 20 years to rapidly progress from 2 µm to 90
ously, serious structural challenges have made adoption of nm rules, as discussed in the article by Chuang et al. also found
DGCMOS untenable. Recently, through use of the delta device in this issue of the magazine [24]. Currently, two obstacles,
[1], now commonly referred to as the FinFET [2], significant namely subthreshold and gate-dielectric leakages, have become
advances in DGCMOS device technology and performance have the dominant barrier for further CMOS scaling, even for highly
been demonstrated. Fabrication of FinFET-DGCMOS is very leakage-tolerant applications such as microprocessors.
close to that of conventional CMOS process, with only minor Double-gate (DG) FETs, in which a second gate is added
disruptions, offering the potential for a rapid deployment to opposite the traditional (first) gate, have long been recognized
manufacturing. Planar product designs have been converted to [3], [4] for their potential to better control short-channel
FinFET-DGCMOS without disruption to the physical area, effects (SCEs). Such short-channel effects limit the minimum

■ 20 8755-3996/04/$20.00 ©2004 IEEE IEEE CIRCUITS & DEVICES MAGAZINE ■ JANUARY/FEBRUARY 2004
channel length at which an FET is electrically well behaved.
Figure 1 schematically illustrates the advantage of DG-FETs.
Channel GATE Channel GATE
As the channel length of an FET is reduced, the drain poten-
tial begins to strongly influence the channel potential, leading
to an inability to shut off the channel current with the gate.
This short-channel effect is mitigated by use of thin gate oxide XD
(to increase the influence of the gate on the channel) and thin
depletion depth below the channel to the substrate, to shield BODY (Neutral)
the channel from the drain. Gate oxide thickness has been
Single-Gate FET Double-Gate FET
reduced to the point where, at 90 nm CMOS, the power drain
from gate leakage is comparable to the power used for switch-
1. The double-gate device architecture escapes the intrinsic
ing of circuits. Thus, further reduction of the thickness would compromise presented by conventional FETs [5].
lead to unreasonable power increases.
Alternatively, further decrease of the depletion region XD
degrades gate influence on the channel and leads to a slower
turn on of the channel region.
In DG-FETs, the longitudinal electric field generated by the 400 120

Subthreshold Swing (mV/decade)

drain is better screened from the source end of the channel due 350 100
to proximity to the channel of the second gate, resulting in 300

reduced short-channel effects, in particular, reduced drain- 80
induced-barrier lowering (DIBL) and improved subthreshold
swing (S). Therefore, as CMOS scaling becomes limited by leak- 200 60
age currents, DGCMOS offers the opportunity to proceed 150 Single-Gate/Bulk
beyond the performance of single-gate (SG) bulk-silicon or PD- Double-Gate
SOI CMOS. Figure 2 shows MEDICI-predicted DIBL and sub- 20
threshold swing for bulk silicon and (symmetrical) DG devices
0 0
as functions of effective channel length Leff. Both the DIBL and
15 25 35 45 55
subthreshold swing for the DG device are dramatically
improved relative to those of the bulk-silicon counterpart. LEFF (nm)
From a bulk-silicon device design perspective, increased body
2. MEDICI-predicted DIBL and subthreshold swing versus effective
doping concentration could be employed to reduce DIBL; how- channel length for DG and bulk-silicon nFETs. The DG device is
ever, at some point it would also increase the subthreshold designed with an undoped body and a near-mid-gap gate material.
swing, thereby requiring higher threshold voltage VT to keep
the subthreshold current adequately low. Similarly, decreasing
the body doping concentration could improve the subthreshold
swing but degrade DIBL. Hence a compromise is necessary for
the bulk-silicon device design. Note that, for a scaled bulk-sili- 10–2
con (or PD-SOI) device, a highly doped channel/halo must be 10–3 S D
used to control severe SCEs, and lower S for extremely short G
10–4 G
Leff could not be achieved by use of low channel/halo doping.
In Figure 3 simulations of the IDS–VGS characteristics of 10–5
DG and SG FETs shows the steeper turn on of the DG-FET,
|DS (A/∝m)

which results from the gate coupling advantage previously
discussed in Figure 1. This property enables the use of lower 10–7
threshold voltage for the DG-FET for a given off-current. As a DG
direct result, higher drive currents at lower power-supply Bulk Si
voltages VDD are attainable. 10–9

DOUBLE-GATE THRESHOLD VOLTAGE –0.2 0.0 0.2 0.4 0.6 0.8 1.0
The very thin silicon body associated with fully depleted DG- VGS(V)
FETs suggests that the centering of VT could be a challenging
proposition. Three basic techniques have been explored both 3. Simulation of double-gate and single-gate FETs designed for equal
theoretically and experimentally, namely, use of body doping, subthreshold current density at VGS = 0 V illustrates the gain in drive
use of asymmetric gate work function, and use of symmetric current from improved channel control of the double-gate FET. Both
gates contribute to control of the channel potential in subthreshold,
mid-gap work-function gate-electrodes. Each technique will while in the bulk case the gate must compete with the influence of the
be visited briefly. substrate.


Body doping has been the employed on the n+ gate-elec-
technique of choice for VT center- If DGCMOS offers significant trode nFETs and phosphorus
ing in both bulk and PD-SOI pla- halos on p + gate-electrode
nar CMOS technologies. advantages over single-gate pFETs. This option is attractive
Adequate body doping can be
achieved by directly doping the
devices, one must question why in that it fits within today’s man-
ufacturing schemes for CMOS
silicon body or by use of “halo” DG devices have not played a threshold-voltage control and
(also known as “pocket”) ion allows multiple values of VT with-
implants introduced laterally
significant role on the CMOS in a CMOS die.
from the gate edges, or a combi- technology scene to date. Ultimately, concerns sur-
nation of these two techniques. rounding random VT variations
In Figure 4 experimental data for due to the statistical nature of the
n-type and p-type DG-FETs with halo-centered VTs are shown small number of dopant atoms within a transistor point toward
[6]. CMOS-compatible VTs were achieved with body thickness methods of VT centering that are less reliant on silicon doping.
TSi in the vicinity of 60 nm in these DG-FETs using convention- One technique uniquely available to DG-FETs is the use of
al dual-doped polysilicon gate electrodes. Boron halos were asymmetric gates, wherein the two gate electrodes are of materi-

pFET nFET Vd = 1.5V
1E+1 1E–5 nFET
|Id|(A/∝m) 1E–6 pFET
Vd = 0.05V
1E–2 1E–7

1E–4 Tsi = 40nm
1E–5 1E–9
1E–7 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5
–1.5 –1.0 –0.5 0.0 0.5 1.0 1.5
VGATE(V) Vg(V) Gate Doping

4. Drain current versus gate voltage for both n-type and p-type DG- 5. Id − Vg characteristics of Asymmetric-double-gate nFET
FETs integrated on a single die, using halo doping to center VTs [6]. and pFET [7].

NiSi Gate NiSi

Tox = 1.6 nm

Tsi = 25 nm


7. Electron density versus distance from body center for
6. TEM cross section of metal-gate DG-FinFET using nickel-silicide as symmetric-metal-gate and asymmetric-poly-gate FETs. TSi = 5 nm for
the gate electrode (reprinted from [8]). this simulation.


als of differing work functions. In partic-
ular, if one gate electrode consists of
degenerately doped n+ polysilicon and
the second one of degenerately doped p+
polysilicon, then the resultant VT resides
at a point close to the average of the VTs
that would result individually from
exclusive use of each type of electrode in
a DG-FET. Undoped DG-FETs have been
fabricated with CMOS-compatible VTs
(Figure 5) using this technique [7].
Metal gates offer the possibility of
centering threshold voltage with a sin-
gle workfunction for both gate elec-
trodes without relying on body doping.
Many metals with workfunctions near
the middle of the silicon bandgap exist.
Use of these metals in SG-FETs is prob-
lematic since the VT of such devices is
typically above 0.5 V, which is too high
for most CMOS applications. Lower VT
may be achieved by counter-doping the
body, which results in buried conduc-
tion channels in the off-state, thus
degrading short-channel effects. Metal
gates on DG-FETs, on the other hand,
naturally achieve VTs in the vicinity of
0.2 V (the exact value depending on
details) and good short-channel char-
acteristics. Self-aligned DG-FETs with
NiSi2 metal electrodes (Figure 6) and
VTs of 0.1 V and −0.23 V for nFETs and
pFETs, respectively, have been experi-
mentally demonstrated recently [8] as
well as p-type FinFETs with molybde-
num gate electrodes [9].
The choice of strategy for thresh-
old voltage encompasses some inter- 8. Three categories of DG-FET structures describe a large variety of schemes used over the last two
esting implications regarding the decades in attempts to realize DGCMOS (inset SEMs reprinted with permission from [11]–[13].)
formation of the channel inversion
layer in DG-FETs. The inversion carrier concentration (elec-
tron density) for DG-FETs employing symmetric metal gates
and asymmetric polysilicon gates is shown in Figure 7. In
1 Top Gate
the symmetric metal gate case two inversion channels can
be seen, one adjacent to the first gate (x = −2.5 nm) and a
second adjacent the second gate (x = 2.5 nm). At this very
Source Drain
thin body thickness the two channels are substantially Drain
2 3
merged. The asymmetric polysilicon case is obviously quite
different; here the polysilicon electrode adjacent to x = −2.5
nm consists of n+ polysilicon while that adjacent to x = 2.5
nm consists of p+ polysilicon. As a result, for practical gate Bottom Gate 4
voltages, only one channel is formed, adjacent to the n+ Cross-Sectional View Plan View
gate. The p+ gate still contributes to control of channel con-
duction but acts as though it has a thicker effective gate
insulator, consisting of the oxide thickness plus the electri- 9. Four significant obstacles to a successful DG-FET are illustrated, as
cal equivalent (~1/3 × TSi ) of the body thickness. discussed in the text (reprinted with permission from [5]).


Numerous structures for DG-FETs have been proposed and
demonstrated. These structures may be classified into one of
three basic categories [10] illustrated in Figure 8, namely:
✦ Type I, the planar DG, which is a direct extension of
Gate a planar CMOS process with a second, buried gate.
Conduction ✦ Type II, the vertical DG, in which the silicon body has been
rotated to a vertical orientation on the silicon wafer with the
source and drain on the top and bottom boundaries of the body,
Source Drain and the gates on either side.
✦ Type III, today most commonly referred to as a Fin-
FET (with the silicon resembling the dorsal fin of a fish), in
Cross-Sectional View
which again the silicon body has been rotated on its edge
Drain into a vertical orientation so only the source and drain
regions are placed horizontally about the body, as in a con-
ventional planar FET.
DG-FETs have been the subject of much research for over 20
years; hence, if DGCMOS offers significant advantages over SG
Source devices, one must question why DG devices have not played a
significant role on the CMOS technology scene to date.
HFin TFin
In Figure 9, four major obstacles to DGCMOS are repre-
sented schematically. The first three issues are closely related
to one another and consist of 1) definition of both gates to the
same image size accurately, 2) self-alignment of the
Drain source/drain regions to both top and bottom gates, and 3)
alignment of the two gates to one another. These three goals
are critical for short devices to provide high drive current and
LGate low gate capacitance simultaneously. The fourth obstacle is
that of providing an area-efficient means of connecting the
Source Channels two gates with a low-resistance path. These issues are dis-
cussed next for each of the three device types from Figure 8.
Plan View Type I planar DG-FETs are severely challenged to deliver
all of the first three requirements since the “second” gate is
buried below a layer of active silicon. The fourth hurdle also
10. The FinFET structure, a Type III DG-FET, forms channels in a “fin”
of silicon perpendicular to the wafer surface. The gate is formed on challenges the planar DG-FET; a process module is required
both sides. to define the additional contact to the buried gate if extra

FinFET Conventional SOI FinFET Conventional SOI

Nitride/Oxide Films, Nitride/Oxide Films,

Etch Silicon Fins Ion-Implant Extentions and Halos
Etch Silicon Islands
and Source/Drain Regions

Deposit/Etch Spacer
Oxide Isolation Planarization Ion-Implant Sources/Drains, Gates

11. FinFET process flow (I) (reprinted with permission from [5]). 12. FinFET process flow (II) (reprinted with permission from [5]).


space is not to be lost to it, and a low-resistance gate material tion. Ion implantation of source/drain species and halos (or
must be intriduced in the burried oxide. pockets) must differ for obvious geometrical reason but other-
Type II vertical DG-FETs typically address problems 1 and wise are largely similar to conventional planar implantation
4 quite successfully. In this case the gate length is usually steps (Figure 12). Conventional CoSi2 or NiSi2 processes are
defined by the thickness of a deposited gate-electrode materi- used to silicide the tops of the mesas and the gate, for contacts
al, which automatically makes both gates the same length and to source/ drain and gate, respectively.
self-aligned to each other. Similarly, the source
and drain junctions can be symmetrically
defined to have the same alignment to both
1.5 V-Bi-True
gates; however, unique challenges are presented Vwl = 1.5V

to defining both self-alignment of the bottom

junction to the gates and to keeping the para-

Vdata-True (V)
sitic series resistances associated with the bot- V-Bi-True
tom junction low. Furthermore, a space-efficient Write "0"
low-capacitance contact scheme to the lower
junction requires a high-wire act in process 0.5
integration. While high drive currents have been
achieved with Type II structures, high perfor- Write "1"
mance (e.g., low capacitance) and CMOS inte- 0.0
0.0 0.5 1.0 1.5
gration have met with limited progress.
V-BL-True (V)
Type III vertical fin-type DG-FETs have the
advantages of access to both gates, and both Cu-M1
sides of source and drain, from the front of the
wafer. Gate length is conventionally defined
since the direction of the current is in the wafer
plane. Gate width, however, is no longer con- Pull-Down


trolled by lithography; rather, the width is given
by twice the height of the silicon fin HFin (Fig-
ure 10). This aspect will be discussed in more
detail later.


In Figures 11 and 12, a schematic process flow
for the FinFET is compared with that for a planar
Si Substrate
SOI process to illustrate just how remarkably Ground Node
close the FinFET process integration can parallel
today’s advanced CMOS manufacturing technol-
ogy. A conventional SOI wafer can be used as 13. Physical design and electrical function of a 6T-SRAM cell fabricated in 180 nm Fin-
starting material, except that the alignment FET DGCMOS are demonstrated (reprinted with
permission from [14]).
notch of the wafer is preferably rotated 45◦ about
the axis of symmetry of the wafer. The reason for this deviation
is to provide {100} planes on silicon fins that are oriented
along the conventional “x” and “y” directions on the wafer.
The process of defining fins and source/drain silicon is
very similar to that used to define trench isolation in
p-Type FinFET Inverter Out
today’s CMOS. Patterns are defined and etched into the
active (top) silicon layer in both processes. The convention-
al process requires additional processing to fill and pla-
narize the isolation trenches; the FinFET process, on the
other hand, proceeds directly to channel processing, such as
sacrificial oxidations, masked ion implantations for chan-
nels, or specialized passive elements, followed by the gate
dielectric module. Inverter In n-type FinFET
Gate deposition and etch are very similar, with less-severe
14. Tilted-view SEM of FinFET DGCMOS ring oscillator inverter stages
demands on the selectivity of the gate-electrode etch to gate fabricated in 180 nm foundry-compatible rules (reprinted with
oxide, since the oxide surface is orthogonal to the etch direc- permission from [5]).


While demonstration of static operation of DGC-
MOS is key to proving that the device parametrics
can all be centered to the practical values demanded
for VLSI, demonstration of transient operation is
Gate similarly important to demonstrate that the numer-
ous parasitic elements that can degrade circuit per-
formance can be tamed. In particular, low gate
nFET resistance and gate capacitance are critical, as indi-
Source cated by the CV/I delay estimation.
A ring of 60 inverters with a single two-way
W-Via W-Via NAND has been successfully fabricated to
demonstrate this goal. An SEM of a section of
the inverters is shown in Figure 14 [5].
Drain In each inverter stage one fin is used for a
Source single transistor, as shown in Figure 15. nFETs
fin/body and pFETs with W = 240 nm and Lgate = 140 nm
100 nm
made up the ring oscillator. The physical gate-
50 nm
Via to Gate oxide thickness was 2.2 nm with estimated inver-
sion equivalent thickness of 3.2 nm.
15. A single inverter stage and cross-section TEMs of a FinFET Inverter delay as low as 19 ps was measured at
from an inverter are shown.
VDD = 1.5 V. The ring was designed with a three-
stage buffer output directly at the ring frequency;
FinFET CIRCUIT DEMONSTRATION the waveform measured is shown in Figure 16.
Progress toward full CMOS integration of FinFET-DGCMOS Numerous landmarks have been achieved in FinFET-
has been rapid. Experimental operation of an inverter chain DGCMOS, indicating that this DG technology may indeed prove
was demonstrated [6] in 180 nm CMOS with four stages of manufacturable. The remaining challenge, however, is to show
inversion achieved. that real product designs can be efficiently and readily transferred
Subsequently, using a similar process, a six-transistor from planar CMOS designs to FinFET-DGCMOS.
SRAM cell was fabricated (Figure 13), demonstrating success-
ful write, read, and data retention [14]. The SRAM cell was
taken from a 180 nm-node foundry-based physical design; the
active silicon layer was modified, replacing conventional pla-
nar shapes with fins for the six devices and mesas for the con-
tact landings, as seen in the inset to Figure 13.
A tungsten-via, copper interconnect process was used for
the wiring of the cell with no modifications to the standard
foundry processes.

16. Waveform of the buffer output from the ring oscillator shown in 17. Potential for double-gate applications [21]. (a) Low-power design.
Figures 11 and 12 (reprinted with permission from [5]). (b) Variable threshold CMOS. (c) Simplified logic gates [16].


DG devices like FinFETs offer unique opportuni- Trim Level
ties for microprocessor design (Figure 17 ).
Compared to a planar device in the same tech-
nology node, FinFETs have reduced channel and
gate leakage currents. This can lead to consider-
able power reductions when converting a planar
design to FinFET technology [15]. Figure 17(a)
shows an example for the 90 nm technology
node. Utilizing FinFETs would lead to a reduc-
tion in total power by a factor of two, without
compromising performance.
SIT Level
Another possibility to save power arises when
both gates can be controlled separately. The sec-
ond gate can be used to control the threshold
voltage of the device [Figure 17(b) ], thereby Active Area Poly Gate
allowing fast switching on one side and reduced Fin Trim
leakage currents when circuits are idle.
Finally, separate access to both gates could
also be used to design simplified logic gates [Fig- 18. Sidewall image transfer (reprinted with permission from [19]).
ure 17(c)]. This would also reduce power, and
save chip area, leading to smaller, more cost-efficient designs.
However, chip designs using FinFETs must cope with
quantization of device width, since every single transistor con-
sists of an integral number of fins, each fin having the same
height. The following section will describe how existing planar
designs can be converted to FinFET technology and the specif-
a y
ic issues that must be addressed in the design.
As described above, FinFET processing on SOI wafers uses
standard manufacturing process modules [7]. To etch the ultra-
thin (TSi = 15 nm) fins, spacer lithography [sidewall image
transfer (SIT)] [17], [18] is used. Figure 18 shows the principle

Planar Process

Poly Gate

Active Area

Planar P/N=1.5
FinFET Process

Poly Gate

FinFET Devices
FinFET P/N=9/6=1.5

1 2 3 N HFin Active Area Poly Gate Fin Trim

20. NAND2 gate conversion for processing with sidewall image
19. Device width quantization [19]. transfer (SIT) technique.


of this process and, as an example, the layout of a
converted six-transistor (6T)-SRAM cell. Since the
SIT process always generates an even number of
fins, an extra process step is needed for removal of
c2 c2_b
scanc1 scanc1_b fins to allow odd number of fins or otherwise
break fin “loops” where needed. This means, that
for conversion of an existing design, two addition-
al levels have to be introduced, namely the “Fin”
and the “Trim” level (Figure 18). All other design
|2_b levels remain unchanged.
Consider now a planar design to be converted

for processing in the 90 nm FinFET technology
node. The FinFET height HFin together with the
|2 fin pitch (determined by photolithography) defines

the total FinFET device width WFin within the


fb_si fb
given silicon width of the planar device (WP). To
c1_und_b c2_b
get the same or better device strength, (1) in Fig-
ure 19 must be followed [19]. As an example, a

FinFET height of HFin = 70 nm (identical to the

q active layer thickness of the SOI wafer) would ful-
fill this requirement in the 90 nm FinFET technol-
ogy node. This value would result in a minimum
c1_und c2
device width of WMin = 2 × HFin = 140 nm and
also determines the increments in device width
that the designer can use for circuit design.
Figure 20 shows as a second example how a
static NAND2 layout is altered using the original
levels as well as with the two additional levels “Fin”
and “Trim” for SIT processing, and removal of
unwanted fins, respectively. In this case the Trim
level is used to adjust the P- to N-device width ratio
to the original value in the planar design.
For automatic Fin and Trim generation, Fin-
GEN, a software tool, has been developed [20],
which takes the active area and poly gate levels,
and, based on special FinFET ground rules, gener-
ates the additional levels. Figure 21 shows a latch
circuit that has been converted using the automat-
ic generation of the FinFET specific levels. This
circuit (as well as other β-ratio sensitive circuitry)
may additionally require manual adjustment on
the number of fins in the N- and P-devices after
automatic addition of the FinFET levels.
Besides device width quantization, other factors
like width variation, threshold variation, and self-
heating must be taken into account when design-
ing with FinFETs. Table 1 [21] gives an overview of
the design considerations for the different circuits
and elements needed for microprocessor design. It
also shows that a process with multiple threshold
voltages and multiple gate oxide thicknesses is
required to take full advantage of this new device.
As already discussed, the width quantization
imposes some restrictions on device strength
flexibility, but most of them can be absorbed eas-
21. Latch converted to FinFETs (layer convention, see Figure 20). ily when converting an existing design or start-


ing a new design, respectively. Thorough evaluation of hard-
Of course, as stated earlier, Compared to a planar device in ware results will show how to
latches, dynamic circuit styles deal with such effects.
in general, and SRAM cells need the same technology node, Overall, there are no major
careful optimization when
designing with FinFETs.
FinFETs have reduced channel obstacles that prevent use of
FinFETs in the design of micro-
Discrete devices and circuits and gate leakage currents. processors.
for analog applications require Of particular importance are
special attention. As an exam- SRAM cells when considering a
ple, consider a driver/receiver circuit with an ESD protection conversion of microprocessor designs to FinFET technology. In
diode. In a planar process the protection voltage is propor- Figure 22 a 6T-SRAM cell is shown, with the definition of
tional to the total peripheral junction length of the diode. In beta(β)-ratio of the cell. In case of partially depleted-SOI (PD-
FinFET technology the same junction length would require SOI) the β -ratio is evaluated dynamically [22] as the body
more area, because the junction length per Fin pitch may be potential changes during operation. For a fully depleted tech-
only about one-eighth of that of a planar device. nology, such as a FinFET, the β-ratio remains fixed during the
Another example is the total output driver impedance operation. The bit-line capacitance is also reduced as the devices
matching, which is usually implemented with a planar resistor are in a fully depleted state. In the following section a cell that
requiring a silicon block resistor, on a silicon island to adjust has been mapped into a FinFET layout (Figure 22) is compared
output impedance (including the wire to the pad) to 50 . For to the original PD-SOI version.
such applications, and analog circuits in general, special First, a proper fin quantization is essential to achieve
devices may be necessary for optimized designs using FinFETs. appropriate β-ratio. Once this is fulfilled, the feasibility of a
Furthermore, the threshold variation and the effective 6T-SRAM cell in a FinFET design can be demonstrated.
transistor width (Weff) variation of the FinFET have implica- To evaluate the functionality of the cell, bit-select and
tions on chip design with FinFETs. The variation of Weff is sense amplifier circuits (not shown here) are used. The wave-
especially different from that of planar CMOS. Since wide forms are shown in Figure 23. As the word-line (WL) is trig-
FETs consist of many narrow fins, the total Weff tolerance will gered, the cell can be operated first in the read and then in
be the sum of the individual fin height tolerances. An open the write mode (the left node of the cell is “L” and the right
question right now is if the individual fins will all have the node is “R”). The left and right outputs of the sense-amp
same tolerance, or if, for example, local variations that are denoted by “SL” and “SR,” respectively, toggle depending on
due to fin density can lead to circuit functionality problems. the read and write operation. The performance of the FinFET

Table 1. Design considerations with FinFET device quantization [21].

Width Multiple Multiple Self-
∆W ∆Vt Heating
Quantization Vt tox
Design for FinFET +> o.k.
Design Conversion Leakage/
Standard Power/
=> Tradeoffs Performance Performance
Library, Performance
Design Sensitive to Test/Sort Early Mode/ Performance
Static CMOS Optimization
Technology Changes (e.g. Race Issues
Fin Height)
Design for FinFET => o.k.
Local Variation Power/
Latches Design Conversion
=> Functionality Noise Margin Performance Performance
=> Tradeoffs
Impact Optimization
Feedback Devices Critical
Domino Highly Tuned β-Ratio Tolerance
Dynamic Power/
β-Ratio Very Critical (Esp. Fin Density β-Ratio Tolerance Performance Clock-
CMOS Small Circuits) Impact to be P/N Tracking Distribution
=> Finer Width Quantization Investigated
β-Ratio Impact
=> Read/Write/Stability/ β-Ratio Change Power/
SRAM Leakage Optimum? SA=>Margin Performance
β-Ratio Change Minor Issue
Special SRAM Device Might Variation Optimization
be Necessary Delay Variability

R, C, Diodes, Special Devices May Be Decoupling Device

Device Variability N/A N/A Capacitors
... Required Tolerance

Linearity Linearity Power/ Rds Change,

Analog "Analog" Device May Be Performance
Tracking Tracking Thermal
Required Optimization
Asymmetry Asymmetry Coupling


cell (from WL to the sense Finally, the complete design
amplifier output analyzed with a FinFET technology offers a flow for chip design with FinFETs
newly developed basic FinFET is shown in Figure 24. The design
compact model [23]) is better as tactical solution to the gate flow is of course very similar to
compared to a cell in a similar
PD-SOI technology. This is due
dielectric barrier and a the one used for designs using
planar devices. However, to
to the reduction in bitline strategic path for silicon enable a design for FinFETs, addi-
capacitance in case of the Fin- tional tool development is neces-
FET version.
scaling to the point where sary (boxes with orange
Issues such as cell stability, only atomic fluctuations halt background in Figure 24). This
noise, and other quantization includes the handling of the
effects need further investigation further progress. device quantization in the
in order to get a better under- schematics and for circuit tuning
standing when designing SRAM as well as enhanced compact
cells in FinFET technology. modeling and parasitic extraction.

Double-gate devices will enable the continuation of CMOS
scaling after conventional scaling has stalled. DGCMOS/Fin-
FET technology offers a tactical solution to the gate dielectric
Beta Ratio = PL PR barrier and a strategic path for silicon scaling to the point
where only atomic fluctuations halt further progress. The
(Bitline_Left) (Bitline_Right) conventional nature of the processes required to fabricate
Pg L these structures has enabled rapid experimental progress in
just a few years. Fully integrated CMOS circuits have been
Cc demonstrated in a 180 nm foundry-compatible process, and
methods for mapping conventional, planar CMOS product
designs to FinFET have been developed. For both low-power
WL and high-performance applications, DGCMOS-FinFET offers a
most promising direction for continued progress in VLSI.

Edward J. Nowak is with the IBM Microelectronics Division in

Essex Junction, Vermont. Ingo Aller and Thomas Ludwig are
with IBM Entwicklung GmbH in Boeblingen, Germany. Keun-
woo Kim, Ching-Te Chuang, Kerry Bernstein, Rajiv V. Joshi,
and Ruchir Puri are with the IBM T.J. Watson Research Center
in Yorktown Heights, New York.




22. 6T-SRAM cell converted to FinFETs (layer convention, see Figure 20). 23. Compact model simulation for FinFET 6T-SRAM cell.


[1] D. Hisamoto, T. Kaga, Y. Kawamoto, and E.
Takeda, “A fully depleted lean-channel tran- High Level
sistor (DELTA)—A novel vertical ultra thin Design
SOI MOSFET,” in Tech. Digest IEDM 1989,
Compact Model Layout Generation
Washington, DC, pp. 833–836.
Simulation and Checking
[2] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto,
L. Chang, J. Kedzierski, E. Anderson, H. DG-FinFET Device
Takeuchi, Y.-K. Choi, K. Asano, V. Subrama- Model
nian, T.-J. King, J. Bokor, and C. Hu, “Sub Parasictics
50-nm FinFET: PFET,” in Tech. Digest Extraction
IEDM 1999, Washington, DC, pp. 67–70.
Circuit Tuning Schematics
[3] H-S.P. Wong, D. Frank, and P. Solomon,
“Device design considerations for double-
gate, ground-plane, single-gated ultra-thin
SOI MOSFETs at the 25 nm channel length FinFET Hardware
generation,” in Tech. Digest IEDM 1998, Device
San Francisco, CA, pp. 407–410. Quantization
Mask Data
[4] S. Christoloveanu, T. Ernst, D. Munteanu, FinFET Generation
and T. Ouisse, “Ultimate MOSFETs on SOI: Process
Ultra thin, single gate, double gate, or
ground plane,” Int. J. High Speed Electron.
Syst., vol. 10, no. 1, pp. 217–230, 2000.

[5] E. Nowak, T. Ludwig, I. Aller, J. Kedzierski, 24. Design flow for design with FinFETs [21]. Areas with orange background
M. Ieong, B. Rainey, M. Breitwisch, V. Gern- require new developments or extensions to existing tools.
hoefer, J. Keinert, D.M. Fried, “Scaling
beyond the 65 nm node with FinFET-
DGCMOS,” in Proc. IEEE CICC, San Jose, CA, pp. 339–342. [14] E. Nowak, B. Rainey, D.M. Fried, J. Kedzierski, M. Ieong, W. Leipold,
J. Wright, and M. Breitwisch, “A functional FinFET-DGCMOS SRAM
[6] B. Rainey, D.M. Fried, M. Ieong, J. Kedzierski, and E.J. Nowak, cell,” in Tech. Digest IEDM 2002, San Francisco, CA, pp. 411–414.
“Demonstration of FinFET CMOS circuits,” in Proc. 2002 Device
Research Conf., Santa Barbara, CA, pp. 47–48. [15] S.H. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V. Sub-
ramanian, J. Bokor, T.-J. King, and C. Hu, “FinFET - A quasi-planar double-
[7] J. Kedzierski, D.M. Fried, E.J. Nowak, T. Kanarsky, J.H. Rankin, H. gate MOSFET,” in Proc. ISSCC 2001, San Francisco, CA, pp. 118–119.
Hanafi, W. Natzle, D. Boyd, Y. Zhang, R.A. Roy, J. Newbury, C. Yu, Q.
Yang, P. Saunders, C.P. Willets, A.R. Johnson, S.P. Cole, H.E. Young, N. [16] K.W. Guarini, P.M. Solomon, Y. Zhang, K.K. Chan, E.C. Jones, G.M.
Carpenter, D. Rakowski, B. Rainey, P.E. Cottrell, M. Ieong, and H.-S.P. Cohen, A. Krasnoporova, M. Ronay, O. Dokumaci, J.J. Buchignano, C.
Wong, “High-performance symmetric-gate and CMOS-compatible asym- Cabral Jr., C. Lavoie, V. Ku, D.C. Boyd, K.S. Petrarca, I.V. Babich, J. Tre-
metric-gate FinFET device,” in Tech. Digest IEDM 2001, Washington, ichler, P.M. Kozlowski, J.S. Newbury, C.P. D'Emic, R.M. Sicina, and H.-
DC, pp. 437–440. S.P. Wong, “Triple-self-aligned, planar double-gate MOSFETs: Devices and
circuits,” in Tech. Digest IEDM 2001, Washington, DC, pp. 425–428.
[8] J. Kedzierski, E.J. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers,
C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, [17] W.R. Hunter, T.C. Holloway, P.K. Chatterjee, and A.F. Tasch Jr., “A
P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. Rainey, new edge-defined approach for submicrometer MOSFET fabrication,”
D.M. Fried, P.E. Cottrell, H.-S.P. Wong, M. Ieong, and W. Haensch, “Metal IEEE Elec. Dev. Let., vol. EDL-2, no. 1, pp. 4–6, Jan. 1981.
gate FinFET and fully depleted SOI devices using total gate silicidation,”
in Tech. Digest IEDM 2002, San Francisco, CA, pp. 247–250. [18] Y.-K. Choi, T.-J. King, and C. Hu, "A spacer patterning technology for
nanoscale CMOS," IEEE Trans. Elec. Dev., vol. 49, no. 3, pp. 436-441,
[9] Y.K. Choi, L. Chang, P. Renade, J.-S. Lee, D. Ha, S. Balasubramanian,
Mar. 2002.
A. Argawal, M. Ameen, T.-J. King, and J. Bokor, “FinFET process refine-
ments for improved mobility and gate workfunction engineering,” in [19] T. Ludwig, I. Aller, V. Gernhoefer, J. Keinert, A. Mueller, E. Nowak,
Tech. Digest IEDM 2002, San Francisco, CA, pp. 259–262. R.V. Joshi, and S. Tomaschko, “FinFET Technology for future micropro-
cessors,” IEEE SOI Conference, Sept. 29 – Oct. 2, 2003, Newport Beach,
[10] H.-S. Wong, D.J. Frank, P.M. Solomon, C.H.J. Wann, J.J. Welser,
CA, pp. 33–34.
“Nanoscale CMOS,” Proc. IEEE, vol. 87, no. 4, p. 537, Apr. 1999.

[11] J.-H. Lee, G. Taraschi, A. Wei, T.A. Langdo, E.A. Fitzgerald, and D.A. [20] V. Gernhöfer, “FinGEN, a tool for automated FinFET level genera-
Antoniadis, “Super self-aligned double-gate (SSDG) MOSFETs utilizing tion,” unpublished.
oxidation rate difference and selective epitaxy,” in Tech. Digest IEDM [21] I. Aller, “The double-gate FinFET: Device impact on circuit design,”
2001, Washington, DC, pp. 71–74. in Proc. ISSCC 2003, San Fransisco, CA, pp. 14–15 (and visual supple-
[12] J.M. Hergenrother, D. Monroe, F.P. Clemens, A. Kornblit, G.A. Weber, ments pp. 655-657).
W.M. Mansfield, M.R. Baker, F.H. Baumann, K.J. Bolan, J.E. Bower, N.A.
[22] R.V. Joshi, A. Pellela, O. Wagner, Y.H. Chan, W. Dachtera, S. Wilson,
Ciampa, R.I. Cirelli, J.I. Colonell, D.J. Eaglesham, J. Frackoviak, H.J.
and S.P. Kowalczyk, “High performance SRAMs in 1.5 V, 0.18 µm par-
Grossman, M.L. Green, S.J. Hillenius, C.A. King, R.N. Kleiman, W.Y-C.
tially depleted SOI technology,” in Dig. Tech. Papers, Symp. VLSI Cir-
Lai, J.T-C. Lee, R.C. Liu, H.L. Maynard, M.D. Morris, S.-H. Oh, C.S. Pai,
cuits 2002, Honolulu, HI, pp. 74–77.
C.S. Rafferty, J.M Rosamilia, T.W. Sorsch, and H-H. Vuong, “The vertical
replacement-gate (VRG) MOSFET: A 50 nm vertical MOSFET with [23] R. Williams and E. Nowak, “FinFET PowerSPICE compact model,”
lithography-independent gate length,” in Tech. Digest IEDM 1999, unpublished.
Washington, DC, pp. 75–78.
[24] C.T. Chuang, K. Bernstein, R.V. Joshi, R. Puri, K. Kim,
[13] D. Fried, A.P. Johnson, E.J. Nowak, J.H. Rankin, and C.R. Willets, “A E.J. Nowak, T. Ludwig, and I. Aller, “Scaling planar silicon devices,”
sub-40 nm body-thickness n-type FinFET,” in Conf. Digest 59th Device IEEE Circuits Devices Mag., vol. 20, no. 1, pp. 6–19, Jan./Feb. 2004.
Research Conf., Notre Dame, IN, June 2001, pp. 24–25.