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1. What are the types of computer? Personal computer, Notebook computer, Workstations, and Enterprise or Mainframes. 2. What are the functional units of a computer? Input unit, Memory unit, Arithmetic and Logic unit, Output unit and Control unit. 3. What are instructions? Instructions are explicit commands that, • Govern the transfer of information within a computer as well as between the computer and its I/O device • Specify the Arithmetic and Logic operations to be performed. 4. What is a program? A set of instructions for solving a particular problem is called a program. 5. Give some examples for input devices Keyboard, Joystick, Mouse, Lightpen and trackball 6. What is object program? Compiling a high-level language source program in to a list of machine instructions constituting a machine language program is called an object program. 7. What do you mean by bits? Each number, character, or instruction is encoded as a string of binary digits called as bits, each having one of two possible values, 0 or 1. 8. Define RAM. RAM stands for Random Access Memory, which is used to store program and data. It is very faster. 9. What is the function of memory unit? How will you classify it? Memory unit is used to store programs and data. There are two classes of storage namely primary and secondary 10. Define word length. The number of bits stored in each memory location is called word length. Typical word lengths range from 16 to 64 bits. 11. Define memory access time? The time required to access one word is called as memory access time. This time is fixed and independent of the location of the word being accessed.
12. What is memory hierarchy? The memory of a computer is normally implemented as a memory hierarchy of three or four levels of semiconductor RAM units with different speeds and sizes. The small, fast RAM units are called caches. The large and slowest unit is referred to as main memory. 13. What is primary storage and secondary storage? Primary memory is a fast memory that operates at electronic speeds. It is expensive. Secondary memory is used when large amounts of data and many programs have to be stored, particularly for information that is accessed infrequently. Example: Primary storage : RAM Secondary Storage : FDD, HDD, CD-ROM, DVD 14. What is a cache memory? The cache is a small, fast memory. They are tightly coupled with the processor and are often contained on the same IC chip to achieve high performance. 15. What are registers? Registers are high speed storage elements. Each register can store one word of data. Access time to registers is faster than access time to the fastest cache memory. 16. What is the use of secondary storage? Give Examples Secondary storage is used to store large amount of data and programs. Ex: Magnetic disk (FDD, HDD), tapes, Optical disks(CD, DVD) 17. What are registers? Register is a high speed storage element, which are mainly used for storing operands while performing computations. Each register can store one word of data. The registers are vary from one processor to another processor. 18. What are timing signals? Timing signals are generated by the control circuits. Data transfers between the processor and memory are also controlled by the control unit through the timing signals. 19. What is an instruction register? The instruction register (IR) holds the instruction that is currently being executed. Its output is available to the control circuits which generate the timing signals that control the various processing elements involved in executing the instruction. 20. What is a program counter? The program counter (PC) keeps track of the execution of a program. It contains the memory address of the next instruction to be fetched and executed. 21. What is MAR and MDR? The Memory Address Register (MAR) holds the address of the location to be accessed. The Memory Data or Buffer Register (MDR or MBR) contains the data to be written into or read out of the addressed location. 22. What is an interrupt? An interrupt is a request from an I/O device for service by the processor. The processor provides the requested service by executing an appropriate interrupt-service routine.
cleared to 0 C (carry) . It is a measure of performance of the entire computer system.23. The clock defines regular time intervals called clock cycles. cleared to 0 Z (Zero) . What are clock and clock cycles? The timing signals that control the processor circuits are called as clocks. To start a load operation. Explain briefly the operation of 'load'. N×S R Where. It is affected by the speed of the processor. 31. A bus is a group of lines or wires that transmit signals from one place to another place. The load operation transfers a copy of the contents of a specific memory location to the processor. V (overflow) . otherwise. There are three types of buses. the processor sends the address of the desired location to the memory and requests that its contents be read. together with the data to be written into that memory location. cleared to 0. Address bus. 33. Explain briefly the operation of 'store'. Define conditional code register (OR) status register. Define bus. namely.set to 1 if the result is negative. T – Performance parameter R – Clock Rate N – Number of instruction execution S – Average number of basic steps needed to execute one machine instruction. It is used to transfer the contents of source register to any one of the destination register. cleared to 0 .set to 1 if the carry-out results from the operation. therwise. 28. The basic performance equation is given by T = 27. otherwise. Data bus and Control bus. 25. What is processor time? The sum of the periods during which the processor is active is called the processor time. 32. destroying the former contents of that location. The memory reads the data stored at that address and sends them to the processor. The conditional code flags are usually grouped together in a special processor register called conditional code registers or status registers. the disk and the printer.set to 1 if arithmetic overflow occurs. 24. ' 26. What is elapsed time? The total time required to execute the given program is called elapsed time. otherwise. What are the four commonly used flags? N (negative) . Give the basic performance equation. What is a register transfer notation? RD ← RS. Define OS. The processor sends the address of the desired location to the memory. Operating system (OS) is system software which is used to execute our user programs and share resources. The memory contents remain unchanged. The store operation transfers an item of information from the processor to a specific memory location. 29. 30.set to 1 if the result is 0.
35. What is a branch instruction? A branch instruction loads a new value into the program counter. 42. 36. Define absolute mode addressing. The address of this location is given explicitly in the instruction. This is also called direct mode addressing. In absolute mode addressing the operand is in a memory location. 44. What is a zero address instruction? Instructions in which the locations of all operands are defined implicitly is called zero address instruction. Relative Indexed. What is addressing modes? The different ways in which the location of an operand is specified in an instruction is referred to as addressing modes. What are the various addressing modes? Register Direct. The name of the register is given in the instruction. Indexed.B .B.C. Immediate. the operand is given explicitly in the instruction. Such instructions are found in machines that store operands in a structure called pushdown stack. In register mode addressing the operand is the contents of a process register. 38. List the basic instruction types The various instruction types are: Three address instruction. In immediate mode addressing. 40. Register Indirect. What is a two address instruction? The instruction that contains the memory address of two operands is called two byte address instruction. 43. . 41.C. Define register mode addressing. The processor fetches and executes the new instruction at this new address called the branch target.34. One address instruction and Zero address instruction. What is a three address instruction? The instruction that contains the memory address of three operands is called three byte address instruction. instead of the instruction at the location that follows the branch instruction in sequential address order. STORE A. What is a one address instruction? The instruction that contains the memory address of only one operand is called one address instruction. Relative. 37. Example: LOAD A. Example: ADD A. Auto increment/decrement Absolute. Two address instruction. EXAMPLE: Add A. Define immediate mode addressing. 39. MOV B.
the contents of this register are automatically incremented to point to the next item in a list. The processor keeps track of information about the results of various operations for use by subsequent conditional branch instructions. the effective address of the operand is generated by adding a constant value to the register. In index mode addressing. In indirect mode addressing the effective address of the operands is the content of a register or memory location whose address appears in the instruction. In this mode the effective address of the operand is the contents of a register specified in the instruction. Define conditional code flags. 51. This is called straight line sequencing. Define index mode addressing. . If the condition is not satisfied. Example: A= *B Here B is a pointer variable. After accessing the operand. What is a pointer? The register or memory location that contains the address of an operand is called a pointer. one at a time. 55. 53. In this mode the contents of a register specified in the instruction are first automatically decremented and then used as the effective address of the operand.47. In relative mode addressing the effective address is determined by the index mode using the program counter in the place of the general purpose register Ri. Define Auto increment mode. 52. . List the four condition code flags The code flags are: • Negative • Zero • Overflow and • Carry flags. This is done by recording the required information in individual bits called as conditional code flags. EA= X + [Ri]. It can be written as -(Ri). 48. Define indirect mode addressing. in the order of increasing addresses. 49. Then the processor control circuits use the information in the PC to fetch and execute instructions. A conditional branch instruction causes a branch only if a specified condition is satisfied. 56. It can be written as (Ri)+. What is straight line sequencing? To begin executing a program. 50. Define conditional branch. the address of its first instruction must be placed into PC. the PC is incremented in the normal way and next instruction in the sequential address is fetched and executed. Define relative mode addressing. Define Auto decrement mode. 54.
because of the LIFO nature of the stack. in which items can be inserted and deleted at the same end.[Ind]. Consider a two level indirection instruction such as MOV A. Handling of pointers is easy with indirection. INC and BR. What is a stack pointer? Stack pointer is a processor register. removes it from top of stack. (iv) I/O transfer. Why is stack called as last-in-first-out? Stack is called as last-in-first-out (LIFO). • Instruction lengths are smaller in stack based . which is used to keep track of the address of the element of the top of the stack 60. 58. INCREMENT. 63. because the last data item placed on the stack is the first one removed when retrieval begins. it becomes easier to handle pointer of pointers and makes implementation of pointer manipulations easy. What is a bus? What are the different buses in a CPU? The groups of wires that serve as a connecting path for several devices is called a bus. • Lot of overhead involved in maintaining temporary variables in a stack . What are the four basic types of operations that needed to be supported by an instructor set? The basic types of operations are: (i) Data transfer between memory and the processor register.because source and destination specifiers are not required. Hence code length may be smaller. ADDITION. This is called mnemonics. 61. where Ind points to the memory location that contains the address of the operand that needs to be moved to register A. With two level indirections.57. What are mnemonics? When writing programs for a specific computer. ADD. .The different types of buses are: • Data bus • Address bus • Control bus. (ii) Arithmetic and logic operations on Data. The term PUSH is used to describe placing a new item on the stack and POP is used to describe removing the top item from the stack. Give an application of such two level indirection. Compare Stack based architecture with GPR architecture. This end is called the top of the stack. register file stack is invisible to the programmer . (iii) Program sequencing and control. • In stack based. 64. Hence easier to maintain compatibility with future versions where the amount of storage allocated to the stack is increased. but reading in a stack architecture. and BRANCH are replaced by acronyms such as MOV. and the other end is called the bottom of the stack. • Reading a register in a GPR architecture does not affect its contents.only top of the stack is visible. What is a stack? A stack is a storage unit. 59. 62. words such as MOVE.
Hence. What role have they played in the evolution of computers? Software Compatibility: Instruction set will be same for more than one machine. Hardware compatibility: Same hardware components are used to build up one machine. Efficient. Condition codes are 1-bit flags that store the information regarding the results of various operations.65. Regular and Compatible. . Define the terms software compatibility and hardware compatibility. Define underflow. What are condition codes? Can a processor be designed without any condition code? Explain. Discuss the stored program concept. A processor may be designed without condition codes. These are made use of by subsequent conditional branch instructions. The processor will fetch and execute the instructions in sequence.What are the requirements to be satisfied by an instruction set? Instruction set should be Complete. Disadvantage: The instructions can be modified themselves during program execution. 68. They give an elegant way of handling conditional control flow. 69. but it must have some other means of handling change in flow control may be instructions like Compare and Branch if equal to zero 66. 67. What are its advantages and disadvantages? Programs are stored in the main memory. Advantage: It facilitates the programming process. debugging programs will be difficult and error prone. writing. underflow is said to occur. If the result of the arithmetic operation involving n-bit numbers is too small to be represented by n-bits.
otherwise set q0 to 1. the result is denormalized by right shifting the fraction and incrementing the exponent for each shift . .until the exponent within a representable range. 3. For base 2 representations. What is an n-bit ripple carry adder? A cascaded connection of n full adder blocks. What are guard bits? Guard bits are the extra bits retained during the intermediate steps which yield maximum accuracy in the final results. What is the purpose of using fast adder? A fast adder circuit must speed up the generation of the carry signals. • To use an augmented logic gate network structure. 4. 10. It treats both positive and negative 2's complement of n-bit operands uniformly. 1. What are the two approaches to reduce delay in address? • To use fastest possible electronic technology in implementing the ripple-carry logic design or variations of it. What are denormalized numbers? _ Denormalized numbers are those numbers to handle cases of exponent underflow. Subtract M from A and place the answer back in A. • It handles both positive and negative multipliers uniformly. through this cascade. If the sign of A is 1. A normalized number is one in which the most significant digit of the significant is non-zero. Give the algorithm for performing restoring division. Define a normalized number. can be used to add two n-bit numbers. 6. Give the normalized number for base 2 representation. a normalized number is one in which the most significant bit of the significant is one. or ripple. 8. When the exponent of the exponent of the result becomes too small. 7. Booth algorithm has the following features. Shift A and Q left one bit position. What is Booth's Algorithm? Booth's algorithm is a technique for generating a 2n-bit product.UNIT II l. 5. List the two attractive features of Booth algorithm. 2. the configuration is called an n-bit ripple carry adder. 3. 9. The algorithm for performing restoring division is as follows. Since the carries must propagate. • It achieves some efficiency in the number of additions required when the multiplier has a few large blocks of 1’s. set q0 to 0 and add M back to A. 2. .
the number is said to be normalized. Write the Add/subtract rule for floating point numbers. 2) It achieves efficiency in the number of additions required when the multiplier has a few large blocks of 1’s 3) The speed gained by skipping 1 's depends on the data. 14.11. 16. What is a carry look-ahead adder? The input carry needed by a stage is directly computed from carry signals obtained from all the preceding stages i-1. Add or Subtract exponent d. a.1. What is the method of achieving the 2's complement? • Take the. Normalize the result . i-2. What is full adder? A full adder is logic circuit with three inputs and two outputs. rather than waiting for normal carries to supply slowly from stage to stage. 17. What is the advantages (features) of using Booth algorithm? 1) It handles both positive and negative multiplier uniformly. An adder that uses this principle is called carry look-ahead adder. producing a sum and a carry. 1 's complement of the number and add 1 to LSB. 18.0. Give the IEEE standard for floating point numbers for single precision and double precision number. When can you say that a number is normalized? When the decimal point is placed to the right of the first (nonzero) significant digit. Align mantissa c. which adds two bits at a time. which adds three bits at a time giving a sum and a carry 13. 12.2. …. 15. What is half adder? A half adder is a logic circuit with two inputs and two outputs. What is signed binary? A system in which the leading bit represents the sign and the remaining bits the magnitude of the number is called signed binary. Check for Zero b. 19. This is also known as sign magnitude.
It obviously occurs if the sign of the result is different. Delay in CSA is less than delay through the ripple carry adder. and yi in two numbers x and y. Positive underflow and Positive overflow. 26. When does an overflow occur? Overflow can occur when the signs of two operands are the same. 28. 22. The five regions are: Negative overflow. Zero. Exponent underflow. a. Round toward –∞ . During a floating point operation. List the conditions produced during a floating point operation. Define underflow. Write the multiply rule for floating point numbers. . Give the five regions on the IEEE floating point number. Give the logic expression for sum and carry out functions for adding equally weighted bits xi. A circuit to detect overflow can be added to the n-bit adder by implementing the logic expression. Negative underflow. the conditions produced are Exponent overflow. underflow is said to occur. In floating point numbers when so you say that an underflow or overflow has occurred? In single precision numbers when an exponent is less than – 126 then we say that an underflow has occurred. 24. Instead of letting the carries ripple along the rows. Add the exponent and subtract 127 b. If the result of the arithmetic operation involving n-bit numbers is too small to be represented by n-bits. Significant underflow. 27. Round toward 0.20. What are generate and propagate function? The generate function is given by Gi = xiyi and the Propagate function is given as Pi = xi + yi 23. S i = x i y i c i + x i y i c i + x i y i ci + xi y i c i = xi ⊕ y i ⊕ c i C i +1 = y i ci + xi ci + xi y i 25. the alternative approaches are: Round to nearest. In rounding. they can be saved and introduced into the next row at the correct weighted Position. 29. Normalize the result 21. c. Give the four alternative approaches in rounding mode. Round toward +∞. Significant overflow. Multiply the mantissa and determine the sign of the result. In single precision numbers when an exponent is greater than + 127 then we say that an overflow has occurred. Define carry save addition(CSA) process.
• Store a word of data from a processor register into a given memory location. What is the purpose of an instruction decoder? The instruction decoder generates the control signals needed to select the registers involved and direct the transfer of data. All operations and data transfers within the processor take place within time periods defined by the processor clock. 2.UNIT 3 1. • Fetch the contents of a given memory location and load them into a processor register. and the BUSES all collectively interconnected is called as data path. It is a three-bus structure used to connect the registers and the ALU of a processor. • Enable the input of register. 7. . What are the steps accomplished when we wish to transfer the contents of register RI to register R4? • Enable the output of register R1 by setting R1 out to 1. An instruction can be executed by performing one or more operations in. 9. What are those operations? • Transfer a word of data from one processor register to another or to the ALU • Perform an arithmetic or a logic operation and store the result in a processor register. Define Processor Clock. 5. R4 by setting R4 into 1. What are the three steps to execute an instruction? To execute an instruction. This loads data from the processor bus into register R4. Define register file. Define Control Store The micro routines for all instructions in the instruction set of a computer are stored in a special memory called the control store 8. This places the contents of R1 on the processor bus. What is an ISP? ISP stands for Instruction Set Processor. What is a data path? The Register. the processor has to Perform the following steps • Fetch the instruction • Decode the instruction • Fetch operand address • Execute the instruction 3. This unit is also called as processor which executes machine instruction and coordinates the activities of other units. All generalpurpose registers are combined into a singl block called the register file. 4. some specified sequence. the ALU. 6.
. Define micro instructions. (d) Load the resu1t into R1. What is the difference between hard wired and micro programmed control unit? S. What is a hard wired control unit? A hardwired control unit consists of a collection of combinational circuits to generate various controls signals. This address is usually obtained by adding an offset x. What are the actions needed to execute the instruction ADD (R1) R2? To execute the instruction ADD (R2) R1. such as MFC and interrupt requests. (c) Perform the addition. List any two situations where a PC is not incremented every time a new micro instruction is fetched. ALU stands for Arithmetic and Logic Unit. What is a control word? A control word is a word whose individual bits represent the various control signals. the required control signals are determined by. What is a branch instruction? A branch instruction replaces the contents of the PC with the branch target address. 12. The individual control words in the micro routine are called as micro instructions. the PC is loaded with the branch address. 14. • Contents of the control step counter • Contents of the instruction register • Contents of the condition code flags • External input signals. the PC is loaded with the starting address of the micro routine for that instruction. the steps followed are: (a) Fetch the instruction. 15.10. 13. which is given in the branch instruction. 18. 19. It is a combinational circuit that has no internal storage. 11. It performs arithmetic and logic operations on two operands applied as the input. How will you determine the required control signals for hardwired control? For hardwired control. 17. to the updated value of the PC.No Hardwired Control Unit Digital circuits generate the control 1 signals It is conventional design technique 2 Microprogrammed Control Unit The control signals are stored as bit pattern in a ROM It is modem design technique 16. Define ALU. What is a micro routine? A sequence of control words corresponding to the control sequence of a machine instruction constitutes the micro routine. • When a branch instruction is encountered and the branch condition is satisfied. • When a new instruction is loaded into the IR. (b) Fetch the first operand.
What are the disadvantages of microprogramming The disadvantages of microprogramming are: • A microprogrammed CU is slow. What are the advantages of microprogramming? The advantages of microprogramming are: • The design of micro program control unit is less complex. 28. What is bit-OR ing technique? It is a technique for modifying the branch address.20. • An CPU's instruction set can be easily modified. For example. This. Any condition that causes the pipeline to stall is called a hazard. • The microprogram is flexible. Such hazards are often called control hazards. 24. Why does vertical micro programming organization result in slower operating speeds? Because more micro instructions are needed to perform the desired control functions. Pipelined operation is said to have been stalled for two clock cycles. 25. It is used to specify only a small number of control functions in each macro instruction are referred to as a vertical organization 21. one for the direct and one for indirect addressing modes. 27. Define hazard. • For a small CPU with very limited hardware resource a microprogram CU is expensive. requiring the instruction to be fetched from the main memory. technique by pass micro instruction 170 by having the preceding branch micro instructions specifying the address 170 and then an OR gate to change the least significant bit of the address 0 if the direct addressing mode is involved. 29. 23. • Debugging and maintenance of micro programmed CPU is easy. 26. Define horizontal organization. The Pipeline may also be stalled because of a delay in the availability of an instruction. • To include two next address fields within a branch micro instruction. Define vertical organization. What are the alternatives for the bit-OR ing technique? • Use the two conditional branch micro instructions at certain locations. What is the main function of micro programmed control? The main function of micro programmed control is to provide a means for simple. Define control hazards. The minimally encoded scheme in which many resources can be controlled with a single microinstruction is called a horizontal organization 22. this may be a result of a miss in the cache. flexible and relatively inexpensive execution of machine instructions. .
What are the requirements to be satisfied by an instruction set? Instruction set should be Complete. (iv) A facility for subroutines calls and returns. by pre-fetching the next micro-instruction. 35. 32. 31. What is pipelining? The technique of overlapping the execution of successive instruction for substantial improvement in performance is called pipelining. Define stalls. (iii) Conditional branch dependit1g on status bits in registers of computer. When does a structural hazard occur? A structural hazard is a situation when two instruction require the use of a given hardware resource at the same time. while the current one being executed. The Decode unit is idle in cycle 3 through 5. 33. A data hazard is any condition in which either the source or destination operands of an instruction are not available at the same time expected in the pipeline. such idle period are called stalls. The most common case in which this hazard may arise is in access to the memory unit. pre-fetching may get the incorrect instruction. Define structural hazard. 38. Regular and Compatible. . 34. 36. What are the address-sequencing capabilities required in a control memory: (i) Incrementing of the control address register. Efficient. Hazard that may be encountered in pipelined operation is known as a structural hazard.30. More compllex hardware required to correct for such cases. the execute unit is idle in cycle 4 through 6 and the write unit is idle in cycle 5 through 7. Define data hazard. OR Pipeline is a technique of decomposing a sequential process into sub-processes with each subprocess being executed in a special dedicated segment that operates concurrently with all other segments 37 Faster operations can be achieved. (ii) Unconditional branch as specified by address field of the microinstruction. What is a branch penalty? The time lost as a result of a branch instruction is called as branch penalty. What are the complexities involved in pre-fetching microinstructions? Whenever status flags need to be checked to determine the next address of the microinstruction.
40. only the microprogram of the control unit has to be modified. the existing control unit cannot be used and a new control unit should be defined from the scratch. Micro programmed Control Unit Merit : Speed will be less Demerits: If some instructions are added to the instruction set. What is Pipelining? Pipeline is a technique of decomposing a sequential process into sub-processes with each sub-process being executed in a special dedicated segment that operates concurrently with all other segments. Hardwired Control Unit Merit : Speed will be more Demerits: If some instructions are added to the instruction set.39.Discuss the relative merits and demerits of a hardwired control unit and a microprogrammed control unit. .
Write short notes on READ. 6. Secondary memory stores programs and data. Number of words Unit of transfer: Word. Random. What is known as secondary memory? Secondary memory is much larger in capacity but also much slower than main memory. The storage capacity of a cache is less than main memory. Magnetic surface Physical characteristics Organization: Volatile/ Non-volatile Organization: Erasable / Non-erasable 2. What are the characteristics of memory system? Location: CPU. Name the two types of RAM SRAM and DRAM 7. Associative Performance: Access time. the R/W line is made HIGH. Mention the types of memory? The information storage components of a computer can be placed in four memory groups. Internal (main). which enables output buffer and disables input buffer. WRITE and REFRESH operation in DRAM? ' WRITE: To enable write R/W line is made LOW. ROW line and REFRESH line are made HIGH. They are: Register Cache (level-1) Cache (level-2) Main memory and Secondary Memory 4. REFRESH: To enable refresh operation R/W line. Cycle time. What is meant by cache? Cache is positioned logically between the CPU registers and Main memory.UNIT 4 1. 5. Block Access method: Sequential. Transfer rate Physical type: Semiconductor. 8. but speed of the cache is faster than main memory. What is the use of a Main Memory? The main memory is used to store the programs and data inactive use. External(Secondary) Capacity: Word size. . which enables input buffer and disables output buffer. READ : To read data from the cell. Name the physical characteristics of memory Volatile and Non-volatile 3. Its location is addressed directly by the CPU's LOAD and STORE instruction. Direct.
PROM. the information stored is permanent.9.No 1 2 3 4 Static RAM Less memory cell per unit area Access time is very low and hence it is faster It consists of number flip-flops. • They are used for implementing memories. but it is not possible to write an entire block of cells. What is ROM. Compare between SRAM and DRAM S. PROM (Programmable ROM): The PROMs are one time programmable. For example it is the time between two successive read operation. 14. These modules are implemented in two types: flash cards and flash drives. EPROM (Erasable PROM): Here. 13. EEPROM (Electrically EPROM): EEPROM allows selective erasing at the register level rather than erasing all the information since the information can be changed by using electrical signals. Define memory access time(access time)? The time required to access one word is called the memory access time (or) it is the time that elapses between the initiation of an operation and the completion of that operation. It is a permanent storage. . The flash memories are available in modules. 10. In flash memories it is possible to read the contents of a single cell. Each flip flop is used to store one bit. • Their cycle time range from 100 ns to less than 10 ns. one erase the stored data in the EPROMs by exposing the chip to ultraviolet light through its quartz window for 15 to 20 minutes. What are the characteristics of semiconductor RAM memories? • They are available in a wide range of speeds. 12. Once programmed.EPROM and EEPROM? ROM: It is Read only memory. . Define memory cycle time? It is the minimum time delay required between the initiations of two successive memory locations. Write short note on flash memory? Flash memories are read /write memories. The EEPROM memory also has a special chip erase mode by which entire chip can be erased in 10 ms. Cost is less 5 Cost is more 11. Extra hardware is required to control refreshing. A flash cell is based on a single transistor controlled by trapped charge. Refreshing is not required Dynamic RAM More memory cell per unit area Access time is higher than static RAM It stores charge on a capacitor Refreshing is required to maintain the charge on the capacitors after every few milliseconds. • They replaced the expensive magnetic core memories.
It enables cache controller to get a block of memory instead of getting just a single address. but this number is small compared to the total number of blocks in the main memory. What is cache memory and hit rate? Cache memory is a small section of SRAM is added along with main memory. What is program locality and locality of reference and mention its types? The prediction of next memory address from the current memory address is known as program locality. 4 They have lower power consumption and hence suitable for battery driven applications 5 They are available in smaller storage capacity. This is referred to as locality of reference. 20.15. Block size. Mapping function. What is use of cache controller? It is used to implement the cache logic. Memory latency and Bandwidth. 16. 3 They have shorter seek and access times which results in faster response. Differentiate flash drives and hard disk drives S. What is SIMM and DIMM? The main memory (DRAM) is implemented using large memory modules known as SIMMs (Single In-Line Memory Modules) and DIMMs (Dual-In-Line Memory Modules): These modules are an assembly of several memory chips on a separate small board that plugs vertically into a single socket on the motherboard. How the performance of the memory can be measured? The performance of the memory can be measured using two typical Performance parameters namely. 6 Higher cost per bit. 19. 14. What are the elements needed for the cache design? The elements needed for the cache design are Cache size. Storage capacity is larger Lower cost per bit.No Flash Drives 1 These are solid state electronic devices 2 They don't have movable parts and hence insensitive to vibration. What is mapping function and its types? The cache memory can store a reasonable number of blocks at any given time. The percentage of accesses where the processor finds the code or data word it needs in the cache memory is called the hit rate. They have comparatively larger seek and access times They have comparatively large power consumption. Write policy. 18. The correspondence between the main memory blocks and those in the cache is specified by a mapping function. 17. and Number of Caches 15. 7 Deterioration rate is high Hard Drives These are magnetic devices They have moveable parts. The hit rate is normally greater than 90 percent. Replacement algorithm. . They are sensible to vibrations. Deterioration rate is low. Many instructions in localized area of the program are executed repeatedly during some time period. and the remainder of the program is accessed relatively infrequently.
page fault and demand paging? If the page required by the processor is not in the main memory. The choice of replacement of the existing block should be such that the probability of accessing same block must be very less. Hardware transparency. two different sets of data become associated with the same address. Associative-mapping technique and Set associative mapping technique. The various approaches are Least-Recently Used (LRU) First-in-First-out (FIFO) Least-Frequently-Used (LFU) Random 19. another bus master can take over control of the system bus. What is TLB? TLB (Translation Look aside Buffer) is use to store the most recently used page table entries in an on-chip cache. one in cache and one in main memory. It translates virtual address into physical addresses. What is segment translation and page translation? Segment translation is a process of converting logical address into a linear address. Techniques that automatically swaps program and data blocks between main memory and secondary storage device are called virtual memory. two copies of same data can exist at time. by a new block. The memory management unit controls this virtual memory system. the data in the cache no longer match those held in main memory creating inconsistency. This bus master could write data into a main memory blocks which are already held in the cache of another processor. 22. 21. Non-cacheable memory and Cache flushing. It transforms a linear address generated by segment translation into a physical address. the page fault occurs and the required page is loaded into main memory from the secondary storage memory by special routine called page routine. If one copy is altered and other is not. Page translation is the second phase of address translation. The types of the cache updating are: Write Through System. The different approaches to prevent data inconsistency are Bus watching (snooping). 16. What is cache coherency and name the different approaches to prevent data inconsistency? In multiprocessor systems. . 18. 20. What is virtual memory and MMU? The operating system moves program and data automatically between the main memory and secondary storage. What is memory interleaving? The main memory is divided into a number of memory modules and the addresses are arranged such that the successive words in the address space are placed in different modules.There are three types of mapping techniques. The replacement algorithms do the task of selecting the existing block which must be replaced. What is cache updating and name the types? In a cache system. 23. What is address translation page fault routine. Buffered Write Through System and Write-Back System 17. one of the existing blocks must be replaced. They are: Direct-mapping technique. When this happens. What is replacement algorithms and name the various approaches? When a new block is brought into the cache.
In memories where information rotates around a closed track is called the rotational latency. 28. This time depends on the initial position of the head relative to the track specified in the address. MBR/MDR (Memory Buffer/Data Register) 31. Define seek time? The time required to move the read write had to the proper track is called seek time.4. The WORM storage provides one-time writing but unlimited reading of data.2Thus if the word length of the machine is 32 bits. 29.8with each word consisting of 4 bytes. This hit and miss ratio is used to measure the performance of cache. 25. otherwise miss. The average time for this movement to take place is the latency of the memory. 30. What are the two registers involved in data transfer between the memory and the processor? The registers used to transfer data are MAR (Memory Address Register). Define rotational latency? The time is consumed for the cell to reach the read write head for the data transfer to begin. What do you understand by hit ratio? Hit ratio is a concept defined for any two adjacent level of a memory hierarchy. a single large file is stored in several separate disk units by breaking the flip up into a number of smaller pieces and storing these pieces on different disks. This system is referred to as RAID (Redundant Arrays of Inexpensive Disks) In a RAID system. 32. LATENCY TIME: The rotational delay also known as latency time is the amount of time that elapses after the head is positioned over the correct track until the starting position of the addressed section passes under the read / write head. This is called byte addressable memory. This is called data striping. the write-once read-many (WORM) CD is used. . What are its types? During the course of execution of a program memory references by the processor for both the instruction and the data tends to cluster. arrays of inexpensive disks operate independently and in parallel to improve the speed of data transfer. and (ii) Temporal Locality. The average seek time is in the range of 5 . There are two types: (i) Spatial Locality. Byte locations have addresses 0.24. Data cannot be overwritten or erased but can be updating by writing new information into a file at another location on the disk 27.8 ms. When an information is found in cache we call it as a hit. 26 Write short notes on WORM? One or a small number of copies of a set of data is needed. successive words are located at addresses 0. What is RAID and data striping? In a multiple disk system.1. Define locality of reference. Define byte addressable memory. What is seek time and latency time? SEEK TIME: The seek time is the time required to move the read / write head to the proper track.
37. What are the factors of the long access time? • The read write head positioning time. • The fact that data transfer to and from the memory is serial rather than parallel. What are called as the destructive read out and non destructive read out? In some memories. 40. What is Virtual Address? The binary address that the processor used for either instruction or data called as virtual address. What is virtual memory? Techniques that automatically move program and data blocks into the physical main memory when they are required for execution are called as virtual memory. This type of memory is accessed simultaneously and in parallel on the basis of data content rather than by specific address or location. 34. 38. What is virtual page number? Each virtual address generated by the processor whether it is for an instruction fetch is interpreted as a virtual page.33. What is a hit & hit rate? A successful access to data in cache memory is called hit & the number of hits stated as a fraction of all attempted access. Define content addressable memory (CAM)? A memory unit accessed by content is called content addressable memory (CAM). • Write . 41. . What are the two ways in which the system using cache can proceed for a write operation? • Write through protocol technique. the part of a track within a sector stores a fixed amount of information corresponding to the memory units block size. • The address is then processed by the decoder which selects the required location in the storage cell unit. this phenomenon is called DRO. • The relatively slow speed at which.back or copy back protocol technique. 35. What is called as sector? The recording surface is divided into sectors so that. reading does not affect the stored data are called NDRO. 42. 36. 39. Memories in which. the track move. Explain how the RAM operates? RAM operates as follows: • First address of the target location to be accessed is transferred via the address bus to the RAM's address buffer. the method of reading the memory destroys the stored information.
47. and tA2 = 10-3 sec. M2) has the access times tAl = 10-8 sec. Define memory interleaving. being able only to perform primitive I/O operations. In order to carry out two or more simultaneous accesses to memory. In many computers the Cache block size is in the range of 32 to 128 bytes. Smaller size would mean more misses. thus reducing the total execution time of the program. How Cache memory is used in reducing the execution time? If the active portions of the program and data are placed in a fast small memory.because only 1 edge will be seen by the processor (if the two interrupts occur in quick succession i. the average memory access time can be reduced. In some computers. Such terminals are sometimes called dumb terminals. A two level memory (Ml.Define dumb terminal. .43. What happens if two independent devices are connected to this line? The request from 1 device may be masked by the other . the processor responds only to leading edge of the interrupt-request signal on one of its interrupt-request lines. 45. 44. What would be the main advantages and disadvantages of making the size of Cache blocks larger or smaller? Larger size cache would imply fewer misses if most of the data in the block are actually used. Early CRT terminals were relatively simple in their functional capability. What must the hit ratio H be in order for the access efficiency to be at least 65% of its maximum possible value? Hit Ratio H = 0. the memory must be partitioned into separate modules.65x10 −8 − 10 −3 10 −8 + 10 −3 46. and wasteful if much of the data are not used before the cache block is ejected from the cache. The advantage of a modular memory is that it allows the interleaving ie consecutive addresses are assigned to different memory module. 48.e. Such a fast small memory is referred to as a cache memory. before the first interrupt has powered its line).
3. What is the various mechanisms for implementing I/O operation? • Program controlled I/O • Interrupts • DMA 7. When the privilege exception arises? An attempt to execute a privileged instruction while in the user mode leads to a special type of interrupt called a privilege exception. S. the processor repeatedly checks a status flag to achieve the required synchronization between the processor and an input and output device. • Each devices has different methods of operations. Why Input/Output devices cannot be connected directly to the System Bus? • The data transfer rate of the Input/Output devices is often slower than. 2. What is Program controlled I/O? In program controlled I/O. . 5. What are the 2 independent mechanisms for controlling interrupt request? • At the device end. then the arrangement is called memory mapped I/O. • It has different data formats and word length than that of CPU. Two types of Interfacing Techniques are • Memory mapped Input/Output • Input/Output Mapped Input/Output. either an interrupt enable bit in the priority structure determines whether a given interrupt request will be accepted. 3 Memory control signals are used to I/O control signals are used to control control read and write units I/O operations real/write unit I/O operations 4. Give the comparison between memory mapped I/O and I/O mapped I/O. 2 Processor provides more address lines for Processor provides less address lines for accessing memory. What is memory mapped I/O? When the I/O devices share the same address space. an interrupt enable bit in a control register determines whether the device is allowed to generate an interrupt requires.No Memory mapped I/O I/O Mapped I/O 1 Memory and Input/Output share the Processor provides separate address range address range of address range of of address range for memory and I/O devices processor. that of memory or CPU. Explain Input/Output Interfacing Techniques.UNIT -V 1. • At the processor end. 8. accessing Input/Output. 6.
What is PCI interrupts? Each PCI device has its own interrupt line or lines to an interrupt controller. List down the arbitration schemes used in centralized bus arbitration approach. Bring out the merits and demerits of Daisy chaining method. Demerits: • The propagation delay of bus grant signal is proportional to the number of masters in the system. optical fibers and wireless links 3 It support parallel data transmission It support serial data transmission 4 Cost is high Cost is less 10.No Intra System Communication Inter System Communication 1 Which occur within a single computer Which can involve communication over much system and involves information transfer longer distances over lesser distances 2 Implemented by groups of electrical wires Implemented by a variety of physical media called buses like electrical cable. Merits: • It is simple and cheaper method.9. • Failure of any one master causes the whole system to fail. (ii) Multi level interrupts. What is interrupt and be interrupt service routine. What is cycle stealing? The processor originates most memory access cycle and the DMA controller can be said to cycle steal memory cycles from the processor. Then the processor can immediately start executing the corresponding ISR. • Daisy chaining. 13. • It requests the least number of lines and this number is independent of the number of masters in the system. The schemes based on this approach are called vectored interrupts. 12. 14. 15. The interrupt pins are provided for PCI devices that must generate request for service. Give the classification of interrupts. What are vectored interrupts? To reduce the time involved in the polling process a device requesting an interrupt may identify itself directly to the processor. • Polling method • Independent Request. This makes arbitration time slow and hence limits the number of masters in the system. • The priority of the master is fixed by its physical location. The event that causes the interruption is called interrupt and the routine executed to service the interrupt is called interrupt service routine. How do you differentiate the inter and intra system communication? S. This technique is known as cycle stealing. . 16. (i) Single level interrupts. 11.
hardware and control signal requirements parallel ports are classified as input port and output port. A typical keyboard consists of mechanical switches that are normally open. What is DMA and DMA controller. Explain input port with an example. Explain Parallel Port. 19. signal after and encoder circuit generates ASCII code for the corresponding key. Parallel port is used to send or receive data having group of bits (8 bits or 16 bit) simultaneously. 25. In synchronous bus. Explain vectored interrupt. 23. The external device which controls the data transfer is known as DMA controller. If the internal control circuit of the processor produces a CALL to a predetermined memory location which is the starting address of ISR. Explain Maskable interrupt. 20. 24. 21.Single level interrupts . 22. DMA . I. arbitration is fast and is independent of the number of master in the system. . Hence this technique is referred as Direct Memory Access (DMA).Multi level interrupts 2. According to the use. Explain Synchronous Bus and asynchronous Bus. It allow peripheral device to access directly memory. Software interrupts. Hardware interrupt . then that address is called vector address and such interrupts are called vector interrupts. Advantage: Due to separate pain of bus request and bus grant signals. When masked. List the different types of interrupts. In this technique external device is used to control data transfer which generates address and control signals required to control data transfer.17. Processor has to execute interrupt service routine for servicing that interrupt. Commonly used input device is a keyboard. When key is pressed corresponding. Input ports are used to receive the data. 18. . What are the advantages of polling method? • The priority can be changed by altering the polling sequence stored in the controller. In the processor those interrupts which can be masked under software control are called maskable interrupts. Maskable interrupts are enabled and disabled under program control by setting or resetting the particular flipflops in the processor. all devices derive timing information from a common clock signal. What is the advantage and disadvantage of independent request bus arbitration method. In asynchronous bus. • If one module fails entire system does not fail.Direct Memory Access. processor does not respond to the interrupt even though the interrupt is inactive. the common clock is eliminated and data transfer on the system bus in achieved by the use of a hand shake between the processor and the device being addressed. When the external device interrupts the processor. Disadvantages: It requires more bus request and grant signals.
Hence single port ran be programmed to use for input the data or output the data. 35. DMA stands for Direct Memory Access. 27. What is the necessity of an interface? Any device that has to be connected to a CPU requires an interface. What is DMA operation? State its advantages. 30. Such a port is known as programmable parallel port. 31.) One bit at a time. This mode of operation is called superscalar execution. There are: • Distributed Memory ( loosely coupled) • Shared memory (tightly coupled). A shift register is used to transform information between the parallel and serial formats. this technique is used. 34. With such an arrangement it is possible to start the execution of several instruction in every clock cycle. Commonly used output device is printer. data and electrical characteristics between the CPU to the device. which takes care of the mismatch in speed. Explain programmable parallel port. multiple functional units are used to create parallel paths through which different instructions can be executed in parallel so it is possible to start the execution of several instructions in every clock cycle. 29. 32. This mode of operation is called superscalar execution. 33. How are multiprocessors classified based on their memory organization? Multiprocessors are classified by the organization of their memory systems. Explain output port with an example. This means that multiple functional units are used. The input and output interfaces can be combined into a single interface and the direction of data flow can be controlled by data direction register. What is meant by super scalar processor? Super scalar processors are designed to exploit more instruction level parallelism in user programs. In order to transfer large amount of data between memory and I/O device without involvement of CPU. 28. A serial port is used to transmit/receive data serially. A key feature of an interface circuit for a serial port is that it is capable of communicating in a bit serial fashion on the device side and in a bit parallel fashion on the processor side. The processors with more complex instructions are called as Complex Instruction Set Computers (CISC). (i. What is RISC and CISC? The processors with simple instructions are called as Reduced Instruction Set Computers (RISC). The output ports are used to send the data to the output device. What is superscalar execution? In this type of execution. What is meant by multiprocessors? The system contains two or more CPUs and can execute instructions independently then the system is called multiprocessor system.e. The output port contains a data register and status flux.26. The advantage is fast data transfer. . Explain serial port.
The instruction executed on a speculative basis should be one that is likely to be the correct choice most often. Define Availability in fault tolerance? Availability is defined as the probability that a system is operational at a given point in time. Distinguish the reliability and availability: Reliability characterizes the ability of a system to perform its service correctly when asked to do so. but only on a speculative basis. If a branch does not take place. Alternatively. What is Vector Processor? A vector computer or vector processor is a machine designed to efficiently handle arithmetic operations on elements of arrays. 41. each CPUs has independent cache. Such machines are especially useful in high performance scientific computing. What is the role of the operating system in the computer? The role of the operating system is: • Allocate resources to programs and users • Control and execution of user program • Reads commands from the user. The instruction in this slot is always executed. but the event is never occurs. where matrix and vector arithmetic are quite common. with an instruction from the body of the loop moved to the delay slot if possible. 37. Define deadlock? Process is waiting for an event such as the release of a shared resource. Suggest a way to implement program loops efficiently on this computer. What is an operating system? An operating system is a program which acts as an interface between a user of a computer and computer hardware. A computer has one delay slot. 42. 38. the possibility exists for two or more cache contain different version of the same information at the same time. called vectors. a copy of the first instruction in the loop body can be placed in the delay slot and the branch address changed to that of the second instruction in the loop. Define fault tolerance? It is defined as the ability of a system to execute specified algorithms correctly regardless of these failures. 44. the results of that instruction are discarded. Availability means that the system is available to perform this service when it is asked to do so. verigy their accuracy and execute the command given by the user. What is meant by cache coherence problem in multiprocessors? In multiprocessor. . 39. the conditional branch should be placed at the end of the loop. this known as deadlock. this is known as cache coherence problem. 40. 43.36. Thus. The Cray Y-MP and the Convex C3880 are two examples of vector processors used today.
Microprogrammed control technique is used. and hence faster.No RISC 1 Number of instructions. addressing modes. microprogram sequencer. then the CPU structured in this manner is called a bit sliced processor. Discuss the Flynn's classification of computers. 3 Instructions need one clock cycle for execution. R = ∏R i =1 n i Parallel System: R = 1 - ∏ (1 − R ) i i =1 n 49.What is meant by reliability? How is it defined for a series and parallel system? Reliability : It is defined as the probability of a unit or system surviving (functioning correctly) for a period of time t. 48. Fixed field decoders can be used.45. 46. Single Instruction Stream Single Data Stream (SISD) Single Instruction Stream Multiple Data Stream (SIMD) Multiple Instruction Stream Single Data Stream (MISD) Multiple Instruction Stream Multiple Data Stream (MIMD) 47. addressing modes. Instructions need more than one clock cycle for Execution.What is meant by bit sliced processor? If CPU is constructed with IC components such as processor unit. . Serial System : Reliability is a product of the component reliabilities. and control memory. CISC Number of instructions. 2 Hardwire control technique is used. instruction formats will be less. RISC processors typically have all instructions of equal size. instruction formats will be less. What is the advantage of such a choice? This makes the decoding easier. S. Distinguish between RISC and CISC machines.
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