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A Study on Microstructure and Reliability Tests of Low Cost Flip Chip

Jian Cai1*, Annette Teng1, Philip C. H. Chan2, Simon P. C. Law2, Guowei Xiao2
Computer Aided Design & Manufacturing Facility
Department of Electrical and Electronic Engineering
Hong Kong University of Science and Technology
Hong Kong SAR, China


Electroless nickel plating followed by stencil printing is an attractive process because of its cost savings over the
conventional high lead C4 process. The development of the process for reliability of this low cost bumping process at HKUST
is discussed in this paper. The focus of the study is on the solder and the under bump metallurgy (UBM) microstructure as well
as the reliability test results of flip chip on board (FCOB). Electrical resistance and shear strength were measured to monitor
the reliability of the bumped chips under various thermal environments. Multiple reflows and high temperature aging at 150ºC
were performed for bumped dice. The results showed that the shear force would increase with thermal exposure and reach a
peak value during the third reflow, subsequent reflows revealed that the shear force would decrease but is still maintained. SEM
and EDS results of the fracture surface indicated that the fracture was cohesive or inside the solder. The microstructure of
solder bump was observed by cross section and SEM to consist of several layers. A layer of Ni 3P at the solder/nickel interface
indicated that recrystallization of amorphous Ni-P occurred. Lead rich layer and Ni-Sn intermetallic compounds (IMC) were
detected. This layer of lead rich solder created a decrease in the strength of the solder bumps. Additionally, bonded FCOB
samples with and without underfill were subjected to Condition B temperature cycling test. The underfilled units passed 1000
cycles whereas the units without underfill failed after only 110 cycles. Cross-section showed various modes of cracking on the
solder joints including at the UBM.

Introduction The UBM system is important to the structure

with its functions summarized as:
Advanced electronic packaging technology 1) To promote the adhesion between bonding
has evolved rapidly in the past 20 years (1) from large pad and the solder bump.
pitch dual-in-line packages to fine pitch area array 2) To act as a diffusion barrier layer between the
packages. Today’s packaging technology must satisfy solder bump and the Al pads caused by
the requirements of modern electronic products, which diffusion resulting in the formation of brittle
demand lighter weight, thinner profile, shorter intermetallic phases or Kirkendall voids.
connection, and smaller volume. These requirements 3) To provide a wettable and solderable layer for
have allowed flip chip to recently become a very the solder bump.
attractive packaging technology since its introduction Currently, there are many different UBM
by IBM in 1960’s (2). With the chip facing down and structures developed by various companies and
using solder bumps to replace the traditional wire institutes for their applications (2,3,4). For C4 high
bonding, flip chip offers many advantages and has a lead solder alloy, Cr-CrCu-Cu is the UBM used
huge market potential. whereas for eutectic solder, NiV/Au, TiW/Cu, or
A sketch of flip chip technology is shown in electroless Ni/Au are used.
Fig.1. The structure of flip chip involves I/O pads, Electroless nickel/stencil printing is low cost
passivation layer, under bump metallurgy (UBM) and because this process bypasses the high cost process of
solder bumps. UBM sputtering and photolithography using thick
photoresist. Examples of companies using this
Passivation Solder technology are PacTech of Germany, IC Interconnect
UBM Chip bump and Flip Chip Technologies of USA. High bumping
yields of 100% are not uncommon(5). More and more
Underfill licenses are sold for this technology validating its
Substrate (FR-4, Flex) importance in the industry. This technique can
potentially drive wafer-bumping cost down to below
Fig. 1 Sketch of flip chip on substrate

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US$70/wafer. It is therefore of interest to develop this from this seed of nickel. The actual chemical reactions
electroless nickel/stencil printing technique in-house. in electroless Ni plating are discussed in reference
(7,8). A thin layer of Au was deposited on the nickel
Experimental stud by immersion for oxidation protection.
Type 5 and 6 solder pastes from different
Wafers were prepared for the electroless vendors were printed by a DEK 260 printer, with an
nickel/ gold immersion UBM. The details of the electroformed 75m thick nickel stencil. Reflow
process flow have been previously published by the process was processed in a programmable desktop
same and other authors (6,7). oven with the typical eutectic solder reflow profile,
Test chips were designed as daisy chain characterized by a peak temperature of 220C. For
structures, as shown in Fig. 2. Al film was sputtered lead free pastes, a peak temperature of 250C was used.
on 4-inch wafers and patterned by standard The flux residue was then removed by rinsing wafers
semiconductor photolithography process. It was in 50oC water leaving shiny solder bump surfaces.
necessary to remove native oxide and form a nuclear This paper will focus on the eutectic solder bumps.
seed layer to initiate the electroless nickel deposition. The shear strength of solder bump was
The quality of this nucleation process strongly measured by a Dage 4000 Multipurpose tester with a
determines the morphology of nickel studs and their shear tool tip with 75m face width. Bumped test
mechanical and electrical properties. The metallized chips were exposed to multiple reflows and high
and passivated wafers were exposed to a double temperature storage prior to shear force testing. A
zincation treatment before electroless nickel plating. Research Device Automation M-8A Flip Chip Aligner
The zincation solution was prepared in-house. Bonder was used to align the bumped dies onto the
After zincation, a monolayer of zinc nuclei FR-4 substrates. A water-soluble flux from was
exists on the Al pads. During electroless nickel-plating, applied onto the chip prior to alignment. The aligned
this layer of zinc would be replaced by Ni growing chip on board was reflowed in a the programmable
desktop oven. The electrical integrity of the daisy
chained FCOB was checked for open or short. A
Feinfocus X-ray machine was used to check for
bonding defects and to screen out defects such as
bridging or excessive voiding.
The dispensing of the underfill was done in a
Camalot 1414 machine using Hysol FP4526 underfill.
C-SAM using a Sonix system was used to evaluate the
(b) integrity of the underfill process after curing. The
FCOB samples were placed in Blue M ETC-04
thermal cycle chamber set to Condition G (JESD22-
A104-B). Cross-sections, SEM and EDS were
(a) One of test chips on wafer performed to analyze the microstructure. For IMC
observation, the sample was etched by a nitric-based
Al pad on chip acid for a few of seconds.

Results and Analysis

Al connection covered
by passivation (1) Microstructure of solder bumps

Fig. 3 shows SEM pictures of a solder ball

that has been cross-sectioned. Different compositions
are detected near the solder/Ni interface by EDS. The
lead rich layer is adjacent to the IMC layer, having a
distance of approximately 10µm from the interface. As
(b) Detail at the corner of test chip
eutectic Pb-Sn solder alloy has relatively higher
Fig. 2 Daisy chain design of test chip strength (9) compared to the lead rich layer, this

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created a weaker layer near the IMC where yielding amorphous Ni-P occurred during reflow. Some
and fracture occurred during shear testing. researchers have indicated that this crystallization can
EDS indicates that the IMC composition is only occur at annealing temperatures above 400ºC (10).
Ni3Sn4. The Ni3Sn4 needles could be observed in Fig. 3 It can be speculated that it is the formation and growth
(right). Between Ni-P and IMC layer, there is a thin of the Ni-Sn intermetallic that caused the Ni-P to form.
dark layer. EDS analysis of this layer indicates that it The surfaces of the solder ball after multiple
is Phosphorous-rich and matches the composition of reflows are shown in Fig. 4. Reflow affected the grain
Ni3P. It can be speculated that the crystallization of the size of the solder bump. The as-reflowed solder ball

Eutectic Pb-Sn

Eutectic Pb-Sn

Lead rich layer

Chip Ni3P

Fig. 3 SEM of solder bumps (Slightly etched on the right)

Fig. 4 Surface of solder bumps (Left: as-reflowed, Right: after 3 reflows at same mag.)
Shear Force after Multi-reflows
Shear Force After Thermal Aging
70 70

60 60
S hea r Force (gra ms/bump)
shear streng h (g ram/bu mp )

50 50

40 40

30 30

20 20

10 10

0 0
1 2 3 4 5 6 7 8 9 10 0 200 400 600 800 1000 1200
times of reflow Aging Time (hrs)

Fig. 5 Shear force results of solder bumps

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has coarser grains whereas the grain size after 3 surface A of eutectic solder would yield completely to
reflows becomes finer. Coarser grain structure is the lead rich surface B as shown in Fig. 6(b). The
associated with lower strength in metals. So fracture height of fracture surface is still at 15µm, which
induced by shear test occurred inside the solder rather coincides with the height of the lead rich layer. As the
than at the interface where the adhesion is much number of reflow is increased, the microstructure of
higher for as-reflowed solder bumps. The finer grains solder would coarsen further enhancing the
due to the recrystallization of solder alloy result in aggregation of lead near the lead rich layer, thus
higher strength temporarily. Further exposures to lowering the shear force. Ni3Sn4 and Ni3P phases
reflow profile caused the grain size to start coarsening. could be found at the edge of the fracture bumps (Fig.
This is reflected by a peak shear force at the third 6(b)). This indicates that the crack initiated at the
reflow, as shown in Fig. 5. The recrystallized grains interface of the Ni3P and the Ni-Sn IMC and then
start to coarsen with subsequent reflow steps. After 10 propagated into the solder along the lead rich layer.
reflows, abnormal coarsening of Pb-Sn solder and
aggregation of Pb/Sn individually was observed (6).

(2) Shear force test of Ni studs and solder bumps

Normally, the electroless plated Ni stud is
5~6µm in thickness, however 15µm Ni studs were
specially prepared for shear testing. An average shear B
strength of 230MPa was measured, which satisfied the
requirement for electronic packaging applications (6).
For the high temperature storage, bumped
chips were placed in oven at 150C up to 1000 hours (a)
according to JEDEC standard (JESD22-A103-A).
After thermal preconditions, solder bumps were sent
for shear force test. The stencil printed eutectic solder
bump after reflow had a height of 120µm and a
diameter of 160µm. During shear testing, the height of
the shear tool was set at 30µm. The results are shown
in Fig. 5. For the thermally aged samples, a peak Ni3P
value was found similar to that in the reflow
experiment. The shear force would increase slightly
during the first 200 hours of aging and then decreased
somewhat but is still maintained at 56-58 grams per
bump until 1000 hours. This variation of shear force (b)
has been reported by others (11) and is attributed to
the grain size changes of the lead and tin binary phases
inside the solder bump (6).
Various fracture surfaces and features were
characterized using SEM and categorized in Fig. 6.
For as-reflowed solder bump, the fracture failure
occurs inside the bulk solder. There are two fracture
surfaces as indicated by A and B, as shown in the Fig.
6(a). The height is about 30µm for A and 15µm for B
from the chip surface. EDS analysis revealed that the
higher surface A is eutectic Pb-Sn in composition
whereas B is lead rich in composition. Ni-Sn (c)
intermetallic was not exposed on the surface. After 3
reflows, the strength of solder alloy would improve Fig. 6 Fracture surface after multiple reflows
due to the recrystallization of solder alloy. The higher (a) As-reflowed, (b) 3 reflows, (c) 10 reflows

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After 10 reflows, the 30m high plateau appeared and recorded by a HP Data Logger. As shown in Fig.
again but with a lead rich composition. This implies 7, FCOB samples with underfill passed 1000 cycles
that the cracks initiated at the lead rich layer due to the whereas those without underfill failed after 110 cycles.
intensive aggregation of lead caused by the formation Failed samples were cross-sectioned after thermal
and growth of Ni3Sn4. The height of this fracture cycling and observed by SEM to reveal various
surface is about 30µm, which is the height of the shear failures modes.
tool. Fig. 8 shows the solder joint microstructure
of the cross sections after thermal cycling. For the
(3) Reliability Tests samples with underfill, the microstructure of the solder
joints coarsened during thermal cycling but this
As is well documented, underfilling is one of coarsening did not affect the reliability up to 1000
the most important steps for the reliability of FCOB or cycles. The growth of Ni-Sn IMC is negligible during
FCIP (flip chip in packaging) (1,2). The underfill the 1000 Condition G thermal cycle, which has a
material will reduce the effect of the CTE mismatch maximum temperature of 125oC. Needle shaped Ni-Sn
between chip and substrate, and direct localized IMC grains were observed to cluster together at the
stresses away from the solder bump joints. interface but did not grow in thickness.
Referring to JEDEC standard JSED22-A104- Samples without underfill experienced high
B, a thermal cycling profile was selected for reliability thermal stresses during thermal cycling and failed
test. The condition is –40C~+125C at the rate of one early on. Three failure modes were observed and can
cycle per hour. Electrical resistance was selected as be characterized as crack near chip side, crack near
the criterion for evaluation. FCOB samples with and PCB side and delamination of Al and UBM layer. The
without underfill were both placed into the cycling former two modes are both due to the relative low
chamber and the electrical resistance was measured strength of the solder joints. The latter mode from Al-

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Samples without underfilling
Contact electrical resistance (ohms)

Samples with underfilling

Contact electrical resistance (ohms)

102 109
104 110
4 4
3 3

2 2

1 1

0 0
0 20 40 60 80 100 120 140 0 200 400 600 800 1000
Number of Cycles
Numble of cycles

Fig. 7 Electrical resistance of FCOB during thermal cycling


Crack near
chip side Coarsened solder
Crack near
PCB side

Fig. 8 Cross-sections after thermal cycling

Left: without underfill, 110 cycles, (underfill in picture was filled for cross-
sectioning); Right: with underfill, 1011 cycles

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UBM delamination could have been due to poor Al 2. John H. Lau, low Cost Flip Chip Technologies,
sputtering and Ni plating process (12). McGraw-Hill, New York, NY, 2000.
There are many interesting papers on the 3. Deborah S. Patterson, A Comparison of Popular Flip
growth of IMC between solder alloy and the UBM and Chip Bumping Technologies,
4. Glenn A. Rinne, Solder Bumping Methods for Flip Chip
its effect on reliability (13,14,15,16). For copper based packaging, 1997 ECTC, 240-247.
UBMs, high IMC growth rates may cause voiding and 5. Andrew J. G. Strandjord, Scott F. Popelar, Curt A.
sites for crack initiation. Additionally, brittle Cu-Sn Erickson, Low Cost Wafer Bumping Process for Flip
phases can affect strength (16). However, for non- Chip Applications(Electroless Nickel-Gold/Stencil
copper UBM systems such as shown here, the slower Printing), IMAPS 1999.
growth rate will reduce the rate of void formation and 6. Jian Cai, Simon Law, Annette Teng, Philip C. H. Chan,
extend solder joint lifetime for filled FCOB. Inferences of pad shape and solder microstructure on
shear force of low cost flip chip bumps, Proceedings of
Conclusion International Symposium on Electronic Materials and
Packaging, Nov 30 ~ Dec 2, 2000, Hong Kong, 91-98
7. Szu-Wei Lu, Ruoh-Huey Uang, Kuo-Chuan Chen, Hsu-
A low cost flip chip bumping process based Tien Hu, Ling-chen Kung and Hsin-Chien Huang, Fine
on electroless Ni/stencil printing was developed in Pitch Low-Cost Bumping for Flip Chip Technology,
HKUST. Microstructural characterization of the solder 1999 IEEE/CPMT-EMPT Symposium, 127-130.
bumps by SEM and EDS shows crystallization of the 8. Glenn O. Mallory, Juan B. Hajdu, Electroless plating:
amorphous Ni-P UBM. This lead rich layer is the fundamentals and applications, Orlando, Fla., c1990.
weakest link and is often the fracture surface exposed 9. Guruswamy, Sivaraman, Engineering properties and
during shear testing. applications of lead alloys, New York : Marcel Dekker,
The shear force of the solder bump changed 2000
10. C. Y. Liu, K. N. Tu, T. T. Sheng, C. H. Tung, D. R.
with the recrystallization and coarsening of the solder
Frear, and P. Elenius, Electron microscopy study of
alloy grain size during multiple reflows and thermal interfacial reaction between eutectic SnPb and
aging. Cu/Ni(V)/Al thin film metallization, J. Appl. Phys. 87,
Underfilled FCOB can pass JEDEC thermal 750-754, 2000
cycling test at 1000 cycles. Those without underfill 11. Joachim Kloeser, Andreas Ostmann, etc, Low Cost Flip
failed as expected at 110 cycles due to cracks in the Chip Based on Chemical Nickel Bumping and Solder
solder joint. The Ni-Sn intermetallic thickness change Printing, ISHM’96 Proceedings, 93-102.
was negligible in the solder joint during the thermal 12. Simon P. C. Law, Jian Cai, Philip C. H.Chan, A Study
cycling. of Passivation Defect on Electroless Nickel UBM, 4th
International Academic Conference on Electronic
Packaging Research, Education and Training for new
Acknowledgement Millennium, March 5~ 6, 2001, Hong Kong
13. Sabine Anhock, Andreas Ostmann, etc, Reliability of
This work is supported by the Innovation and Electroless Nickel for High Temperature Applications,
Technology Fund, Hong Kong SAR, number 1999 Int’l Symposium on Advanced packaging
ITS/196/00 and the Cooperative Research Center Materials, 256-261.
Grant, Research Grants Council of Hong Kong, 14. Kwang-Lung Lin, Yi-Cheng Liu, Manufacturing of
number CRC96/99.EG02. The authors would like to Cu/Electroless Nickel/Sn-Pb Flip Chip Solder Bumps,
thank Miss Cell Wong, Miss Katherine Ho, Mr. Eric IEEE Transaction on Advanced Packaging, Vol. 22,
No.4, 1999.
Yan, and Mr. S. F. Luk for their help. The authors 15. Chwan-Ying Lee, Kwang-Lung Lin, The interaction
would also like to acknowledge the donation of kinetics and compound formation between electroless
electroplating chemical from Shipley Asia Ronal Ltd., Ni-P and solder, Thin Solid Films, 249(1994), 201-206
Engelhard-Clal Hong Kong Ltd. and the support of 16. Michael J. Sullivan, The Effects of Interfaces on C-4
Microelectronics Fabrication Facility and Materials Solder Bump Reliability, MRS Symp. Proc. Vol. 515,
Characterization and Preparation facility in HKUST. 1998, 55-66.

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