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ENGINEERING
Digital Integrated Circuits - ENCS333
Saturday
Sunday
Monday O. H. O. H. ENCS313/Masri303
Tuesday ENCS333/Masri108 O. H. ENCS333/Masri108 O. H.
Wednesday O. H. ENCS313/Masri303
Thursday ENCS333/Masri108 O. H. ENCS333/Masri108
Friday
2
Digital Integrated Circuits
Course topics and Schedule
Subject
Assessment Policy
Assessment Type Expected Due Date Weight
Short Exam/QZes TBD 15%
Midterm Exam TBD 30%
Projects/Assignments TBD 20%
4
Design Abstraction Levels
SYSTEM/ARCHITECTURE
MODULE
+
GATE
TRANSISTOR
Vin Vout
DEVICE
G
S D
n+ n+
6
Intel 8486
Technology Evolution: Intel CPU Chips
Lec 1 8
Intel 8286 Intel 8486
Courtesy Intel
80x86 Evolution
Base SoC Handheld Tablet
Micro Server
10
Courtesy Intel
An estimate of the maximum number of transistors per chip over time.
Scaling
• Technology shrinks by 0.7/generation
• With every generation can integrate 2x more
• functions per chip; chip cost does not increase significantly
• Cost of a function decreases by 2x
• How to design chips with more and more functions?
• Design engineering population does not double every two
years…
• Need to understand different levels of abstraction
12
13
ISSCC2016-01_Visuals.pdf
14
15
3D Gate
16
CMOS
17
The MOS transistor
p-ch
• Symbols:
n-ch
4T (Bulk to VCC/VSS) 3T
• Physical structure:
Gate Gate
Source Drain Source Drain
n+ n+ p+ p+
channel channel
p-well n-well
p-substrate p-substrate
n-ch MOS p-ch MOS
The MOS transistor -
the different modes of operation
Vgs > Vt ; Vds=0V
Gate
Source Drain 0V
n+ n+
p-sub
n-ch MOS
Process technology
20
Capacitance of the MOS Transistor
Cp Cgd Cdb
diodes
Ca
Overlap cap
Parameters:
Diffusions area (diodes)
Diffusions perimeter (diodes)
Gate W (overlap cap)
Gate W*L (gate cap) Cgb Cgs Csb
Doping profiles
Note: all capacitors have voltage
dependence (not simple caps)
P1262 Line Capacitance Calculation
W S W
Cf Cf
CA1 td CA1
nwell N diffusion
P diffusion
poly
poly
Nwell tap substrate tap S D
G
Layout vs. Schematic
24
Microwind
Sequential elements
d o
d o d o
clk clk
clk
Master Slave
Latch is open
Latch is closed
clk
o
Timing
A 20 A
B 30
20ps
G
30
O G
30
C 30 H 30ps
D 20 O
C4 bump pattern:
296u: provide an 86um trace width bussing on surface layer
270u
provide a 76um trace width
bussing on 2F layer
30
Challenges
Frequency/speed Moore’s Law - Logic Density/Area
Power
31
https://video.search.yahoo.com/yhs/search?fr=yhs-iba-1&hsimp=yhs-
1&hspart=iba&p=vlsi+semiconductor+youtube+intel#id=3&vid=c096894102ab5f6e
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https://video.search.yahoo.com/yhs/search?fr=yhs-iba-1&hsimp=yhs-
1&hspart=iba&p=vlsi+semiconductor+youtube+intel#id=4&vid=42b014a8c2a22357
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https://video.search.yahoo.com/yhs/search?fr=yhs-iba-1&hsimp=yhs-
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https://video.search.yahoo.com/yhs/search?fr=yhs-iba-1&hsimp=yhs-
1&hspart=iba&p=vlsi+semiconductor+youtube+intel#id=10&vid=c143e8a683f11e6
d3c3510a91ec6c551&action=view 32