This action might not be possible to undo. Are you sure you want to continue?

# A Direct Digital-to-RF Digital-to-Analogue Converter using Image Replica and Nonlinearity Cancelling Architecture

S. Balasubramanian and W. Khalil

A parallel architecture for a direct digital-to-RF digital-to-analogue converter (DDRFDAC) is proposed for digital radio transmitters. Multiple paths of wide-bandwidth DACs are used, each fed with interleaved signal samples and each sampled at interleaved time instants. This results in the cancellation of the first N-1 replica images and the first N-1 nonlinearity spurs, thus allowing for wideband operation.

Introduction: The linchpin in future radio transmitters is a direct digital-to-RF converter, so as to allow for the implementation of the whole transmitter chain on a single reconfigurable device that supports multimode/multiband operation. Digital-toanalogue converters (DACs), the main building blocks in digital transmitters, are known to suffer from the problems of nonlinearity and generation of replica images due to its sample-and-hold operation. In particular, the sampling image replica problem forces the need for stringent post-DAC filtering. Conversely, relaxed filter requirements limit the instantaneous bandwidth that DACs can achieve to baseband frequencies, hence forcing the need for RF up-conversion through mixing operation. Consequently, this hinders the feasibility of an entirely-digital radio transmitter, which is the requirement in Tier 3 and 4 software defined radios (SDRs) [1]. Several techniques in improving the spectral properties of DACs have been proposed [2 - 5]. In [2], a dual path partial-order hold DAC architecture was shown to cancel image replicas, but the cancellation was limited to the frequency range fclk to 3 fclk/2, where fclk denotes the sampling clock frequency. Dithering and dynamic element matching techniques are well known to mitigate nonlinearity problems, but are not suitable for

Fig. but are limited to narrow bandwidth operation. When tk is chosen to be k*Tclk/N. Bandpass delta-sigma modulators [4] have been proposed towards direct digital-to-RF generation. A recent approach of using poly-phase circuits has been proposed for cancelling mixer and amplifier nonlinearities. This requires a close to ideal post-DAC reconstruction filter and thus restricts the DAC signal generation to frequencies well below half the sampling clock. where tk is the instant of reconstruction of the kth path. 1 depicts the complete block-level transmitter using the proposed DDRF-DAC. . its sampling image replica also moves closer to fclk/2 (Fig.high frequency operation [3]. When samples of a digital signal are fed across N DACs in N paths. Direct Digital-to-RF DAC: The proposed Direct Digital-to-RF (DDRF) DAC uses a parallel path architecture with N DACs. Alternatively. Each DAC is made to reconstruct at different time instances by the use of multi-phase sampling clocks. for any frequency f. as the signal frequency moves close to fclk/2. 2). In effect. so that the first N-1 sampling image replica components and the first N-1 nonlinearity spurs of the signal are cancelled. This allows for close-to-Nyquist frequency generation with relaxed post-DAC filtering and also results in increased output SNR. Cancellation of sampling image replicas: In a conventional DAC. the signal in the kth path incurs a phase shift of 2πf*tk. The outputs of all the DAC paths are then summed together. with each path reconstructing at a different time instant. the signal spectrum in each path sees a different phase shift for all frequencies. each being fed with interleaved digital data samples. and acts as a strong interferer for the signal of interest. but has not been applied to DACs [5]. the phase of the signal in the kth path is rotated by. a cascoded load impedance compensation technique was proposed for RF DACs. but it still calls for stringent post-DAC filtering requirements [3].

all images have the same phase. it guarantees a constant phase shift within the bandwidth of the signal and within each replica. For them to be cancelled. Fig. and the fact that the sum of all paths is equivalent to a sum of the exponents of the individual phases: = 0= 0 k k ∑e N −1 jφk ( f ) = ∑e N −1 j 2π ik N = 0. As a result. ∀ i ≠ 0. the spectrum shows a null at fclk. 3 illustrates the signal feeding scheme and the DAC clocking (i.e. As a result. until (N-1)*fclk as well as (N+1)*fclk. the images undergo a phase rotation by ji for the ith image. (N+2)*fclk. N . all frequency components within the bandwidth of an image replica must suffer the same rotation. reconstruction) scheme. The rotation and cancellation of the image .φk(f) = 2πfTclkk/N (1) Considering f=i*fclk such that i indicates the ith image replica of a DAC. the combined output reinforces the desired signal and the replica at 4fclk. 2 N . but cancels the image replicas at fclk. etc. different frequency components within the bandwidth of an image replica have different phases. However this analysis is true only in the case of zero bandwidth signals. when samples of the desired signal are generated and reconstructed at t=0 in the 0th path. etc. (2) In other words. undergoes a complex multiplication by (-1)i and (-j)i for the ith image.. 2fclk. This allows for a change in the phase of the signal in such a way that together with the reconstruction. The signal when reconstructed at t=Tclk/2 and t=3*Tclk/4. and when reconstructed at t=Tclk/4 in the 1st path.. This is achieved by the generation of time-interleaved samples of the signal at intervals of Tclk/N and feeding each path of the DAC with unique samples. Considering the case for N=4. the combined output of the parallel paths does not cancel the image replicas completely across its bandwidth. 2fclk and 3fclk. For a non-zero bandwidth signal. the sample generation followed by a time-lead reconstruction allows for N-1 image replicas to get cancelled by combining the DAC outputs from each path. Hence. respectively..

For example. The multipath approach adopted for image replica cancellation realizes the necessary phaseshifts before and after the nonlinear device (DAC).replicas in the complex domain for a 4-path DAC is depicted in Fig. As a result of combining the outputs of all N-paths. is multiplied by (exp(2πk/N))i. Discussion of Results: A DAC with four parallel-paths clocked at 10 GHz was simulated to generate a signal at 3. 2. the signal of interest reinforces. 5a illustrates the output spectrum for a single path with output nonlinearity spurs occurring at 0. the first N-1 harmonics are cancelled as illustrated in Fig. the signal and its replica) results in a spur that does not cancel. 20 GHz.975 GHz. for an N-path DAC. 30 GHz. In summary.513 GHz. Cancellation of Nonlinearity: When an RF signal is split with different phases across multiple paths of a nonlinear device. and image replicas occurring around 10 GHz. 4a. and is analogous to that explained in [5].5375 GHz. Fig. the ith DAC path should be reconstructed at instances ((i-1) modulo N)*Tclk/N. etc. 5b . The nonlinearity spurs undergo similar rotation as explained in the previous section. and recombined with appropriate phase shifts. etc. in order to achieve image replica cancellation across its bandwidth. Fig. Hence. while the nonlinearity spurs cancel out [5]. greatly relaxing the post DAC filtering requirements. However. the second-order intermodulation of a reinforcing and cancelling entity (for example. the signal at f0 and its replica at fclk-f0 mix to create a spur very close to the signal at fclk-2f0 that is not cancelled out and is made to disappear only by means of implementing a differential DAC topology. and should be fed with samples generated at instances i*Tclk /N. The advantage of pre-processing the signal at digital baseband along with time-interleaved clocking of the DACs is that the need for broadband phase-shifters is replaced by simple time manipulations of the signal and the sampling clock. the spectrum for the ith image (where i=0 to N-1) in the kth path (for k=0 to N-1). 4b.

instead was cancelled by means of a differential output.975 GHz generated by the signal and its first replica was not cancelled by the parallel-path combining process. the reinforcement of the second-order intermodulation term at 2. . 20 GHz and 30 GHz. Using time-shifted clocks and interleaved signal samples both sampling image replicas and nonlinearity spurs can be cancelled and higher output SNR can be achieved. Simulation results validate the concept of image replica cancellation and nonlinearity cancellation for a four-path parallel DAC. The proposed topology enables near-to-Nyquist operation by relaxing the post DAC filtering requirement. Conclusion: A parallel DAC architecture suitable for direct digital to RF transmitters and simultaneous multi-band operation is presented. As mentioned in the earlier section. The higher order spurs are of low amplitudes and hence are not visible. illustrating the cancellation of all nonlinearity spurs until and including that of the third order. and the cancellation of the first three image replicas around 10 GHz.depicts the simulated spectrum at the combined output of all paths.

1785–1794 Authors’ affiliations: S. IEEE Journal of Solid-State Circuits. S. KLUMPERINK.. and KIAEI. May 2008. E.. A. B. Columbus. P. pp. United States of America) Email: balasubramanian.. Dec 2009. 2005. pp. T.. CHI-HUNG et al. 1109–1113 3 LIN. B. The Ohio State University.. IEEE Transactions on Circuits and Systems. A.edu . Khalil (Department of Electrical and Computer Engineering.9 GS/s DAC with IM3 < -60 dBc beyond 1 GHz in 65 nm CMOS’. 1059–1068 5 MENSINK. : ‘A linear Σ-Δ digital IF to RF DAC transmitter with embedded mixer’. IEEE Transactions on Circuits and Systems II.. and KINGET. IEEE Transactions on Microwave Theory and Techniques. E.35@osu. : ‘Distortion cancellation by polyphase multipath circuits’. COPANI. M. 2008. : ‘A 12 bit 2.References 1 http://www. and NAUTA. 2015 Neil Avenue. BAKKALOGLU. pp. S. Balasubramanian and W.org/ 2 JHA. Ohio 43210.wirelessinnovation. pp. M. 3285– 3293 4 TALEIE. : ‘Wideband signal synthesis using interleaved partialorder hold current-mode digital-to-analog converters’.

Figure captions: Fig. 3 Signal samples generation scheme and DAC clocking scheme for N=4 parallel-path DACs. a Image replica cancellation b Non-linearity spur cancellation Fig. 4 Image replica and nonlinearity spur cancellation in the parallel-path DACs for N=4. The effect of the DAC’s sinc transfer function is not depicted for clarity of concept. 5 Simulation results for image replica and nonlinearity spur cancellation a A single path nonlinear DAC b An N=4 parallel path DDRF-DAC . 1 Block diagram of the proposed DDRF transmitter Fig. 2 Generation of image replicas in a DAC Fig. Fig.

Figure 1 INTERLEAVED DIGITAL SIGNAL SAMPLES ANTENNA DAC 0 FILTER DIGITAL BASEBAND DAC N-3 DAC N-2 DAC N-1 PA MULTI-PHASE CLOCK GENERATION MULTIPLE CLOCK PHASES .

5fCLK fIM fCLK fCLK+fO f .Figure 2 POST DAC FILTER RESPONSE Desired signal Image Replicas 0 fO 0.

Figure 3 4 3 2 1 1 2 1 3 4 1 2 3 4 1 2 3 4 1 4 3 2 1 3 2 4 DAC 0 1 4fCLK DAC 1 DAC 2 DAC 3 t .

Figure 4 Re Re 0 Im Re fCLK 2fCLK 3fCLK 4fCLK f Im f0 Re 2f0 3f0 4f0 5f0 f fCLK 0 Im Re fCLK 0 Im Re 2fCLK 3fCLK 4fCLK f Im 3fCLK 2fCLK 4fCLK f Im Re 2fCLK 3fCLK 4fCLK f f0 Im Re f0 f0 Re 2f0 3f0 4f0 5f0 f 2f0 3f0 4f0 5f0 f 3f0 4f0 2f0 5f0 f 0 Im Re fCLK IMAGE REPLICAS CANCELLED NONLINEARITY SPURS CANCELLED 0 Im fCLK 2fCLK 3fCLK 4fCLK f Im f0 2f0 3f0 4f0 5f0 f (a) (b) .

Figure 5 Desired Signal Nonlinearity Spurs fs image 2fs image 3fs image 4fs image (a) (b) .