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# STA

## What Is Positive Slack?

The difference between required arrival time and actual arrival time is positive, then is called as
positive slack. If there is positive slack, the design is meeting the timing requirements and still it
can be improved.
What Is Negative Slack
The difference between required arrival time and actual arrival time is Negative, then it is called
as Negative slack. If there is negative slack, the design is not meeting the timing requirements
and the paths. which have negative slack called as violating paths. We must fix these violations
to make the design meeting timing.
In Back-end Design Which Violation Has More Priority? Why?

In back-end design, hold violation has more priority than Setup Violation. Because hold violation
is related to data path and not depends on clock. Setup violation can be eliminated by slowing
down the clock (Increasing time of the clock).

What Is Slack?

The difference between Required Arrival Time and Actual Arrival Time is called as Slack. The
amount of time by which a violation (Either setup or Hold) is avoided is called the slack.

## What Is Static Timing Analysis(sta)?

Static timing analysis is a method for determining if a circuit meets timing constraints without
having to simulate. So, it validates the design for desired frequency of operation, without
checking the functionality of the design

## What Is Setup Time?

Setup time is the amount of time before the clock edge that the input signal needs to stable to
guarantee it is properly accepted on the clock edge.
What Is Hold Time

Hold time is the amount of time after the clock edge that the input should be stable to
guarantee it is properly accepted on the clock edge.

## What Is Setup and Hold Time Violations?

Violating above setup and hold time requirements is called setup and hold time violations. If
there is setup and hold time violations in the design does not meet the timing requirements and
the functionality of the design is not reliable. STA checks this setup and hold violations.

## 2. Redesign the flip flops to get lesser setup time

3. The combo logic between flip flops should be optimized to get minimum delay

4. Tweak launch flip-flop to have better slew at the clock pin, this will make launch
flip-flop to be fast there by helping fixing setup violations.

What are all the items that are checked by static time analysis?

Static timing analysis is used to check mainly the setup time and hold time checks

## Describe a timing path.

For standard cell-based designs, following figure illustrates basic timing path. Timing path
typically starts at one of the sequential (storage element) which could be either a flip-flop or a
latch. The timing path starts at the clock pin of the flip-flop/latch. Active clock edge on this
element triggers the data at the output of such element to change. This is the first stage delay
which is also called clock -> data out(Q) delay. Then data goes through stages of combinational
delay and interconnect wires. Each of such stage has its own timing delay

What determines the max frequency a digital design will work on. Why hold time is not
included in the calculation for the above?

Worst max margin will decide the max frequency a design will work on. As setup failure is
frequency dependent. Hold failure is not frequency dependent hence it is not factored into the
frequency calculation.
One chip which came back after being manufactured fails setup test and another one fails a
hold test. Which one may still be used how and why?

Setup failure is frequency dependent. If certain path fails setup requirement, you can reduce
frequency and eventually setup will pass. This is because when you reduce frequency you
provide more time for the flop/latch input data to meet setup. Hence, we call setup failure a
frequency dependent failure. While hold failure is not frequency dependent. Hold failure is
functional failure. Following figure shows frequency dependence of setup failure.

FPGA

What is FPGA?

## Field Programmable Gate Array is a semiconductor device containing programmable logic

components called "logic blocks", and programmable interconnects.
Logic blocks can be programmed to perform the function of basic logic gates such as AND, and
XOR, or more complex combinational functions such as decoders or mathematical functions. In
most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or
more complete blocks of memory.

## What are the differences between FPGA and CPLD?

FPGA:
A) SRAM based technology.
B) Segmented connection between elements.
C) Usually used for complex logic circuits.
D) Must be reprogrammed once the power is off.
E) Costly
CPLD:
A) Flash or EPROM based technology.
B) Continuous connection between elements.
C) Usually used for simpler or moderately complex logic circuits.
D) Need not be reprogrammed once the power is off.
E) Cheaper

## What is slice? What is CLB?

The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing
synchronous as well as combinatorial circuits. CLB are configurable logic blocks and can be
configured to combo, ram or rom depending on coding style CLB consist of 4 slices and each
slice consist of two 4-input LUT (look up table) F-LUT and G-LUT. The memory assignment is a
clocked behavioural assignment, reads from the memory are asynchronous, and all the address
lines are shared by the read and write statements.
1. Static timing: 2. Dynamic timing:

a. The delays over all paths are added up. a. The design is simulated in full timing mode.

b. All possibilities, including false paths, b. Not all possibilities tested as it is dependent on
verified without the need for test vectors. the input test vectors.
c. Much faster than simulations, hours as c. Simulations in full timing mode are slow and
opposed to days. require a lot of memory.
d. Not good with asynchronous interfaces d. Best method to check asynchronous interfaces
or interfaces between different timing or interfaces between different timing domains.
domains.

## FPGA design flow?

Block RAM
 It is a Dual port memory with separate Read/Write port.
 It can be configured as different data width 16Kx1, 8Kx8, 4Kx4 and so on.
 BRAM can be excellent for FIFO implementation.
 Multiple blocks can be cascaded to create still larger memory.
 The block RAM functions as dual or single-port memory.

Distributed RAM

##  Synchronous write and Synchronous/Asynchronous read

Inferring?

inferring is the logic which tool generate automatically which you don’t describe....

E.g. gate

Instantiation?

## E.g. module name (half adder)

Components of a slice?
1.LUT (look up table)
2.wide MUX
3.4 FF/L
4.4FF
5.4 bit carry chain

## Dff b/W STA and DTA?

STA
Doesn’t depend on test vector
STA check the timing
Faster
Suitable for sync design
Suitable for FPGA &ASIC semi-custom flow

It will show every path does not depend upon i/p vector.

DTA
It requires a test vector
Check for functionality & timing
Slower
Suitable for sync & async
ASIC full custom flow

## What is a critical path?

The path which takes more delay is known as critical path. The operating freq Is decided only by
critical path
The critical path of a circuit is the path between the input values and the output value which
has the longest delay.

## What are false paths?

False path which are physically there, functionally in active.
False path is a path will never work with clock, which can’t access at any input condition is
called false
Path.
The timing path in these topologies can’t be sensitized by any input vector even if both source
and destination flops are using same clock source.

## What is multicycle path?

Multicycle path is path which take more than one clk period to prohibit data from one flipflop to
another flipflop

## Explain Pipelining with a Verilog example?

Pipe lining is process in which the synchronizer (FF) inserted into the data path to reduce data
path delay which in turn to improves timing performance.
Verilog

Module pipelining
(input clk,
Input [7:0] a, b, c, d, e,
Output reg [16:0]y); // reg [15:0]y1,y2
always@(posedge clk) //reg [16:0]y3
y<=a*b+c*d+e; //y1<=a*b, y2<=c*d, y3<=y1+y2, y=y3+e;
end module

## Here getting large number of logic level

to avoid this logic level by introducing FF or registers, it become splitting the large combo logic
pipelining done in RTL project

RESULT
Pipelining reduce data path delay.
But it increase area.

## What is set max delay and set min delay?

The set_max_delay command set a maximum delay target for timing paths
The set_min_delay command set a minimum delay target for timing paths