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Abstract
A high-sensitivity voltage-to-frequency converter (VFC) using an all-MOS voltage window comparator is presented in this work. The
circuit is composed of one voltage-to-current converter, one charge and discharge circuit, and one all-MOS voltage window comparator.
The input voltage is converted into a current which in turn triggers the charge and discharge circuit, where a built-in capacitor is driven.
The voltage window comparator monitors the variated voltage on the capacitor and generate an oscillated output of which the vibration
frequency is linearly dependent to the input voltage. In this way, the worst-case linear range of the output frequency of the proposed VFC
is 0–55.40 MHz verified by simulations given a 0–0.9 V input range. The physical measurement of the proposed VFC shows a
0–52.95 MHz output frequency given a 0–0.9 V input range. The error in linearity is better than 8.5% while the power dissipation is
merely 0.218 mW.
r 2006 Elsevier Ltd. All rights reserved.
0026-2692/$ - see front matter r 2006 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mejo.2006.11.018
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198 C.-C. Wang et al. / Microelectronics Journal 38 (2007) 197–202
window comparator (VWC). The physical measurement of to discharge a storage capacitor in CDC. Thus, V cap is
the proposed VFC on silicon shows a 0–52.95 MHz output discharged. In the discharging operation, VWC compares
frequency given a 0–0.9 V input range. V cap with VL. The comparison results VOUT ¼ 0 ð0 VÞ
and VOUT ¼ 1 ð2:5 VÞ are generated for V cap 4VL and
2. CMOS voltage-to-frequency converter V cap oVL, respectively. VOUT ¼ 1 causes V cap to be
charged. Thus, a repeated loop is built and VOUT is the
The basic theory of voltage-to-frequency conversion is to output periodical oscillation.
track the back-and-forth variations of a certain signal level
in a pre-determined range. Thus, not only can it be easily 2.2. Schematic design of VFC
carried out by low-cost CMOS technology, but neither
external oscillators nor internal PLLs are required in the The schematic of VFC is shown in Fig. 2. An OPA
design. (operational amplifier) feeds a gate drive to an NMOS,
NM21. The negative terminal of the OPA is connected to
2.1. Architecture of the proposed VFC ground through a resistor, RT . Thus, the current is
dependent on the resistor, RT . Notably, the length of all
The proposed VFC is shown in Fig. 1. The input voltage, of the MOS transistors are set to be at least 5 times of the
V I , is converted into a current signal, I I , by a V-to-I circuit. feature size ð0:25 mmÞ to avoid any short-channel effect.
I I is fed to the CDC to generate a reference voltage, V cap , The width of PM21 is M times that of PM22 and PM23.
which is provided to the following VWC. VWC uses with Hence, the charging current for C T will be 1=M of the
two pre-defined reference voltages, VH (voltage high) current flowing through RT and NM21. Notably, VDD is
and VL (voltage low), which determine the range of the 2.5 V for this design.
voltage window. During the normal operation, V cap will be In addition to the input voltage V I , another input for
charged and discharged between the reference voltages, VL resetting the entire VFC is required, i.e., V INIT , which will
and VH. In the charging operation, V cap is charged. VWC be described later with the VWC circuitry. The charge–
compares V cap with VH and generates VOUT ¼ 1 ð2:5 VÞ discharge operation besides the initialization stage is
for V cap oVH. When V cap 4VH, VOUT ¼ 0 is generated described as follows.
Charging operation: The switch SW1 is shorted to node
a1. Then, the storage capacitor, C T , starts to be charged via
Vcap saturated PM23.
Discharging operation: As soon as the voltage of the C T ,
V cap , reaches VH, the output of VWC, VOUT, is switched
Charge and Voltage VH
VI V II Discharge Window low to short-circuit SW1 to node b1. NM23 is tuned to
to
I
Circuit
Voltage Control
Comparator VL be able to sink a current which is twice of the charging
(CDC) (VWC)
Charge or current provided by PM23. Thus, C T is discharged. As
Discharge soon as the V cap is pulled down to VL, VOUT will be
(VOUT)
turned high to start another cycle of charging-and-
Fig. 1. Architecture of the proposed VFC. discharging operation.
VDD
If Vcap > = VH
VOUT=0 V, discharge
Voltage If Vcap < = VL
Current VOUT=2.5 V, charge
Converter M*W/L W/L
(VCC) Vcap
PM21 PM22 PM23
b1 a1
VDD 0V 2.5 V
Vcap VH
VI OPA I sw1 VWC VL
VOUT
NM21 C T=1 pF
NM22 NM23
R T =2K Ohm
VDD
SW2 VOUT
b2
Vcap a2
2.5 V
VH VL NM58
NM54 NM55 NM56 NM57
VDD
I51 I52 a3 b3 I54
I53
2.5 V 0V
Iref 2.5 V 0V
SW3
V INIT SW4
a4 b4
NM51
NM52
VDD
NM53 NM59
Fig. 6. Output waveform given 0.1 V input. Fig. 8. Output waveform given 0.9 V input.
Fig. 7. Output waveform given 0.4 V input. Fig. 9. Output spectrum given 0.1 V input.
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C.-C. Wang et al. / Microelectronics Journal 38 (2007) 197–202 201
Tektronix TDS 680B oscilloscope, HP 8594E Spectrum because their equivalent input capacitance are far less than
Analyzer, and HP 1660CP Logic Analyzer are used to 8 pF. Moreover, the shape distortion of the square wave in
measure the performance of the proposed VFC. Figs. 6, 7, time domain is equivalent to the attenuation of high
and 8, are the measured output waveform in the time frequency components. Therefore, the exact output fre-
domain given 0.1, 0.4, and 0.9 V input, respectively. The quency of the VFC can be obtained in frequency domain
output frequencies at these input voltages are 6:184; 26:76, according to the fundamental frequency to discard the
and 52.95 MHz, respectively. The rise time and fall time of distorted shape in time domain, as shown in Figs. 9–11.
the waveform in Fig. 8 approximate to 10 ns, which is The measured spectra show the fundamental frequency and
mainly resulted from the capacitor load (about 8 pF) of the the attenuated harmonics.
probe. The 10 ns rise time and fall time would distort the The overall output frequency vs. input voltage measure-
maximum output frequency of 52.95 MHz whose period is ment is summarized in Fig. 12, where the expected values
around 19 ns. Notably, the distortion is resulted from the are the ideal values computed from a linear formula.
parasitic capacitor of the probe. Hence, the severe Fig. 13 reveals the error in Fig. 12. The error of f out is
distortion is predicted to be removed when the probe is computed by firstly subtracting the simulated or measured
disconnected. Furthermore, the distortion would not output frequencies from the expected values which are
happen when common commercial chips are driven
60 simulated
expected
50
measured
40
fout (MHz)
30 20.5
20 19.5
max. error < 8.5% 18.5
10 0.3
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Vin (V)
Fig. 12. Comparison of the measured, the expected, and the simulated
f out .
8.00%
6.00%
4.00%
2.00%
error (%)
Table 1
Characteristics of the proposed VFC design
Simulation Measurement
V in 0–0.9 V 0–0.9 V
Temperature 25 to 75 C 25 to 75 C
Technology 0:25 mm 1P5M CMOS 0:25 mm 1P5M CMOS
Max. O/P freq. 55.40 MHz 52.95 MHz
Error p8:5% p8:5%
Sensitivity X58 MHz=V X58 MHz=V
Power max. f out 0.17533 mW 0.218 mW
Chip area 440 460 mm2 440 460 mm2
Fig. 11. Output spectrum given 0.9 V input.
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202 C.-C. Wang et al. / Microelectronics Journal 38 (2007) 197–202
Table 2
Comparison to prior designs
given the same input voltage. Then, the subtraction results Acknowledgments
are divided by the maximum output frequency to obtain
the error of frequency in a percentage form, as shown in This research was partially supported by National
Fig. 13. The maximum error is less than 8.5% given the Science Council under grant NSC 91-2218-E-110-001 and
operating condition of a 10% VDD variation and the 91-2622-E-110-004. The authors would like to express their
temperature range from 25 to 75 C. An error of 8.5% of deepest gratefulness to CIC (Chip Implementation Center)
the proposed VFC in linearity seems a little large. of NAPL (National Applied Research Laboratories),
However, high sensitivity of the proposed VFC can Taiwan, for their thoughtful chip fabrication service. The
overwhelm the error in the linearity. Thus, a figure of authors also like to thank ‘‘Aim for Top University Plan’’
merit ðFOM ¼ sensitivity ðMHzÞ=error ð%ÞÞ can be de- project of NSYSU and Ministry of Education, Taiwan, for
fined to justify the specifications. partially supporting the research.
The overall characteristics of the proposed design by
measurement is tabulated in Table 1. The measured References
sensitivity is derived to be 52:95=0:9 ¼ 58:83 MHz=V. We
also make a comparison of our design and several prior [1] S. Cai, I.M. Filanovsky, High precision voltage-to-frequency con-
VFC designs in Table 2. Notably, the output frequency of verter, in: IEEE Midwest Symposium on Circuits and Systems, vol. 2,
1994, pp. 1141–1144.
[7] is from 1 to 7 KHz given a 0–3 V input. Thus, the [2] R.A. Pease, Amplitude-to-frequency converter, United States Patent
sensitivity of [7] is 2 KHz/V. It is obvious that our design no. 3746968, July 17, 1973.
outperforms the rest in the categories of the maximum [3] F.N. Trofimenkoff, F. Sabouri, J. Qin, J.W. Haslett, A square-rooting
output bandwidth, and sensitivity. Last but not least, the voltage-to-frequency converter, IEEE Trans. Instrum. Meas. 46 (5)
FOM of the proposed design is very much larger than that (1997) 1208–1211.
[4] H. Matsumoto, K. Waranabe, Switched-capacitor frequency-to-
of the prior VFCs, as shown in Table 2. voltage and voltage-to-frequency converters based on charge-balan-
cing principle, in: IEEE International Symposium on Circuits and
Systems, vol. 3, 1988, pp. 2221–2224.
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and Simulation, IEEE Press, New York, 1998.
This paper has proposed a high-bandwidth VFC. Not [6] M. Stork, New S-D voltage to frequency converter, in: Ninth
only are the sensitivity and output frequency dramatically International Conference on Electronics, Circuits and Systems, vol.
improved, but the overall manufacturing cost is reduced by 2, 2002, pp. 631–634.
[7] P.I. Yakimov, E.D. Manolov, M.H. Hristov, Design and implementa-
not using BiCMOS, and clock control circuitry. On top tion of a V-f converter using FPAA, in: 27th International Spring
of these advantages, the proposed VFC consumes only Seminar on Electronics Technology: Meeting the Challenges of
0.218 mW. Electronics Technology Progress, vol. 1, 2004, pp. 126–129.