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12/9/2018 LBIST - A technique for infield safety

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LBIST - A technique for infield safety

Nikhil Garg, Sagar Kataria, Abhishek Mahajan, Anurag Jindal (Freescale


In this modern era, design complexity and size of the

SOC is increasing at a very fast pace. Designers are 16,000 IP Cores from 450 Vendors
also moving to lower technology nodes to achieve the
higher performance targets. Enter Keywords....

There are defects which may appear during the field operation of device. The
infield failures are mainly because of latent faults which may not be apparent
or readily detectable while manufacturing testing but may evolve over a
period of time or during real time in field application because of
environmental conditions.
Debugging LBIST safe-stating issues
SOCs used in Automotive and military applications in particular are worst
Efficient methodology for design and
affected as the infield failures in these applications could be life threatening. verification of Memory ECC error
Stress testing like burn-in though provides a long term predictive stress management logic in safety critical SoCs
simulation environment but these are also only limited to a few years due to Safety intended Re-configurable
high test costs involved. In order to meet safety requirements, SOCs should Automotive microcontroller with reduced
boot-up time
be designed to perform in field testing.
Risks and Precautions to take care while
To detect the latent faults the device needs to have a mechanism where it using On-Chip temperature sensors in
Safety critical automotive applications
can perform routine tests on itself using software or LBIST based techniques.
In software based self-test the device checks its components functionality by Challenges in LBIST validation for high
reliability SoCs
providing functional test vectors and reads the response to check the pass or
fail status. Software testing could be an option for infield latent fault
detection but pattern generation in this case is manual and may not provide See Freescale Semiconductor Latest Articles >>
sufficient coverage in a given time frame.

Logic Built-in self-test (LBIST) helps to reduce the testing complexity by

order of magnitude. Logic- BIST is circuitry embedded in the chip that
performs scan based structural test of the design. This technique gives
measurement of fault coverage with minimum vectors and helps us PCI Express 3.0 needs reliable timing
overcome drawbacks of the earlier discussed techniques. As shown in the Fig design
1, it consists of test patterns generator and a circuit to analyze the output Designing an Effective Traffic Management
responses of the functional circuitry. System Through Vehicle Classification and
Counting Techniques

Improving reliability of non-volatile

memory systems

Gen-Z Primer for Early Adopters

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1. Dynamic Memory Allocation and
Fragmentation in C and C++
2. A Review Paper on CMOS, SOI and
FinFET Technology
Fig 1: LBIST Circuitry embedded in SOC 3. How to calculate CPU utilization
4. Design Rule Checks (DRC) - A
In this article, we will be discussing how LBIST testing differs from Practical View for 28nm Technology
conventional testing, some important applications of LBIST and design 1/4
12/9/2018 LBIST - A technique for infield safety
overhead of using LBIST in the design. 5. Why using Single Root I/O
Virtualization (SR-IOV) can help
improve I/O performance and Reduce
Scan v/s LBIST Testing Costs

As shown in the Fig 2a, Scan testing is deterministic ATPG testing where Test
See the Top 20 >>
patterns are pre-generated using a gate-level representation of the design
netlist. Scan testing requires Automated Test Equipment (ATE), which
controls the test patterns supplied to the SOC. Patterns are stored in tester
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memory and scanned into the circuit using parallel scan chains. Also, the
coverage target for scan testing is very high (>99% for stuck-at faults and
>90% for transition faults)

Fig 2a: Scan testing using deterministic ATPG

On the other hand, LBIST testing (as shown in Fig 2b) is Random ATPG
where an on-chip pattern generator feeds the scan chains, an on-chip result
compressor compresses the scanned out responses of all patterns into a final
signature. Fig2b shows the basic circuit level details of the LBIST. The
testing mentioned here is non-deterministic because PRPG which is
generating scan vectors here can’t be controlled externally. The LBIST in-
field coverage targets for automotive equipment is defined by ISO 26262
using ASIL levels (Automotive Safety integrity Level) which is applicable
throughout the lifecycle of all automotive electronic safety-related systems.
The coverage targets are different for different safety levels. For example,
For ASIL-D type of devices, diagnostic coverage target is greater than that of
ASIL-B and ASIL-C type of devices.

Fig 2b: Scan Testing using Random ATPG

Applications of LBIST

Safety for Infield test

For critical applications especially automotive, LBIST testing is generally

done. It is not for a one-time production test, but for repeated testing of the
SOCs in the field (or "in system" testing) to ensure that a satellite or medical
device or a car is working as expected. For example, for an electronically-
controlled braking system in the car, LBIST testing is run every time car is
turned on. If there is some fault in the device, and output signature is not
correct, it actually means logic might have some defects. In that case the
car's electronic controls can alert the driver that there is some issue in the
system and it might not be safe to drive the car.

The infield testing can be performed in different ways. The test can be
triggered by hardware every time the device is switched on (can be termed
as offline testing) or it can be triggered by software whenever the application
allows the test to run on the fly (can be termed as online testing) 2/4
12/9/2018 LBIST - A technique for infield safety
The testing can be used for end of life detection as a reliability test of device
by determining number of frequent failures that the device shows over a
period of time.

Logic BIST for Scan testing

As shown in Fig 3, many designs which have very large sizes and their scan
vector can’t fit into tester memory Logic BIST can be used to achieve test
coverage without utilizing much tester memory. Then top of it scan patterns
are generated to extract the remaining coverage which can’t be achieved
through random ATPG.

Fig 3: Logic BIST for Scan Testing

However it comes with its own challenges, the failure diagnostics with LBIST
is not as simple as compared to normal scan patterns. The diagnostics
require extra hardware to be implemented in design.

LBIST Overhead

The various advantages of using LBIST come with a cost. There is significant
design overhead which if not handled properly can degrade the system
performance significantly. The overhead discussed here could be because of

Area and power overhead because of extra test logic inserted in design
Timing Overhead because of test logic which is inserted in functional
paths to improve test coverage
Increase in design complexity to support in field testing implementation
and verification of associated logic


LBIST testing might increase design complexity but it is ideal for field and
system testing throughout the product life cycle, though it can be used for
fast manufacturing test bring up and in few cases for scan testing as well in
conjunction with normal scan testing as well. LBIST testing is must for safety
critical application designs such as automotive. With small area overhead
and the ability to achieve desires testing target in limited time, LBIST helps
designers to achieve their test goals to ensure a quality silicon.

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12/9/2018 LBIST - A technique for infield safety


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