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US 20110210436A1

(19) United States
(12) Patent Application Publication (10) Pub. No.: US 2011/0210436A1
Chow et al. (43) Pub. Date: Sep. 1, 2011
(54) INTEGRATED CIRCUIT PACKAGING (52) U.S. Cl. ................. 257/686; 438/109; 257/E21.506;
SYSTEM WITH ENCAPSULATION AND 257/E25.013; 257/E23.141
METHOD OF MANUFACTURE THEREOF
(76) Inventors: Seng Guan Chow, Singapore (SG); (57) ABSTRACT
Hin Hwa Goh, Singapore (SG);
Rui Huang, Singapore (SG); Heap
Hoe Kuan, Singapore (SG) A method of manufacture of an integrated circuit packaging
system includes: providing a base Substrate; attaching a base
(21) Appl. No.: 12/714,431 integrated circuit on the base Substrate; attaching a base bar
rier on the base substrate adjacent a base perimeter thereof;
(22) Filed: Feb. 26, 2010 mounting a stack Substrate over the base Substrate, the stack
Publication Classification
Substrate having a stack Substrate aperture with the stack
Substrate having an inter-substrate connector thereon; and
(51) Int. C. dispensing a connector underfill through the stack Substrate
HOIL 25/065 (2006.01) aperture encapsulating the inter-substrate connector, over
HOIL 2/60 (2006.01) flow of the connector underfill prevented by the base barrier.

100
N

130
156
104
106
154. 114 160 108

Patent Application Publication Sep. 1, 2011 Sheet 1 of 9 US 2011/0210436A1

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2011 Sheet 4 of 9 US 2011/0210436A1 690 634 636 FIG.884 842-1 EAE-9BGE ESES 810. V VJ. V. 1. V V. V V V 806 802 836 824 814 812 888 858 808 FIG. 7 890 846 874 878 880 876 882 886 -2' ECN NJ TriSEEA-flag N 834 830 fief it.Patent Application Publication Sep.nn inA ( )/( ) ()ty Y-868.8 .

1. 2011 Sheet 5 of 9 US 2011/0210436A1 890 A8 FIG.10 .. (YYA 400 1037 ESSEEGEEEEEE 1066 .. 1030(EEEEEEEEEEEEE gy-O'C) rury). 1010 EEEEEEEGGEEEEE 1004 . (Y.. 9 1000.N.Sisterestern-Silis. ISEEc-102) 1036 1018 1042 1016 1012 1014 1058 FIG.Patent Application Publication Sep. 1081 1074 1076 1088 1090 1086 1064 Y-?-? Y.

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Patent Application Publication Sep. 15 . 2011 Sheet 8 of 9 US 2011/0210436A1 1400 N 14 A A 14 1434 1490 FIG. 1.

1.Patent Application Publication Sep. 2011 Sheet 9 of 9 US 2011/0210436A1 16OO N .

greater grated circuit on the base substrate. including: a base Substrate. and more particularly to a underfill through the stack Substrate aperture encapsulating system for an integrated circuit packaging system with encap the inter-substrate connector. and low cost manufacturing. 7 is a top view of the integrated circuit pack space savings. and communication products for ever-reduced sizes.US 2011/021043. 11 to reduce costs. Continuous cost reduc 0013 FIG. The steps or elements will become apparent to those are particularly noteworthy. overflow of the connector underfill pre response to continually increasing demands on information vented by the base barrier. packaging system providing improved chip interconnection. 8 is a cross-sectional view of an integrated and cost reduction. DISCLOSURE OF THE INVENTION 0023 FIG. they do not 0015 FIG. camcorders. In view of the ever-increasing com a fifth embodiment of the present invention. and in a sixth embodiment of the present invention. it is increasingly critical that answers be circuit packaging system along a section line 8-8 of FIG. 13 is a top view of the integrated circuit pack aging System. 4 is a top view of the integrated circuit pack tion is another requirement. This is in substrate connector. vide more functions within an integrated circuit. 0022 FIG. ever-increasing need to improve performance. a base inte 0002 Increased miniaturization of components. 14 is a cross-sectional view of an integrated 0007. description when taken with reference to the accompanying hands-free cellular phone headsets. Solutions to these problems have long in a seventh embodiment of the present invention. eluded those skilled in the art. 1. 3 is a cross-sectional view of an integrated integrated circuits in an integrated circuit package while para circuit packaging system along a section line 3-3 of FIG. 0017 FIG. underfill prevented by the base barrier. 0008. improve efficiencies and performance. for example. . it is critical that 0019 FIG. 2 is a top view of the integrated circuit pack made Smaller and thinner as well.6 A1 Sep. overflow of the connector Sulation. the need circuit packaging system along a section line 10-10 of FIG. and so forth. thick 0009 Certain embodiments of the invention have other nesses. 0016 FIG. 2011 INTEGRATED CIRCUIT PACKAGING providing a base substrate. Some technologies primarily aging System. and a connector underfill components that are packaged therein while decreasing the through the Stack Substrate aperture encapsulating the inter sizes of the products that are made therefrom. integration. ful product differentiation in the marketplace. the stack Substrate having a TECHNICAL FIELD stack Substrate aperture with the stack Substrate having an 0001.13 Solutions and. aging System. thus. figurations that house and protect LSI require them to be 0011 FIG. 12 is a cross-sectional view of an integrated but prior developments have not taught or Suggested any circuit packaging system alonga section line 12-12 of FIG. Semiconductor package structures continue to Substrate aperture with the stack Substrate having an inter advance toward miniaturization. large-scale IC 0010 FIG. a need still remains for an integrated circuit a fourth embodiment of the present invention. and dispensing a connector grated circuit packaging system. to increase the density of the Substrate connector thereon. along with ever-increasing performance. 9 in found to these problems. attaching a base barrier on the base METHOD OF MANUFACTURE THEREOF Substrate adjacent a base perimeter thereof mounting a stack Substrate over the base Substrate. 10 is a cross-sectional view of an integrated answers be found for these problems. steps or elements in addition to or in place of those mentioned 0003. a base barrier on the base packaging density of integrated circuits (“ICs'). The present invention provides a method of manu circuit packaging system alonga section line 14-14 of FIG. 0006 Solutions to these problems have been long sought 0021 FIG. and costs. BRIEF DESCRIPTION OF THE DRAWINGS All of these devices continue to be made smaller and thinner to improve their portability. mercial competitive pressures. While these approaches pro of the present invention. circuit packaging system along a section line 6-6 of FIG. 7 in and cost reduction. The package con a first embodiment of the present invention. 9 is a top view of the integrated circuit pack expectations and the diminishing opportunities for meaning aging System. 11 is a top view of the integrated circuit pack the critical necessity for finding answers to these problems. In view of the aging System. in portable infor skilled in the art from a reading of the following detailed mation and communication devices such as cellular phones. notebook computers. meet competitive pressures adds an even greater urgency to 0020 FIG. 1 of cuit. Other technologies focus on Stacking these integrated an integrated circuit packaging system in a third embodiment circuits into a single package. 1 is a cross-sectional view of an integrated (LSI) packages that are incorporated into these devices are circuit packaging system along a section line 1-1 of FIG. 0004 Consumer electronics requirements demand more 0012 FIG. attaching a base integrated circuit SYSTEM WITH ENCAPSULATION AND on the base Substrate. The present invention relates generally to an inte inter-substrate connector thereon. The present invention provides an integrated circuit BACKGROUND ART packaging system. focus on integrating more functions into each integrated cir 0014 FIG. increased integrated circuits content. 2 in required to be made Smaller and thinner. higher per Substrate adjacent a base perimeter thereof: a stack Substrate formance. These increasing requirements for miniaturization above. and lower cost are ongoing goals of the computer over the base Substrate.15 facture of an integrated circuit packaging system including: in an eighth embodiment of the present invention. ("PDA's'). Additionally. 0005 Thus. 6 is a cross-sectional view of an integrated fully address the requirements for performance. personal data assistants drawings. integration. aging System. Accordingly. the stack Substrate having a stack industry. along with growing consumer 0018 FIG. 5 is a cross-sectional view similar to FIG. 4 in doxically providing less physical space in the system for the a second embodiment of the present invention.

The solder interconnects can have joints that are not 0042. include inadequate thermal performance of top packages in system configurations. or traces. The integrated circuit packaging system 0029 Where multiple embodiments are disclosed and 100 can represent a configuration of a packaging system. The problems can include a high 0027. The drawings showing embodiments of the system bottom packages in the current PoP structures. The current PoP structures can be mounted on printed circuit boards (PCBs) with underfill tongues formed BEST MODE FOR CARRYING OUT THE around the PCBs peripheries. development. is arbitrary for the most part. “over. include ascending. The base substrate 104 can include a base substrate horizontal as just defined. 0032. The base integrated circuit package 102 can provide deposition of material or photoresist. process.g. as shown in the figures. a for semiconductor devices having better mechanical perfor film. 1. The base integrated circuit 112 can be ture. particu an integrated circuit packaging system in a further embodi larly for PoP stacking structures that have same sizes. The base direct contact between one element and another element barrier 110 can be formed with an epoxy resin. such as “above”. The current PoP structures have a number of disad departing from the scope of the present invention. the term “horizontal as a printed wiring substrate. a wirebond integrated circuit. In the following description. The base integrated circuit package 102 can include sufficiently robust to cope with reliability test requirements a base encapsulation 126. The base integrated circuit package 102 can mance. described with similar reference numerals. The term “vertical refers to a direction perpendicular to the 0040. Solder a ribbon bond wire. complied to introduce the reinforcement layers (e. or a molding material. intended to have any other significance or provide limitations Such as a laminated plastic or ceramic Substrate. or a solder mask. or a conductive wire. etching. the base substrate 104 to mount a base integrated circuit 112. bottom surface 106 and a base substrate top surface 108 on a “bottom'. Such as a cover including an epoxy Such as temperature cycling tests or mechanical impact tests. molding compound. “side' (as in “sidewall”). patterning. It is to be understood that other embodiments age standoff gaps and the current PoP structures’ board-level would be evident based on the present disclosure. In current package-on-package (PoP) structures. are defined with respect to the bottom surface 106. with an underfillencapsulant interposed between packages or similar and like features one to another will ordinarily be in an inter-package standoff gap. system. Similarly. Terms. The base inte etc. Such as a bond wire. and comprehension thereof. 2 in a first embodiment of the can be operated in any orientation. 0035. an encapsulant. “below'. since peripheral balls can insuffi detail.US 2011/021043. as a matter of descriptive convenience and are not grated circuit package 102 can include a base Substrate 104. descending. or straight profile in structure. wiring layers. an organic or for the present invention. Vantages or problems. be practiced without these specific details. ciently or ineffectively dissipate heat through substrates of 0028. or mechanical changes may be made without 0036. The term “directly on' means that there is overflowing over sides of the base substrate 104. “top”. which can are shown exaggerated in the drawing FIGS. side of the base substrate 104 opposite the base substrate “upper”. or attached to the base Substrate top surface 0033. The embodiments 0039. 0034. integrated circuit 112. of the present invention provide answers or solutions to these Some of the dimensions are for the clarity of presentation and problems by providing various form factors. The base integrated circuit package 102 horizontal plane. a photoresist. second embodiment. described having some features in common. inorganic substrate. the invention along a section line 1-1 of FIG. . or 0030. numerous specific amount of wasted underfill materials. 2011 0024 FIG. some well-known circuits. There are increasing expectation and requirements 108 with an attach layer. tions. for clarity and which can include a pre-stacked package-on-package (PoP) ease of illustration. include a base integrated circuit package 102. present invention. it will be apparent that the invention may required to accommodate the long underfill overspreads. on. The term “on” means that there is direct contact formed to contain or prevent the underfill encapsulation from between elements. underfill 0. or an epoxy. Embodiments are semi-diagrammatic and not to Scale and. “higher. 1. thereon. especially for hand held and portable device applica include a base internal interconnect 114. regardless of its orientation. a long dispensing time details are given to provide a thorough understanding of the for double-layer standoff gaps. exposure. The term “processing as used herein includes 0041. description. and “under. Generally.16 is a flow chart of a method of manufacture of materials) in the package-to-package standoff gap. and/or removal of the mate Such as an integrated circuit die. although the views in the drawings for ease of description 0038 Referring now to FIG. and that mounting standoff gaps. rial or photoresist as required in forming a described struc or a chip. particularly. 15 is a top view of the integrated circuit pack The current PoP structures are not amenable or not readily aging System. mounted over.6 A1 Sep. The following embodiments are described in suffi PoP structures if conventional dispensing techniques are cient detail to enable those skilled in the art to make and use employed to provide underfill materials between inter-pack the invention. The integrated circuit packaging system 100 can have been numbered first embodiment. cleaning. ment of the present invention. can include a base barrier 110 defined as a dam or a structure 0031. to Surface of the integrated circuit. without an intervening element. this depiction in the sectional view of an integrated circuit packaging system 100 FIGS. an adhesive. “lower. a printed circuitboard (PCB). or a large PCB keep-out Zone invention. a carrier. However. therein is shown a cross generally show similar orientations.025 FIG. attached or con interconnects of a top package can be directly exposed to nected to the base substrate top surface 108 and the base environment without any reinforcement layers. provide electrical connectivity. and process steps are not disclosed in the current PoP structures. Long underfill overspreads (or INVENTION tongues) can be formed around the peripheries of the current 0026. In order to avoid 0037 Additional problems that need to be addressed can obscuring the present invention. For expository purposes. conductive layers. The base substrate 104 can include used herein is defined as a plane parallel to the plane or bond sites. Such as a die attach.

The external interconnect 160 can be a stack encapsulation 152. substrate bottom surface 132. SMT include an inter-substrate region 156 defined as spacing manufacturers can perform the underfill process only to the between the base substrate 104 and the stack substrate 130. 0053. face mount technology (SMT) manufacturers for pre-stacked 0049. substrate bottom surface 106. The base encapsulation 126 can be formed over 154. The integrated circuit packaging system 100 can PoP systems. a mastic material. 0058. attached to the base substrate bottom surface conductive wire. or a molding material. 2011 The base encapsulation 126 can include a taper side that is The inter-substrate region 156 can include spacing between Slanted to facilitate a release of a mold system in a molding the base substrate top surface 108 and the stack substrate process of the base encapsulation 126. the top side dispensing methods can be per pre-applied to increase thermal transfer efficiency. or traces. providing electrical connectiv 0047. or a metallic the base integrated circuit package 102. a solder column. is over the base substrate layer 154 can include a phase-change material or a thermal 104 that is attached to the external interconnect 160. bottom surface 132 and a stack substrate top surface 134 on a 0055 With the inter-substrate connector 158 attached to side of the stack substrate 130 opposite the stack substrate the stack substrate bottom surface 132. pad. nect 114. The stack encapsulation 152 can beformed over the tion as a reinforcement layer in the inter-substrate region 156. Such as an integrated circuit die. or a chip. surface 134. through the stack substrate 130. The stack substrate 130 can include a performed for the stack integrated circuit package 128. The base encapsulation 126 can be formed over the 0. to 108 and the stack substrate bottom surface 132. The integrated circuit packaging system 100 can pre-deposited with the connectorunderfill 162. such as a solder ball. ganic Substrate. The stack integrated include an external interconnect 160. such as a solder ball. attached on. a cement.052 The inter-substrate region 156 can include spacing base substrate 104. The integrated circuit packaging system 100 can The stack encapsulation 152 can include a taper side that is include a connector underfill 162. The ther formed with the connector underfill 162 dispensed through mal interface layer 154 can be deposited between or attached the stack substrate aperture 136 from the stack substrate top to a top surface of the base encapsulation 126 and the stack surface 134. The inter-substrate region 156 the base integrated circuit 112 and the base internal intercon can include the inter-package standoff gap. The stack device 142 can be attached to the nector 158 can be formed adjacent the base barrier 110. 0043. The stack substrate aperture 136 can be formed base substrate 104 with the inter-substrate connector 158. a circuit package 128 can include a stack device internal inter stud bump. 0060. the thermal interface facilitate the dispensing process. or a metallic connect 144. a stack device 142. or connected to the base Substrate top surface bond sites. an adhesive. mounted over the stack adjacent the base encapsulation 126. The stack integrated circuit package 128 can include ity to external systems. connected to. a printed circuit board (PCB). electrical tests can be bottom surface 132. an encapsulant. the thermal interface layer surface 108. The inter-substrate connector 158 can be formed in the inter-substrate region 156. The stack encapsulation 152 can be formed over The connector underfill 162 can be formed with board-level the stack device 142 and the stack device internal intercon underfill processes. a carrier. wiring layers. an area array around or along a base perimeter of the base 0046. or the process of the stack encapsulation 152. The inter-substrate circuit package 128 can include a stack Substrate 130. The stack integrated alloy conductor. partially covering the base substrate top for the base encapsulation 126. a film. The inter-substrate region 156 can be optionally 0051. 1. attached or connected to the stack Substrate 106. bottom surface 132. underfill encapsulant. an adhesive. a ribbon bond wire. 0050. The stack substrate aperture 136 defined as a through slot or an stack integrated circuit package 128 can be attached to the opening. which can be readily performed by Sur nect 144. The thermal interface layer 154 can optionally be For example. or 0045. attached on. such as a bond wire. For example. having the stack substrate aperture 136 to thermal transfer surfaces. The stack substrate 130 can include to. The external interconnect 160 can be formed on the base 130 and the stack device 142. Such as a cover including an epoxy formed in a full area array. partially covering the stack substrate top providing protection for the inter-substrate connector 158. stack substrate 130 with another attach layer. a liquid encapsulant. Such as a resin. The integrated circuit packaging system 100 can face material (TIM). The inter-substrate connector 158 can be formed in bottom surface 132 and the stack substrate top surface 134. or an epoxy. The stack substrate 130 can include a stack substrate connected on the inter-substrate connector 158. an organic or inor and the base integrated circuit 112. include a stack integrated circuit package 128 mounted over a stud bump. dispensing methods from atop Surface of a packaging system. stack substrate 130. between the stack substrate 0056. an underfill. or a 0054 The inter-substrate connector 158 can be attached printed wiring substrate. a metal conductor. an epoxy. The stack integrated circuit package 128 can include substrate 104 or a stack perimeter of the stack substrate 130. The inter-substrate con substrate 130. substrate 130 can be attached to. Also for example. include a descending structure profile such that the stack or a material that can be pasted or filled in gaps between substrate 130. a metal conductor. molding compound. As such. a wire The inter-substrate connector 158 can be formed around or bond integrated circuit. an encap Slanted to facilitate a release of a mold system in a molding Sulant. or a alloy conductor. such as a thermal inter 0059. a solder column. The connector underfill 162 can func 0048.US 2011/021043. conductive layers. As such. external interconnect 160 upon mounting the integrated cir . The stack provide electrical connectivity. The integrated circuit packaging system 100 can 0044) The integrated circuit packaging system 100 can include an inter-substrate connector 158. the thermal interface layer 154 can the connector underfill 162 can be dispensed with top side include thermal grease or thermal paste. such as a die 0057 The integrated circuit packaging system 100 can attach. or a combination thereof. include a thermal interface layer 154.6 A1 Sep. Such as connector 158 can be formed between the base barrier 110 a laminated plastic or ceramic Substrate.

It has further been discovered that the connector include a stack integrated circuit package 328 mounted over underfill 162 or the thermal interface layer 154 significantly the base integrated circuit package 302. a printed circuit board (PCB). As an example. 0068. The base substrate 304 can include a base substrate attached to the base substrate top surface 108 to prevent bottom surface 306 and a base substrate top surface 308 on a overspill.US 2011/021043. except for the formation of the stack substrate aperture 136 coplanar with the stack substrate top surface 134 after the of FIG. The base integrated circuit package 302 162 from overflowing over edges of the base substrate 104. substrate 130. The integrated circuit packaging sys shown with a portion of the connector underfill 162 formed tem300 can represent a configuration of a packaging system. an encapsulant. or better warpage control. The base substrate 304 can include improve thermal performance of the integrated circuit pack bond sites. provide electrical connectivity. a laminated plastic or ceramic Substrate. conductive layers. or spreaders. or a conductive wire. or 0075. For example. 0064. needle tips. providing better warpage control and improved 0077. the com greatly enhances the underfill process thereby eliminating plicated underfill process for multi-level standoff gaps can be complicated underfill processes for multi-level standoff gaps. In other words. film. a wirebond integrated circuit. the inter-substrate con a ribbon bond wire. a photoresist. molding compound. junctions where the inter-substrate connector 158 is attached 0072 Referring now to FIG. The integrated pensed with a dispenser or any encapsulation method during circuit packaging system 100 can include the stack encapsu manufacturing processes. a printed circuitboard (PCB). As another example. the base integrated circuit 312. an adhesive. to aging system 100. which can include dispensing guns. the stack substrate aperture 136 or a chip. The base inte dispensing of the connector underfill 162. The stack integrated enhances thermal dissipation of the integrated circuit pack circuit package 328 can include a stack substrate 330. or an epoxy. The base integrated circuit package 302 can provide 0066. The base integrated circuit 312 can be can be selectively formed at or near corners of the stack mounted over or attached to the base substrate bottom surface substrate 130 to encapsulate the inter-substrate connector 158 306 with an attach layer. The integrated circuit packaging system 100. can enhance the grated circuit package 302 can include a base substrate 304. a carrier. surface 134 after the dispensing process. Such as a die attach. or a molding material. 1 and that the dispensing process. or traces. therein is shown a top view 0061. on. the cross-sectional view is the present invention. The stack substrate 330 can include .6 A1 Sep. The base base perimeter. wiring layers. Syringes. avoided. such as aging system 100. 1 and the base barrier 110 of FIG. The base barrier 110 can be mounted over. The base barrier 110 can be formed adjacent or side of the base substrate 304 opposite the base substrate along the base perimeter to prevent the connector underfill bottom surface 306. lation 152 formed over a portion of the stack substrate top cartridges. Such as a cover including an epoxy mechanical drop impact tests. a that are critical. Therefore. 0078. It has also been discovered that encapsulating the The base encapsulation 326 can be formed over the base inter-substrate connector 158 with the connector underfill substrate 304. or inorganic substrate. mechanical shock/impact resistance performance. therein is shown a cross or connected to the base substrate 104 and the stack substrate sectional view of an integrated circuit packaging system 300 130 in the inter-substrate region 156. the stack substrate aperture 136. having 0074 The integrated circuit packaging system 300 can the stack substrate aperture 136 to facilitate encapsulation or include a base integrated circuit package 302. The connector underfill 162 can also a printed wiring substrate. adjacent or around encapsulate the inter-substrate connector 158 and joints or the stack encapsulation 152. integrated circuit packaging system 100 is inverted. tem 100. The connector underfill 162 can be filled or dis of the integrated circuit packaging system 100. It has been discovered that the connector underfill include a base internal interconnect 314. Surface 134. attached or con nector 158. The stack substrate aperture 136 can be strategically the base substrate 304 to mount a base integrated circuit 312. along a section line 3-3 of FIG. The integrated circuit packaging system 100 can The connector underfill 162 can be filled through the stack include a portion of the connector underfill 162 dispensed substrate aperture 136. the base barrier 110 can include a formed to contain or prevent the underfill encapsulation from closed loop structure that is contiguously formed around the overflowing over sides of the base substrate 304. the base barrier 110 can barrier 310 can be formed with an epoxy resin. The connector underfill 162 can over the stack Substrate top surface 134. 162. and the base 162 is significantly better in rheological control consistently internal interconnect 314. the 0073. providing Void-free coverage performance. a carrier. The base integrated circuit package 302 can 0067. over the stack substrate top surface 134. include a segmental structure that is partially formed around or a solder mask. and the base barrier 110 significantly improves nected to the base substrate bottom surface 306 and the base mechanical integrity of the integrated circuit packaging sys integrated circuit 312. 0076. an organic or inor 0070 Further it has been discovered that pre-depositing ganic Substrate. can include a base barrier 310 defined as a dam or a structure 0065. The base integrated circuit package 302 can include solder joint reliability based on thermal cycling tests and a base encapsulation 326. 2. or selectively formed near or at a peripheral area of the stack Such as an integrated circuit die. 3. or a the connector underfill 162 in the inter-substrate region 156 printed wiring substrate. mechanical integrity including temperature cycling test reli Such as a laminated plastic or ceramic Substrate. surface of the connector underfill 162 can be substantially 1. as examples. thereon. the base perimeter. an organic or ability. The integrated circuit packaging system 300 can be connector underfill 162 can be formed such that an exposed similar to the integrated circuit packaging system 100 of FIG. although it is under which can include a pre-stacked package-on-package (PoP) stood that the connector underfill 162 can be formed through with an underfillencapsulant interposed between packages or the stack substrate aperture 136 up to the stack substrate top in an inter-package standoff gap. 0071 Referring now to FIG. Such as a bond wire. 4 in a second embodiment of 0062 For illustrative purposes. 1. 0063. 2011 cuit packaging system 100 on the board. The integrated circuit packaging system 300 can 0069.

oran epoxy. although it is understood that a include an inter-substrate connector 358. facilitate the dispensing process. wiring layers. The thermal interface layer 354 can optionally be plicated underfill process for multi-level standoff gaps can be pre-applied to increase thermal transfer efficiency. Such as an integrated circuit die. the thermal interface pre-deposited with the connectorunderfill 362. or spreaders. or a metallic stack substrate top surface 334. The stack integrated circuit package 328 can include external systems. The inter-substrate connector 358 can be 0095. The integrated circuit packaging system 300 can The stack encapsulation 352 can include a taper side that is include an ascending structure profile such that the stack Slanted to facilitate a release of a mold system in a molding substrate 330. substrate top surface 334 to provide electrical connectivity to 0080. or a conductive wire. Syringes. The stack substrate 330 can include a include an external interconnect 360. for the stack encapsulation 352. The inter-substrate region 356 shown with an exposed surface of the connector underfill 362 can include the inter-package standoff gap. The integrated circuit packaging system 300 can through the stack substrate aperture 336 from the stack sub include a thermal interface layer 354. a metal conductor. 0088. the thermal interface layer 354 can external interconnect 360 upon mounting the integrated cir include thermal grease or thermal paste. The stack substrate 330 can include a stack substrate adjacent the stack encapsulation 352. Also for example. side of the stack substrate 330 opposite the stack substrate I0089. As such. attached thereto. such as a bond wire. a ribbon bond providing protection for the inter-substrate connector 358. partially covering the stack substrate connector underfill 362 can be dispensed with bottom side bottom surface 332. the cross-sectional view is 354. a mastic material. a stack substrate aperture 336 defined as a through slot or an stud bump. an encapsulant. bond integrated circuit. The stack encapsulation 352 can beformed over the interconnect360 and over the base substrate 304. the stack substrate 330. Such as a cover including an epoxy PoP systems. The inter-substrate region 356 can include spacing 330 in the inter-substrate region 356. SMT layer 354 can include a phase-change material or a thermal manufacturers can perform the underfill process only to the pad. needle tips. an adhesive. or traces. The stack substrate aperture 336 can be formed alloy conductor. Therefore. mounted over the stack 0090 The integrated circuit packaging system 300 can substrate 330. include an inter-substrate region 356 defined as spacing The connector underfill 362 can be filled through the stack between the base substrate 304 and the stack substrate 330. substantially coplanar with the stack substrate top surface 334 0087. Sulant. a solder column. mal interface layer 354 can be deposited between or attached 0093. The stack device 342 can be attached to the include a connector underfill 362. a wire formed in a full area array. The inter-substrate connector 358 can be formed in 0096. is attached to the external 0082. substrate aperture 336. such as a thermal inter strate top surface 334. The base barrier 310 can be formed adjacent or strate top surface 308 and the stack substrate bottom surface along the base perimeter. be performed with the connector underfill 362 dispensed 0083. the thermal interface layer 0094 For illustrative purposes. cuit packaging system 300 on the board. an encap stack substrate bottom surface 332 with another attach layer. or a material that can be pasted or filled in gaps between 0092. Such as a resin. a metal conductor. For example. underfill processes. 0091. an adhesive. The integrated circuit packaging system 300 can bottom surface 332. The external interconnect360 can beformed on the stack bottom surface 332 and the stack substrate top surface 334. The connector underfill 362 can be filled or dis to the base substrate top surface 308 and the stack encapsu pensed with a dispenser or any encapsulation method during lation 352. As such. The integrated circuit packaging system 300 can cartridges. or the Such as a die attach. the base barrier 310 can include a an area array around or along a base perimeter of the base closed loop structure that is contiguously formed around the . or a combination thereof. attached or connected to the stack The connector underfill 362 can be formed with board-level substrate bottom surface 332 and the stack device 342. having the stack substrate aperture 336 to process of the stack encapsulation 352. the com 0084. or a molding material. a liquid encapsulant. manufacturing processes. such as a solderball. which can be readily performed by Sur 0081.US 2011/021043. The inter-substrate connector 358 can be formed around or 0079. The connector underfill 362 can func integrated circuit package 328 can include a stack device tion as a reinforcement layer in the inter-substrate region 356. The ther avoided. The connector underfill 362 can The inter-substrate region 356 can include spacing between encapsulate the inter-substrate connector 358 and joints or the base substrate top surface 308 and the stack substrate junctions where the inter-substrate connector 358 is attached bottom surface 332. preventing the connector underfill 332. or connected to the base substrate 304 and the stack substrate I0086.6 A1 Sep. or a metallic opening. For example. The base barrier 310 can be mounted over or formed in the inter-substrate region 356. 362 from flowing over edges of the base substrate 304. attached to the stack Substrate top Surface through the stack substrate 330. 1. as examples. provide electrical connectivity. internal interconnect 344. which can include dispensing guns. 0085. an underfill. a film. The integrated circuit packaging system 300 can after the dispensing process. The stack underfill encapsulant. conductive layers. to substrate 304 or a stack perimeter of the stack substrate 330. a cement. 2011 bond sites. an epoxy. The stack encapsulation 352 can be dispensing methods from a bottom surface of a packaging formed over the stack device 342 and the stack device internal system. The inter-substrate attached to the base substrate top surface 308 to prevent connector 358 can be attached or connected to the base sub overspill. where the external interconnect 360 is face material (TIM). As an example. The stack integrated circuit package 328 can include face mount technology (SMT) manufacturers for pre-stacked a stack encapsulation 352. The external interconnect 360 can be a stack device 342. portion of the connector underfill 362 can be formed over the a stud bump. between the stack substrate 334. The inter-substrate con bottom surface 332 and a stack substrate top surface 334 on a nector 358 can be formed adjacent the base barrier 310. a solder column. molding compound. The inter-substrate region 356 can be optionally thermal transfer surfaces. such as a solder ball. alloy conductor. wire. or a chip. the bottom side dispensing methods can interconnect 344.

The stack integrated include a segmental structure that is partially formed around circuit package 528 can include a stack substrate 530. a die. 1. 1 of an integrated circuit pack a stud bump. The top substrate 566 can include 0104. provide electrical connectivity.US 2011/021043. 1. 0098.6 A1 Sep. area array. conductive layers. 1. respectively. the stack device internal Sulation process using the bottom side dispensing methods. and a base barrier 510. a stack device internal interconnect 544. having the base perimeter. wiring layers. The stack integrated circuit package 528 can be structure with various package types and an underfill encap mounted over the base integrated circuit package 502 with the Sulant interposed between packages or in inter-package inter-substrate connector 558. an organic or inor similar to the base substrate 104 of FIG. 2011 base perimeter. 558 can be attached or connected to the base integrated circuit 0103) The integrated circuit packaging system 500 can package 502 and the stack integrated circuit package 528. The top substrate 566 can include a top substrate integrated circuit 512 can be attached or connected to the base bottom surface 568 and a top substrate top surface 570 on a substrate top surface 508 with a base internal interconnect side of the top substrate 566 opposite the top substrate bottom 514. a stack substrate top 0097. interconnect 144 of FIG. a surface 568. of the integrated circuit packaging system 300. formed in a manner similar to substrate aperture 336. or a 110 of FIG. or a metallic aging system 500 in a third embodiment of the present inven alloy conductor. a stud bump. 1. or a bumped chip. a carrier. 504 and the stack substrate 530. a stack substrate bottom surface 532. therein is shown a top view FIG. The integrated circuit packaging system 500 can is shown with the stack substrate 330 of FIG. To facilitate the underfill encapsulation pro ing oversides of the stack substrate 530. mounted over the top include a stack integrated circuit package 528 mounted over substrate 566. and a stack substrate aperture 536. a solder column. or a chip. 1.4. 508 and the base integrated circuit 512 to protect the base 0114. the base barrier 310 can the base integrated circuit package 502. such as a strate 504 and the basebarrier 510 can be formed in a manner laminated plastic or ceramic Substrate. sectional view similar to FIG. thereon. top integrated circuit 574. to the base substrate 504 to mount a base integrated circuit 512. The integrated circuit packaging system 500 can wirebond integrated circuit. Such as an integrated circuit die. The top integrated circuit package 502 can include a base underfill substrate aperture 572 can be formed through the top sub 524. respectively. The base aperture 572 defined as a through slot or an opening. 1 and an addition of another package. The top substrate 566 can include a top substrate metal conductor. 0102 The integrated circuit packaging system 500 can The inter-substrate connector 558 can beformed adjacent the represent a configuration of a packaging system. except for the formation of the base integrated circuit 0110. such as a solder ball. and the stack encapsulation 152 of 0099 Referring now to FIG. The top integrated cir strate top surface 508. having a stack device 542. The inter-substrate region 0100. strate 566. mask. which can base barrier 510 in the inter-substrate region 556. between the top substrate bottom surface 568 and dispensed in the space between the base Substrate top Surface the top substrate top surface 570. a solder column. the external interconnect360 can be attached to the stack can be formed with an epoxy resin. 1 and the base barrier ganic Substrate. The inter-substrate connector 558 can be formed in package 102 of FIG. The integrated circuit packaging system 500 can be attached or connected to the base substrate top surface 508 similar to the integrated circuit packaging system 100 of FIG. Such as an epoxy resin or any underfill resin material. and the stack substrate bottom surface 532. therein is shown a cross include an inter-substrate connector 558. The inte inter-substrate region 556 can include spacing for the base grated circuit packaging system 300 can include the external integrated circuit 512. printed wiring substrate. The integrated circuit packaging system 300 can 556 can include spacing between the base substrate top sur include the connector underfill 362 dispensed in the stack face 508 and the stack substrate bottom surface 532. a photoresist. The top view 0108. The base 0113. 5. The inter-substrate connector 558 can be tion.1. substrate 504 or a stack perimeter of the stack substrate 530. As an example. 1 and the Stack integrated circuit package an area array around or along a base perimeter of the base 128 of FIG. The top integrated circuit package 564 can include a internal interconnect 514. the base internal interconnect 514. Such as a flip chip. The stack barrier 540 cess. or a solder substrate 330 after dispensing the connector underfill 362. substrate 330. or traces. The stack substrate aperture 336 can be strategically surface 534. or a metallic alloy conductor. a printed circuit board (PCB). include a multi-layer pre-stacked package-on-package (PoP) 0111. The substrate aperture 336 around the stack perimeter. include a base integrated circuit package 502. The base sub cuit package 564 can include a top substrate 566. a metal conductor. a 0105. The base integrated circuit package 502 can provide bond sites. For example. 3 having the include an inter-substrate region 556 defined as an inter stack substrate aperture 336 formed on the stack substrate top package standoff gap or spacing between the base Substrate Surface 334. The top integrated circuit 574 can be attached . formed in a or selectively formed near or at a peripheral area of the stack manner similar to the stack substrate 130 of FIG. or interconnect 360 formed on the stack substrate top surface any spacing between the base integrated circuit 512 and the 334. include a top integrated circuit package 564 mounted over the having a base substrate bottom surface 506 and a base sub stack integrated circuit package 528. the stack substrate aperture 336 0106 The stack integrated circuit package 528 can include can be selectively formed at or near corners of the stack a stack barrier 540 defined as a dam or a structure formed to substrate 330 to encapsulate the inter-substrate connector 358 contain or prevent the underfill encapsulation from overflow that are critical. 1. 0109 The integrated circuit packaging system 500 can 01. The inter-substrate connector standoff gaps. It has been discovered that the integrated circuit 0107 The stack integrated circuit package 528 can include packaging system 300 with the stack substrate 330. the external interconnect 360 attached thereto and the stack and a stack encapsulation 552. The base inte 0112 The integrated circuit packaging system 500 can grated circuit package 502 can include a base substrate 504. Such as a solder ball. The external interconnect 360 can be formed in a full stack substrate bottom surface 532. greatly enhances the underfill encap the stack device 142 of FIG.01 Referring now to FIG.

0. 1. strate top surface 608. The top encapsulation 582 can be formed over the stack Substrate top Surface 534. The external interconnect 588 can be formed on the base the base substrate 604 to mount a base integrated circuit 612. (0123. a liquid encapsulant. or an epoxy. a stud bump. substrate 530 or where the second inter-substrate connector The top encapsulation 582 can include a taper side that is 586 is attached or connected to the stack substrate 530 and the Slanted to facilitate a release of a mold system in a molding top substrate 566.1 and the basebarrier stud bump. an epoxy. 2011 to the top substrate 566 with an attach layer. inter-substrate connector 586. a solder column. or selectively formed at a peripheral area of the top substrate 0118. or the integrated circuit package 602 can include a base underfill underfill encapsulant. process of the top encapsulation 582. which can be readily performed by Surface mount strate. or a metallic 110 of FIG. The connector 0. The base ity to external systems. The second inter-substrate con along a section line 6-6 of FIG. The external interconnect 588 can be integrated circuit 612 can be attached or connected to the base formed in a full area array. attach. or a molding material. a metal conductor. As another example. a solder column. such as a resin. Such as an epoxy resin or any underfill resin material. or a technology (SMT) manufacturers for pre-stacked PoP sys PCB. needle tips. The second inter-substrate connector 586 can be tem 600 can represent a configuration of a packaging system. The integrated circuit packaging system 600 can underfill 590 can be formed with board-level underfill pro include a stack Substrate 630. 576. Syringes.6 A1 Sep. a metal conductor. respectively. The integrated circuit packaging system 600 can a top perimeter of the top substrate 566.124. the top substrate aperture 572 can be selec an inter-package standoff gap. an internal Stacking module. The second inter-substrate connector 586 can be poser by top side dispensing methods. formed in an area array around or along the stack perimeter or I0128. sectional view of an integrated circuit packaging system 600 or a metallic alloy conductor. The base sub 0121 The integrated circuit packaging system 500 can strate 604 and the basebarrier 610 can be formed in a manner include an external interconnect 588. a Sub cesses. substrate bottom surface 506. or 0115 The top integrated circuit package 564 can include a joints or junctions where the inter-substrate connector 558 is top encapsulation 582. The integrated circuit packaging sys 584. The second inter-substrate region 584 can include 566. a include a connector underfill 590. The top integrated cartridges. attached or connected to the top substrate 566 and the connector underfill 590 can encapsulate the inter-substrate top integrated circuit 574. an encapsulant. substrate top surface 608 with a base internal interconnect 0122) The integrated circuit packaging system 500 can 614. a similar to the base substrate 104 of FIG. The base inte substrate connector 586 can be formed around or adjacent the grated circuit package 602 can include a base Substrate 604. a stud bump. attached to the base substrate bottom surface I0129. and a base barrier 610. an underfill. The second inter include a base integrated circuit package 602. 7 in a fourth embodiment of nector 586 can be formed in the second inter-substrate region the present invention. include a second inter-substrate connector 586.126 The top substrate aperture 572 can be strategically strate bottom surface 568. the stack barrier 540 can include a 0117 The integrated circuit packaging system 500 can closed loop structure that is contiguously formed around the include a second inter-substrate region 584 defined as spacing stack perimeter. The connector underfill 590 can func 624. the second inter-substrate connector 586. the stack barrier 540 can between the stack substrate 530 and the top substrate 566. The second inter-substrate connec having a base substrate bottom surface 606 and a base sub tor 586 can be formed adjacent the stack barrier 540. 1. thereon. structure with an underfill encapsulant formed under an inter 0120. a film. The stack substrate 630 can be mounted over the base temS. As an example. such as a I0127. Such as a cover including an epoxy attached or connected to the base substrate 504 and the stack molding compound.130. or a bumped chip. Such as an interposer. The stack barrier 540 can surface 570. as examples. a die. which can include dispensing guns. respectively.125. or a metallic alloy conductor. adjacent or along the stack top substrate 566. a solder column. The base integrated circuit package 602 can provide 506. providing protec 608 and the base integrated circuit 612 to protect the base tion for the inter-substrate connector 558 and the second internal interconnect 614. connector 558.US 2011/021043. or spreaders. such as a bond wire. The connector underfill 590 can be filled or dis 0131 The stack substrate 630 can include a stack substrate pensed with a dispenser or any encapsulation method during bottom surface 632 and a stack substrate top surface 634 on a . Such as a solder ball. The connector underfill 590 can be filled through the the top substrate bottom surface 568. or a conductive substrate aperture 536 and the top substrate aperture 572. 6. circuit package 564 can include a top internal interconnect The connector underfill 590 can be filled through the stack 576. partially covering the top substrate top perimeter to prevent overspill. The base Sulant. such as a solder ball. The include a segmental structure that is partially formed around second inter-substrate region 584 can include spacing the stack perimeter. attached or connected to the stack substrate top surface 534 which can include a pre-stacked package-on-package (PoP) and the top substrate bottom surface 568. integrated circuit package 602. The second inter-substrate tively formed at or near corners of the top substrate 566 to region 584 can include spacing for the stack encapsulation encapsulate the second inter-substrate connector 586 that are 552 and any spacing between the stack encapsulation 552 and critical. tion as a reinforcement layer in the inter-substrate region 556 dispensed in the space between the base Substrate top surface and the second inter-substrate region 584. a ribbon bond wire. stack encapsulation 552. an interface module. such as a die manufacturing processes. 0. between the stack substrate top surface 534 and the top sub 0. Referring now to FIG. The top encapsulation 582 can be formed over prevent the connector underfill 590 from flowing over edges the top integrated circuit 574 and the top internal interconnect of the Stack Substrate 530. For example. an encap metal conductor. The stack barrier 540 can be formed over or on the 0116. providing electrical connectiv Such as a flip chip. alloy conductor. stack substrate aperture 536 and the top substrate aperture 0119 The integrated circuit packaging system 500 can 572 with top side dispensing methods. The wire. an adhesive. therein is shown a cross solder ball.

an encap 0138. an underfill. a Strate 630. mounted over the top stack substrate 630 can include bond sites. a metal conductor. The inter-substrate con 0146 The integrated circuit packaging system 600 can nector 658 can be formed adjacent the base barrier 610. a solder column. needle tips. between the stack substrate bottom surface 632 top second integrated circuit 678. Syringes. The stack substrate 630 can be mounted over the Sulant. 604 and the stack substrate 630. an adhesive. the integrated circuit bottom surface 668 and a top substrate top surface 670 on a packaging system 600 can include the top integrated circuit side of the top substrate 666 opposite the top substrate bottom package 664 having a smaller footprint mounted over the base surface 668. The integrated circuit packaging system 600 can manufacturing processes. con attached or connected to the base substrate 604 and the stack ductive layers. The top integrated circuit package 664 can include a bottom surface 632. conductive layers. and top surface 634 and the top substrate bottom surface 668. or a discrete component. The top substrate 666 can include bond sites. Such as a laminated plastic or through the stack substrate aperture 636. a film. wiring layers. The integrated circuit packaging system 600 can top integrated circuit 674. 658 or joints where the inter-substrate connector 658 is 0140. which can include dispensing guns. or spreaders.6 A1 Sep. The top integrated nected to the stack substrate bottom surface 632 and the stack circuit package 664 can include a top internal interconnect substrate top surface 634. an epoxy. attached to the base substrate bottom surface 606.148. The stack substrate 630 can include a stack substrate wire. underfill 690 can encapsulate the inter-substrate connector a printed circuit board (PCB). the top internal include an inter-substrate region 656 defined as an inter interconnect 676. such as a die attach. The inter-substrate connector 658 can be tion as a reinforcement layer in the inter-substrate region 656. The external interconnect 688 can be an area array around or along a base perimeter of the base formed in a full area array. The any spacing between the base integrated circuit 612 and the second inter-substrate connector 686 can be attached to a stack substrate bottom surface 632. Such as a passive 678 can be attached to the top integrated circuit 674 with an device. Such as a cover including an epoxy bottom surface 632. or an over the stack substrate 630. attached or connected to the base integrated circuit package providing protection for the inter-substrate connector 658. 676. such as a solder ball. substrate 604 or the stack perimeter. a solder column. The top integrated circuit package 664 can include a 642 can be mounted on or attached to the stack substrate top encapsulation 682. a in a singulated or strip form for encapsulant dispensing. 602 and the stack substrate 630 in the inter-substrate region 0147 The connector underfill 690 can be filled or dis 656. 1. The top encapsulation 682 can be formed over the top sub 0135 The integrated circuit packaging system 600 can strate 666. a stud bump. the cross-sectional view is to the top substrate 666 and the top second integrated circuit shown with the stack device 642 mounted on or attached to 678. The external interconnect 688 can be formed on the base and the stack substrate bottom surface 632. The wirebond integrated circuit. or a metallic include an external interconnect 688. or a chip. attached or connected 0134) For illustrative purposes. or the package standoff gap or spacing between the base Substrate top second internal interconnect 680. The inter-substrate region 0144. The integrated circuit packaging system 600 can center region of the stack substrate top surface 634. the stack substrate top surface 634. the stack substrate top surface 634. The top integrated circuit package 664 can include a substrate 630. or a printed wiring substrate. With the stack substrate 630. to provide electrical Substrate 630. to provide electrical connectivity to the top substrate 666 with an attach layer.139. 2011 side of the stack substrate 630 opposite the stack substrate 0. The top substrate 666 can includea top substrate 0. pensed with a dispenser or any encapsulation method during 0.141. the top second integrated circuit 678. substrate bottom surface 606. or a chip. a film. or a molding compound. a alloy conductor. stack substrate aperture 636 can be formed through the stack 0142. a ribbon bond wire. an active device. connectivity. such as a solderball. stack substrate 630. or a metallic attached or connected to the base substrate top surface 608 alloy conductor. The connector underfill 690 can func connector 658. such as a die between electrical devices or packaging systems that are con attach. The integrated circuit packaging system 600 can 656 can include spacing between the base substrate top sur include a second inter-substrate connector 686. The stack substrate 630 can be designed top integrated circuit 674. The top second integrated circuit optionally include a stack device 642. The stack device 642 can be epoxy. combination thereof. an encapsulant. mounted attach layer. such as a bond wire. or a conductive wire. a liquid encapsulant. mounted over the 0133. 0145 The integrated circuit packaging system 600 can a stud bump. although the stack device 0143. attached or connected to the top substrate 666 and the aperture 636 defined as a through slot or an opening. include a connector underfill 690. the base internal interconnect 614. or traces. an adhesive. a metal conductor. inter-substrate region 656 can include spacing for the base or a metallic alloy conductor. Such as a face 608 and the stack substrate bottom surface 632. The top integrated circuit package 664 The connector underfill 690 can be dispensed or filled can include a top Substrate 666. integrated circuit package 602 having a larger footprint. the top integrated circuit 674. a carrier. Such as an integrated circuit and the stack substrate top surface 634. or traces. an organic or inorganic Substrate. or an epoxy. a wirebond integrated circuit. die. 0136. providing electrical connectiv 0137 The inter-substrate connector 658 can be formed in ity to external systems. as examples. The inter-substrate connector 658 can be stud bump. a solder column. Such as an integrated circuit die. The second inter-substrate con nector 686 can be attached or connected to the stack substrate integrated circuit 612. or a conductive 0132. such as a bond wire. include an inter-substrate connector 658. The connector ceramic Substrate. The solder ball. a metal conductor. include a top integrated circuit package 664 mounted over the cartridges. The top integrated circuit 674 can be attached wiring layers. or the base integrated circuit package 602 with the inter-substrate underfill encapsulant. substrate 666. The top integrated circuit 674. ribbonbond wire. or a molding material. Such as a resin.US 2011/021043. The top integrated circuit package 664 can include a mounted around or along a stack perimeter of the stack Sub top second internal interconnect 680. The .

Such configuration can allow the dispenser or aperture 836 defined as a through slot or an opening. having a base substrate bottom surface top surface 870. 0150 Referring now to FIG. or a include a second inter-substrate region 884 defined as spacing PCB.165. The stack substrate protrusion 837 can out circuit packaging system 600 can include the stack Substrate wardly laterally extend from the center of the stack substrate 630 of FIG. the top second integrated a base integrated circuit 812. structure with an underfill encapsulant formed by top side 0164. to provide electrical 0149. The integrated circuit package 802. 6. the top second internal interconnect 880. respectively. bottom surface 832. The any encapsulation method to dispense the connector underfill stack substrate aperture 836 can be formed through the stack 690 beside or next to a vertical surface of the top integrated substrate 830. The integrated circuit packaging system 800 can in a singulated or strip form for encapsulant dispensing.168. 882. and a base barrier interconnect 876. wiring layers. along a section line 8-8 of FIG.6 A1 Sep. The integrated circuit packaging system device 846 can be mounted over or attached to the stack 800 can represent a configuration of a packaging system. and a top encapsulation formed in a manner similar to the base substrate 604 of FIG. include a stack substrate 830. edges of the stack substrate 830 can laterally extend stack perimeter. The base Substrate 804 and the base barrier 810 can be second internal interconnect 880. The stack device 842 can be which can include a pre-stacked package-on-package (PoP) mounted over a center region of the stack substrate 830. 7. The integrated circuit packaging system 800 can include a top integrated circuit package 864. The integrated circuit packaging system 800 can device. In other substrate aperture 636 can be formed around or along the words. The stack substrate 830 can include a stack substrate between the stack substrate top surface 834 and the top sub bottom surface 832 and a stack substrate top surface 834 on a strate bottom surface 868. include a second inter-substrate connector 886. 0156 The base integrated circuit package 802 can include the top internal interconnect 876. therein is shown a cross optionally include a stack second device 846. 6. substrate top surface 834.US 2011/021043. 0163 The integrated circuit packaging system 800 can 0153. second inter-substrate region 884 can include spacing 0158. an active device. 6. The stack substrate aperture 636 can be formed optionally include a stack device 842. The stack second present invention. The stack device 842 can be mounted around or the stack perimeter. con with a width smaller than that of the stack substrate 630. 6. The stack substrate 830 can be mounted over the base between the stack substrate 830 and the top substrate 866. The integrated circuit packaging system 800 can strate. a sub 0167. The stack substrate aperture 636 can be formed base substrate 804. 6. an interface module. The inter-substrate region 856 and the inter similar to the integrated circuit packaging system 600 of FIG. and the base underfill 824 can the top substrate 666 of FIG. the top encapsulation 882 can be formed in a manner similar to base internal interconnect 814. The stack substrate 830 can include bond sites. an internal Stacking module. 6.161 The stack substrate 830 can include a stack substrate of the integrated circuit packaging system 600. package 664 of FIG. the top integrated circuit 874. second integrated circuit 678 of FIG. respectively. a top 810. the top integrated circuit 674 be formed in a manner similar to the base integrated circuit of FIG. 6 and the inter-substrate 6. nal interconnect 680 of FIG. The second inter-substrate region side of the stack substrate 830 opposite the stack substrate 884 can include an inter-package standoff gap. The top inte include a base integrated circuit package 802. a top internal 806 and a base substrate top surface 808. can be mounted over the stack substrate 630. 6. The stack project over the base integrated circuit package 802. such as a . 9 in a fifth embodiment of the mounted over the stack substrate 830. or traces. 6. the inter-substrate region 656 of FIG. The integrated protrusion 837. mounted package 664. and the top integrated circuit connector 658 of FIG. adjacent the stack device 642 or the top integrated circuit 0162 The integrated circuit packaging system 800 can package 664. an active device. the top internal interconnect 676 of FIG. The stack substrate 830 can be designed 0. grated circuit package 864 can include a top Substrate 866. Such as a passive between the stack device 642 and the top integrated circuit device. The integrated circuit packaging system 800 can dispensing methods on a protruded interposer. 6. This configuration can allow the entirety of the top connectivity between electrical devices or packaging systems integrated circuit package 664 mounted over a portion of the that are connected to the stack substrate bottom surface 832 stack substrate 630 that is adjacent or next to another portion and the stack substrate top surface 834. the stack device 642 of FIG. The stack substrate protrusion 837 can overhang or the stack substrate aperture 636 formed thereon. The stack device 842 can be through the stack substrate aperture 636. except for the formation of the stack substrate 630 of FIG. a top second integrated circuit 878. the top second inter and the base underfill 624 of FIG. therein is shown a top view 0. a base internal interconnect 814. Referring now to FIG. respectively. the top 612 of FIG. The connector underfill 690 can be dispensed under the stack substrate 830. or a discrete component. beyond edges of the base integrated circuit package 802 or the 0151. and the top encapsulation 682 0157. 6. 6. 6. respectively. 0155 The base integrated circuit package 802 can include having a top substrate bottom surface 868 and a top substrate a base substrate 804. a top integrated circuit 874. Such as a pas sectional view of an integrated circuit packaging system 800 sive device. and the stack substrate top surface 834. 8. and an addition of another stack 0. 0166 The top substrate 866. and the and a base underfill 824. mounted over or attached to the stack substrate bottom sur 0152 The stack device 642 can beformed around or along face 832. such as an interposer. 6. substrate connector 858 can be formed in a manner similar to 6. 1. 6 having the stack substrate top surface 634 and 830. circuit 878. The top integrated circuit package 664 along a stack perimeter of the stack substrate 830. The base integrated circuit 812. the base internal interconnect 614 of FIG. between the stack substrate bottom surface 832 circuit package 664. 2011 top integrated circuit package 664 can have a configuration 0159. or a discrete component. The integrated circuit packaging system 800 can of FIG. ductive layers. include an inter-substrate region 856 and an inter-substrate 0154 The integrated circuit packaging system 800 can be connector 858. 6 and the base barrier 610 of FIG. of the stack substrate 630 that includes the stack substrate (0160 The stack substrate 830 can include a stack substrate aperture 636.

therein is shown a cross include a stack substrate 1030. a solder column.184 The stack substrate 1030 can include a stack sub tem. The connector underfill 890 can func 1002 can include a base barrier 1010 defined as a dam or a tion as a reinforcement layer in the inter-substrate region 856 structure formed to contain or prevent the underfill encapsu and the second inter-substrate region 884. Such as an the connector underfill 890 as two and two. such as a bond wire. to provide electrical connec nect 888 can be formed in a manner similar to the external tivity. a sub sectional view of an integrated circuit packaging system 1000 strate. to the integrated circuit packaging system 800 of FIG. a wirebond integrated circuit.US 2011/021043. a wirebond integrated circuit. each side of the stack substrate 830. or a conductive wire. an epoxy. such as a resin. 8 and 0185. The stack substrate 1030 can 0176 The integrated circuit packaging system 1000 can be designed in a singulated or Strip form for encapsulant represent a configuration of a packaging system that is similar dispensing. The external intercon layers. such as an interposer. an underfill. The base integrated circuit package 1002 can can be dispensed over or on a portion of the Stack Substrate top include a base integrated circuit 1012. which can include a pre-stacked package-on-package strate bottom surface 1032 and a stack substrate top surface (PoP) structure with an underfill encapsulant formed by bot 1034 on a side of the stack substrate 1030 opposite the stack tom side dispensing methods on a protruded interposer. or traces. on integrated circuit die. although any numbers of mounted over the base integrated circuit 1012. tem 1000 can represent a configuration of a packaging sys 0. conductive include an external interconnect 888. the base surface 834. providing protec lation from overflowing over sides of the base substrate 1004. interconnect 688 of FIG.9. encapsulating the inter-substrate connector 858 in the over the base substrate 1004. or the bottom surface 1006. 10. a film. a stud bump. 2011 solder ball. over the stack substrate top surface 834. The inte cal connectivity between electrical devices or packaging sys . or a chip. or a solder mask. encap surface 1008. tion for the inter-substrate connector 858 and the second (0179 The base barrier 1010 can be formed with an epoxy inter-substrate connector 886. 1. or a along a section line 10-10 of FIG. The base integrated circuit package 1002 can bottom surface 868 and the stack substrate top surface 834. Such as a die attach. or a molding circuit packaging system 800 can include the top integrated material. The integrated circuit packaging system 800 can internal interconnect 1014. or an strate connector 858 is attached or connected to the base epoxy. respectively. substrate bottom surface 1032. nector 886 can be attached or connected to the top substrate 0177. an interface module. or a printed wiring substrate.11 in a sixth embodiment of PCB. a ribbonbond wire. and the base second internal interconnect 1018. 6. 0169. or a chip. an organic or inorganic Substrate. a inter-substrate connector 886 is attached or connected to the ribbonbond wire. the second inter-substrate connector 886. attached or connected stack substrate 830 and the top substrate 866. The integrated circuit packaging sys integrated circuit package 1002. an internal Stacking module. The integrated circuit packaging system 800 can The base substrate 1004 can include bond sites. The stack substrate 1030 can be mounted over the base the present invention. the base integrated circuit 1012. to the base substrate bottom surface 1006 and the base inte 0172 For illustrative purposes. The base integrated circuit 0173 The stack device 842 can be attached to the stack package 1002 can include a base second internal interconnect substrate protrusion 837 or over the stack substrate bottom 1018. The stack substrate 1030 can include bond sites. The base integrated circuit package underfill encapsulant. The second inter-substrate con integrated circuit package 1002. grated circuit packaging system 1000 can include a base or a metallic alloy conductor. is inverted to allow the underfill encapsulant to be dispensed conductive layers. wiring layers. The base barrier 1010 (0171 The connector underfill 890 can be dispensed over can be mounted over or attached to the base substrate top or on a portion of the stack substrate protrusion 837. the cross-sectional view is grated circuit 1012. the base second integrated circuit include a portion of the connector underfill 890 dispensed 1016. The base integrated circuit package 1002 can the second inter-substrate connector 886 encapsulated with include a base second integrated circuit 1016. The base barrier 1010 can be formed along or sulating the second inter-substrate connector 886 in the sec around a base perimeter of the base substrate 1004. The base integrated circuit package 1002 can include substrate 804 and the stack substrate 830 or where the second a base internal interconnect 1014. or a conductive surface 832.178 The base substrate 1004 can include a base substrate 0170 The integrated circuit packaging system 800 can bottom surface 1006 and a base substrate top surface 1008 on include a connector underfill 890. a carrier. an adhesive. 0182. The base sec the inter-substrate connector 858 and the second inter-sub ond integrated circuit 1016 can be attached to the base inte strate connector 886 can be encapsulated with the connector grated circuit 1012 with an attach layer. ond inter-substrate region 884. Such as a die attach. 0. or an epoxy. a metal conductor. Such as an integrated surface 834 and filled through the stack substrate aperture circuit die. an adhesive. an encap a side of the base substrate 1004 opposite the base substrate Sulant. a film. shown with numbers of the inter-substrate connector 858 and 0181. respectively. a printed circuit board (PCB). The stack second device 846 can be attached to wire. The integrated an epoxy molding compound. The base integrated circuit package 1002 can 0. The connector underfill 890 0180.174 Referring now to FIG. to provide electri from the bottom side of the protruded interposer. mounted 836. area array around or near the stack perimeter. such as a laminated plastic or The second inter-substrate connector 886 can be formed in an ceramic Substrate. or traces. such as a bond wire. resin. a liquid encapsulant. underfill 890. therein is shown a top view include a base encapsulation 1026. attached or connected to the base substrate bottom the stack substrate top surface 834 or between a plurality of surface 1006 and the base second integrated circuit 1016. Such as a cover including of the integrated circuit packaging system 800. The base encapsulation 1026 can beformed over the circuit package 864 mounted over the stack Substrate top base substrate 1004.6 A1 Sep. 0183 The integrated circuit packaging system 1000 can 0175 Referring now to FIG. The base integrated circuit 1012 inter-substrate region 856. a photoresist. include a base substrate 1004. wiring layers. The connector underfill 890 can be can be attached to the base substrate bottom surface 1006 with filled to encapsulate joints or junctions where the inter-Sub an attach layer. an encapsulant.

encap metallic alloy conductor. dispensed in the substrate top surface 1070. alloy conductor. or a discrete component. an encap between the base substrate 1004 and the stack substrate 1030. The circuit 1074 can be attached or connected to the top substrate integrated circuit packaging system 1000 can include the top bottom surface 1068 with a top internal interconnect 1076. a printed circuitboard (PCB).6 A1 Sep. an organic or shown with numbers of the inter-substrate connector 1058 inorganic substrate. an 0197) The integrated circuit packaging system 1000 can active device. substrate bottom surface 1032. a stud bump. 1070 on a side of the top substrate 1066 opposite the top 0201 The stack device 1042 can be attached to the stack substrate bottom surface 1068. or near a 1070. a stud bump. such as include the external interconnect 1088 attached to the top an epoxy resin or any underfill resin material. such as a resin.195 The integrated circuit packaging system 1000 can The stack substrate aperture 1036 can be formed through the include a second inter-substrate region 1084 defined as spac stack substrate 1030. encapsulating the inter-substrate connector 1058 in the (0191 The inter-substrate connector 1058 can beformed in inter-substrate region 1056. The inter-substrate connector 1058 sulating the second inter-substrate connector 1086 in the sec can be formed in the inter-substrate region 1056. providing 0190. respectively. although any ductive layers. a liquid encapsulant. The top substrate 1066 can include a top sub inter-substrate connector 1086 can be encapsulated with the strate bottom surface 1068 and a top substrate top surface connector underfill 1090. mounted under the top substrate 1066 or over 0202 Referring now to FIG. The second inter-substrate con In other words. therein is shown a top the top substrate bottom surface 1068. or a metallic alloy conductor. strate aperture 1036 defined as a through slot or an opening. a metal conductor. top integrated circuit 1074 to protect the top internal inter 0186 The stack substrate 1030 can include a stack sub connect 1076. 11. such as a solder ball. conductor. respec 0193 The top substrate 1066 can include bond sites. a solder column. vide electrical connectivity to external systems. 2011 tems that are connected to the stack Substrate bottom Surface space between the top substrate bottom surface 1068 and the 1032 and the stack substrate top surface 1034. a metal strate top surface 1034. The external interconnect 1088 can be formed to pro center region of the stack substrate 1030. The stack substrate protrusion 1037 can over solder ball. the cross-sectional view is Such as a laminated plastic or ceramic Substrate. The inter-substrate substrate connector 1058 is attached or connected to the base connector 1058 can beformed adjacent the base barrier 1010. between the stack substrate bottom ing between the stack substrate 1030 and the top substrate surface 1032 and the stack substrate top surface 1034. a metal conductor. an epoxy. or a metallic alloy conductor. a solder column. or a metallic over or attached to the stack substrate bottom surface 1032. 1. on each side of the stack substrate 1030.US 2011/021043. The second inter-substrate region 1084 can include spacing between the stack substrate top surface 1034 and the 0187. con tively. a stack substrate 1030. strate protrusion 1037.192 The integrated circuit packaging system 1000 can second inter-substrate connector 1086 is attached or con include a top integrated circuit package 1064. 1068. a solder column. The integrated circuit packaging system 1000 can can outwardly laterally extend from the center of the stack include a second inter-substrate connector 1086. a solder column. 0. edges of the stack substrate 1030 can laterally nector 1086 can be attached or connected to the stack Sub extend beyond edges of the base integrated circuit package strate top surface 1034 and the top substrate bottom surface 1002 or the base Substrate 1004. include a stack device 1042. 1056 and the second inter-substrate region 1084. 1066. under. substrate 1004 and the stack substrate 1030 or where the 0. a stud bump. The top integrated view of the integrated circuit packaging system 1000. Such as a flip chip. Sulant. The top integrated 0203 The integrated circuit packaging system 1000 can circuit package 1064 can include a top underfill 1081. or a (0199 The connector underfill 1090 can be dispensed over or on a portion of the stack substrate protrusion 1037. The connector underfill 1090 can func the base substrate top surface 1008 and the stack substrate tion as a reinforcement layer in the inter-substrate region bottom surface 1032. such as a substrate 1030. The stack device 1042 can be 0194 The top integrated circuit package 1064 can include attached to the stack substrate 1030 between a plurality of the a top integrated circuit 1074. with the connector underfill 1090 as two and two. such as a solder ond inter-substrate connector 1086. a metal conductor. The connector underfill 1090 substrate connector 1058 can be attached or connected to the base substrate top surface 1008 and the stack substrate bottom can be dispensed over or on a portion of the Stack Substrate top Surface 1032. The inter ond inter-substrate region 1084. to provide electrical numbers of the inter-substrate connector 1058 and the second connectivity. surface 1034 and filled through the stack substrate aperture 1036. bumped chip. wiring layers. The integrated circuit packaging system 1000 can protection for the inter-substrate connector 1058 and the sec include an inter-substrate connector 1058. mounted under the include an external interconnect 1088. such as a passive device. an underfill. integrated circuit package 1064 mounted over the stack Sub Such as a solder ball. or the The inter-substrate region 1056 can include spacing between underfill encapsulant. The stack device 1042 can be mounted stud bump. The connector underfill 1090 can an area array around or along the base perimeter or a stack be filled to encapsulate joints or junctions where the inter perimeter of the stack substrate 1030. The stack substrate protrusion 1037 0196. 0189 The integrated circuit packaging system 1000 can 0198 The integrated circuit packaging system 1000 can include an inter-substrate region 1056 defined as spacing include a connector underfill 1090. The integrated circuit packaging . The second inter-substrate connector 1086 can be 0188 The integrated circuit packaging system 1000 can formed in an area array around or near the Stack perimeter. or a inter-substrate connector 1058. a die. hang or project over the base integrated circuit package 1002. ball. attached to the top Substrate top surface The stack device 1042 can be mounted over. a carrier. grated circuit package 1064 can include a top substrate 1066. or traces. or and the second inter-substrate connector 1086 encapsulated a printed wiring Substrate. The stack substrate 1030 can include a stack sub top substrate bottom surface 1068. 0200 For illustrative purposes. The top inte nected to the stack substrate 1030 and the top substrate 1066.

or traces. a Sub age 1264 can be substantially the same. the external interconnect 888 of FIG. the 1230 or a portion of the connector underfill 1290 can be base integrated circuit 812 of FIG. the base internal inter trimmed off or removed to maintain the overall footprint of connect 814 of FIG. 1230 can be substantially intersected by an extent of the 0211. sawing marks. portion of the stack substrate 1230 to be removed can include conductive layers. and include a base integrated circuit package 1202. 8. The top substrate 1266. connector 858 of FIG. 12. other removal tool dispensing. 8. a second inter FIG. 8. and a base underfill 1224. nector underfill 1290 removed. 1. respectively. a top internal system. the 0209. 8. after trim 876 of FIG. the stack substrate 1230 can include strate bottom surface 1232 and a stack substrate top surface an external Surface having characteristics of the portion of the 1234 on a side of the stack substrate 1230 opposite the stack stack substrate 1230 removed. widths of the base integrated circuit package 1202. 8. an outer edge of the stack substrate similar to the stack second device 846 of FIG. The integrated circuit strate. Sanding marks. the base internal interconnect 1214. 13 in a seventh embodiment 1274. The integrated circuit packaging grated circuit 1278. 2011 system 1000 can include a portion of the connector underfill interconnect 1276. a base formed in a manner similar to the second inter-substrate barrier 1210. or a physically processed surface. the top second internal interconnect system 1200 can represent a configuration of a packaging 1280. having a base substrate bottom interconnect 1288. and the base under 0215. 8. a base integrated circuit 1212. the structure of the integrated circuit packaging system 1200. the external include a base substrate 1204. of the present invention. The stack substrate 1230 can be mounted over the base ture. or a packaging system 1200 can have a straight profile in struc PCB. an interface module. respectively. the base barrier 810 of FIG. or a physically processed surface. the connector underfill 1290 can 0210. 1212. 8. AS Such. and the connector underfill 1290 can be surface 1206 and a base substrate top surface 1208. For example. other removal tool surface 1232 and the stack substrate top surface 1234. the base integrated circuit connector underfill 890 of FIG. a connector underfill 1290. a portion of the stack substrate substrate 804 of FIG. The top substrate connector 1258 can beformed in a manner similar to view is shown with the integrated circuit packaging system the inter-substrate region 856 of FIG. between the stack substrate bottom marks. an external interconnect 1288. sawing marks. the top second internal interconnect 880 of FIG. 0219 Referring now to FIG. 8. to provide electri an excessive edge or a protruded portion of the Stack Substrate cal connectivity between electrical devices or packaging sys 1230. respectively. the top integrated circuit along a section line 12-12 of FIG. The stack substrate 1230 can include a stack sub trimmed off or removed. the top internal interconnect 1276. The second inter-substrate region 0206. 15 in an eighth embodiment grated circuit package 1264 can include a top Substrate 1266. the top (PoP) structure with an underfill encapsulant formed by top integrated circuit 874 of FIG. Sanding marks. 13. include an inter-substrate region 1256 and an inter-substrate 0218. and the top encapsulation 1282 can be formed in a system. and the base underfill 824 of FIG. the top second integrated circuit 878 of FIG. 8. and the top integrated circuit pack include a stack Substrate 1230.US 2011/021043. second internal interconnect 1280. Such as an interposer. The integrated circuit packaging system 1200 can connector underfill 1290. 8. The marks. and the strate 1204. the second inter-substrate connector 886 interconnect 1214. a top 1090 dispensed over the stack substrate top surface 1034. After the encapsulation process of the connector fill 1224 can be formed in a manner similar to the base underfill 1290 is completed. be similar to the integrated circuit packaging system 800 of 0214. except for the formation of the stack substrate 830 of include a second inter-substrate region 1284. the top internal interconnect side dispensing methods on a protruded interposer. The inter-substrate region 1256 and the inter view of the integrated circuit packaging system 1200. a top integrated circuit 1274. which can include a pre-stacked package-on-package . therein is shown a cross 1282. 0216. 8. The integrated circuit packaging system 1200 can substrate connector 1286. 0207. 8. and the top 0205 The integrated circuit packaging system 1200 can encapsulation 882 of FIG. trimmed off or removed. The integrated circuit packaging having a top substrate bottom surface 1268 and a top substrate system 1400 can represent a configuration of a packaging top surface 1270. the top second inte of the present invention. The integrated circuit packaging system 1200 can sectional view of an integrated circuit packaging system 1400 include a top integrated circuit package 1264. The stack substrate 1230 can tion of the stack substrate 1230 removed can include grinding be designed in a singulated or Strip form for encapsulant marks. The integrated circuit packaging system 1200 can FIG. marks. 8. 14. The characteristics of the The stack substrate aperture 1236 can be formed through the connector underfill 1290 removed can include grinding stack substrate 1230. With the portion of integrated circuit packaging system 1200 can optionally the stack substrate 1230 and the portion of the connector include a stack device 1242 that can be formed in a manner underfill 1290 removed. After the portion of the connector underfill 1290 is 1232 and the stack substrate top surface 1234. The integrated circuit packaging system 1200 can the stack substrate 1230. and a top encapsulation 0204 Referring now to FIG. wiring layers. 8. tems that are connected to the stack Substrate bottom Surface 0217. The stack substrate 1230 can include bond sites. sectional view of an integrated circuit packaging system 1200 0213. 8. which can include a pre-stacked package-on-package manner similar to the top substrate 866 of FIG. The stack substrate 1230 can include a stack sub include an external Surface having characteristics of the con strate aperture 1236 defined as a through slot or an opening. The base integrated circuit package 1202 can 1284. therein is shown a top connector 1258. the second inter-substrate connector 1286. 8. 8. a base internal region 884 of FIG. an internal Stacking module. Referring now to FIG. integrated circuit package 1202. respectively. therein is shown a cross 0212. a top second integrated circuit 1278. ming off the excessive edges of the protruded interposer. After the portion of the stack substrate 1230 is 0208. the base barrier 1210.6 A1 Sep. 8.8. The top inte along a section line 14-14 of FIG. The characteristics of the por substrate bottom surface 1232. 8 and the inter-substrate 1200 having the top integrated circuit package 1264. The base sub of FIG.

The stack substrate the base barrier in a block 1610. 1. 1416. 8. the top second internal interconnect grated circuit 1412 with an attach layer. cost-effective. and mounted over the base second integrated circuit 1416. a wirebond integrated circuit. The base integrated circuit package 1402 can second internal interconnect 1480. 8. a top 0222. such as a bond wire. The base integrated circuit package 1402 can view of the integrated circuit packaging system 1400. integrated circuit die. respectively. a ribbonbond wire. a top second integrated circuit 1478. Such as an 1482. a base integrated circuit 1412. or of FIG. or a chip. 8. a film. attached or connected to the base substrate connector underfill 890 of FIG. therein is shown a top 0224. 8. except that the stack Substrate having a stack Substrate aperture with the stack Substrate 1430 can include a stack Substrate open region stack Substrate having an inter-substrate connector thereon in 1438 defined as a cavity. and the connector underfill 1490 can be die attach. overflow of the connector underfill prevented by in the center of the stack substrate 1430. a stack substrate top surface 1434. the second inter-substrate connector 886 interconnect 1422. The a connector underfill 1490. 2011 (PoP) structure with an underfill encapsulant formed by bot thickness of the base integrated circuit 1412. a top internal interconnect 1476. or a conductive 876 of FIG. and a top encapsulation include a base second integrated circuit 1416. The include a base encapsulation 1426. the similar to the stack substrate 830 of FIG. attached or connected to the base substrate top surface the top second internal interconnect 880 of FIG. such as a bond wire. The base integrated circuit manner similar to the top substrate 866 of FIG. 8. The FIG. The top inte internal interconnect 1414 can be formed in a manner similar to the base substrate 804 of FIG. top surface 1470. the external interconnect 888 of FIG. The integrated circuit packaging system 1400 can 0221) The base integrated circuit package 1402 can include an inter-substrate region 1456 and an inter-substrate include a base substrate 1404. and the a conductive wire. FIG. a hole.8. an external interconnect 1488. base integrated circuit package 1402. The integrated circuit packaging system 1400 can include a base third integrated circuit 1420. a wirebond integrated circuit. 1480. wire. 8. The integrated circuit packaging system 1400 can barrier 1410. device. 8.US 2011/021043. the external second integrated circuit 1416 with an attach layer. or a molding integrated circuit package 1464 mounted over the stack Sub material. or an epoxy. a window. The resulting method. and the base include a top integrated circuit package 1464. the top integrated circuit mounted over the base integrated circuit 1412. 15. a stack the base substrate in a block 1604. mold cap thickness of the base encapsulation 1426 or flip chip product. 0232 Referring now to FIG. the second inter-substrate connector 1486. 8. encapsulation 882 of FIG. 8. The method 1600 includes: providing a base sub include a stack substrate 1430. respectively. The base inte formed in a manner similar to the second inter-substrate grated circuit package 1402 can include a base third internal region 884 of FIG. 0230. 8. the base integrated circuit 1412. The stack substrate aperture 1436 can be formed be similar to the integrated circuit packaging system 800 of adjacent or around the stack substrate open region 1438. 16. or the central a block 1608. substrate connector 1486. 0228. a film. 8. process. The integrated circuit packaging system 1400 can invention. an encapsulant. or the base third integrated circuit central opening. and/or system is straightforward. or a chip. having a base substrate bottom connector 1458. mounting a stack substrate over the base substrate. Such as a die attach. the base integrated circuit 812 of FIG. 8. having a stack substrate bot strate in a block 1602. The stack substrate open region 1438 can beformed connector. and a base inter connector 858 of FIG. the base 0233 Referring now to FIG. 8. 8. attaching a base barrier on substrate aperture 1436. except for the formation of the base integrated circuit top or an upper portion of the base integrated circuit package package 802 of FIG. Such as a cover including integrated circuit packaging system 1400 can include the top an epoxy molding compound. 1420. The base substrate 1404. an adhesive. a base the inter-substrate region 856 of FIG. The top substrate 1466. a top integrated circuit 1474. the base tem 1400 can include a portion of the connector underfill internal interconnect 1414. and the top encapsulation 1482 can be formed in a an adhesive. 0220. or an epoxy. and the top 1408 and the base second integrated circuit 1416. respectively. The integrated circuit packaging system 1400 can 0227. apparatus. the base second integrated circuit 1490 dispensed over the stack substrate top surface 1434. The integrated circuit packaging sys base substrate 1404. 8. The base sec 1474. and a stack substrate protrusion the base substrate adjacent a base perimeter thereof in a block 1437. the base 0229. 8 and the stack substrate 830 of FIG. 8 and the inter-substrate barrier 1410. top surface 1408 and the base third integrated circuit 1420. 1402 can be positioned in the stack Substrate open region The integrated circuit packaging system 1400 can include a 1438. 8. open region 1438 can beformed in order to create spacing for 0234. the base second internal interconnect 1418. Such as an inte include a second inter-substrate region 1484. the top internal interconnect 1476. the base barrier 810 of grated circuit package 1464 can include a top Substrate 1466. the top second integrated circuit 878 of FIG. The second inter-substrate region base third integrated circuit 1420 can be attached to the base 1484. nal interconnect 1414. The stack substrate 1430 can be formed in a manner 1606. a second inter grated circuit die. a ribbonbond wire. the top package 1402 can include a base second internal interconnect integrated circuit 874 of FIG. The base encapsulation 1426 can beformed over the strate top surface 1434. packaging system in a further embodiment of the present 0225.8. the top second inte ond integrated circuit 1416 can be attached to the base inte grated circuit 1478. the base second tom side dispensing methods on a protruded interposer with a integrated circuit 1416. the stack Substrate aperture encapsulating the inter-substrate 0226. the base integrated circuit 1412. The inter-substrate region 1456 and the inter substrate connector 1458 can beformed in a manner similar to surface 1406 and a base substrate top surface 1408. the top internal interconnect 1418. attaching a base integrated circuit on tom surface 1432. 0223) The base integrated circuit package 1402 can 0231.6 A1 Sep. and the base third internal inter chart of a method 1600 of manufacture of an integrated circuit connect 1422. respectively. such as a interconnect 1488. . and the base having a top substrate bottom surface 1468 and a top substrate internal interconnect 814 of FIG. and dispensing a connector underfill through opening. therein is shown a flow third integrated circuit 1420.

6 A1 Sep. and variations that fall within the scope of the aperture. fill. tor. dispensing a connector underfill through the stack Sub 12. and increasing perfor Substrate having a stack Substrate protrusion. dispensing the connector underfill includes dispensing the 0236. entirety of the top integrated circuit package adjacent the 4. What is claimed is: 11. The method as claimed in claim 1 wherein dispensing stack Substrate aperture. underfill over a portion of the stack substrate protrusion. it is to be understood that many connector underfill. The method as claimed in claim 1 further comprising integrated circuit. A method of manufacture of an integrated circuit pack 18. The system as claimed in claim 16 wherein the stack base perimeter thereof. and . the entirety of the top integrated circuit package adja Substrate includes a stack Substrate protrusion. base barrier. it is intended to embrace all such alternatives. simplifying systems. The method as claimed in claim 6 wherein attaching the shown in the accompanying drawings are to be interpreted in base integrated circuit on the base Substrate includes attach an illustrative and non-limiting sense. and variations will be apparent to 9. and stack substrate having a stack substrate aperture with the a connector underfill through the stack Substrate aperture stack Substrate having an inter-substrate connector encapsulating the inter-substrate connector. ing a flip chip on the base Substrate. These and other valuable aspects of the present connector underfill over a portion of the stack substrate invention consequently further the State of the technology to protrusion. thereon and the inter-substrate connector between the c c c c c base barrier and the base integrated circuit. accurate. The method as claimed in claim 1 wherein mounting the tor underfill is adjacent the base barrier. the stack Substrate aperture. The system as claimed in claim 11 further comprising the connector underfill includes dispensing the connector a top integrated circuit package over the stack Substrate. eter thereof. The system as claimed in claim 16 wherein the stack strate. Strate. substantially intersected by an extent of the connector under attaching a base integrated circuit on the base Substrate. an outer edge of the stack Substrate Sub stantially intersected by an extent of the connector underfill. modifications. The system as claimed in claim 11 wherein the inter underfill between the base substrate and the stack substrate. included claims. the having an inter-substrate connector thereon. base barrier. having a stack Substrate aperture with the stack Substrate mounting a stack Substrate over the base Substrate. The system as claimed in claim 11 wherein the connec tor underfill is between the base substrate and the stack Sub a stack barrier adjacent a stack perimeter thereof. 0235 Another important aspect of the present invention is 7. and the connector underfill prevented by the base barrier. highly versatile.US 2011/021043. and dispensing a connector underfill through the stack Sub effective. the connector cent the stack Substrate aperture. and economical manufacturing. alternatives. a base barrier on the base Substrate adjacent a base perim attaching a base integrated circuit on the base Substrate. efficient. The method as claimed in claim 1 wherein dispensing 15. A method of manufacture of an integrated circuit pack a base Substrate. the underfill adjacent the base barrier. the stack substrate base perimeter thereof. The system as claimed in claim 11 wherein the connec 2. 3. sensitive. providing a base Substrate. and can be implemented by adapting known com strate aperture encapsulating the inter-substrate connec ponents for ready. overflow of thereon. stack Substrate having a stack Substrate aperture with the 20. The system as claimed in claim 16 wherein the base stack Substrate having an inter-substrate connector integrated circuit includes a flip chip on the base Substrate. stack Substrate includes mounting the stack Substrate having 14. a stack Substrate open region adjacent the stack Substrate modifications. attaching a base barrier on the base Substrate adjacent a 19. at least the next level. The system as claimed in claim 16 wherein the connec aging System comprising: tor underfill includes an outer edge of the stack substrate providing a base Substrate. 2011 uncomplicated. Substrate includes a stack Substrate open region adjacent the mounting a stack Substrate over the base Substrate. The method as claimed in claim 6 wherein mounting the those skilled in the art in light of the aforegoing description. stack Substrate includes mounting the stack Substrate having Accordingly. The method as claimed in claim 6 wherein: that it valuably supports and services the historical trend of mounting the Stack Substrate includes mounting the stack reducing costs. 1. mounting a top integrated circuit package over the Stack Sub 17. aging System comprising: a base integrated circuit on the base Substrate. An integrated circuit packaging system comprising: 1. All matters hithertofore set forth herein or 10. overflow of the connector underfill prevented by the adjacent a stack perimeter thereof. and aCC. and utilization. the connector underfill includes dispensing the connector 16. 13. 6. The system as claimed in claim 11 wherein the stack strate aperture encapsulating the inter-substrate connec Substrate includes the stack Substrate having a stack barrier tor. attaching a base barrier on the base Substrate adjacent a a stack substrate over the base substrate. substrate connector is between the base barrier and the base 5. overflow of the connector underfill prevented by the application. The method as claimed in claim 6 further comprising 0237 While the invention has been described in conjunc removing a portion of the Stack Substrate and a portion of the tion with a specific best mode. 8.