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ICSP2008 Proceedings


S.A. Hari Prasad 1 B.S.Kariyappa 1 Dr R.Nagaraj 2 Commander S.K.Thakur 3
Department of Electronics & Communication Engineering, R.V. College of Engineering,
Bangalore-560059, India
Director, Center for Cognitive Technologies,R.V.C.E. Campus
Bangalore-560059, India
Deputy Director, Naval Research Board, Defence Research Development Organization,
New-Delhi, India

ABSTRACT overcome if switching patterns are generated

Several techniques have been developed to control by executing simple control algorithms [3]. In
Alternating Current (AC) power. In this paper we spite of using simple control algorithms,
put forward, a novel technique to design and sometimes throughput delay may be
implement a single phase PWM inverter using substantial. With the advent of advanced
simple 8051 microcontroller rather than using microcontrollers and DSP [Digital signal
Digital Signal Processor (DSP) controllers [6].
processor] controllers[6], with many advanced
The main features of 8051 based PWM inverter are
simpler design, low cost, maximum range of features like inbuilt PWM generator, event
voltage control and compact in size. The designed managers, time capture unit, dead time delay
PWM inverter is tested on various AC loads like generators, watch dog timers along with high
AC motor and intensity control of incandescent clock frequency, the limitation of speed,
lamp in a closed loop environment. associated with microcontroller based PWM
inverters[7] can be discarded to some extent.
Keywords: Pulse Width Modulation, Micro
Controller, Single phase PWM inverter, Gate This paper presents a novel technique of
Signals single-phase AC [alternating current] voltage
control, using 8051 microcontroller based
1. INTRODUCTION PWM inverter. The main aim of this work is to
The pulse width inverters can be broadly design a simple low cost AC voltage controller
classified as, Analog bridge PWM inverter [1] used to control AC loads which doesn’t
and Digital bridge PWM inverters [2] Analog demand very high precisions. .
based PWM inverter controller provides
excellent control, in the sense, the level of 2. PWM BRIDGE INVERTER REVIEW
inverter output voltage can be adjusted in a
continuous range and the throughput delay is Inverters can be classified as single-phase and
negligible, but the disadvantages associated three phase inverters [4] and they can be
with Analog based PWM inverters are: further classified as Voltage fed inverter
[VSI.] in which input voltage remains
Analog component output characteristics constant, and a current fed converter [CFI] in
changes with the temperature and time. They which input current remains constant and
are prone to external disturbances. Analog variable DC[direct current] linked inverter in
controller circuitry is complex and bulky. which input voltage is controllable. Figure–1
They lag, the advantage of shows single phase bridge inverter which uses
reprogrammablility, hence they are not MOSFET switches [4]. Even though MOSFET
flexible. Microcontroller based PWM inverter switches have high ON state resistance and
controller on the other hand makes the conduction losses [5], in this paper MOSFET’s
controller free from disturbances and drift, but are used because of the following reasons.
the performance is not very much high due to MOSFET being a voltage controlled device, it
its speed limitation, however to minimize can be driven directly from CMOS or
throughput delay, some microcontroller based TTL logic. The gate drive current required is
PWM inverters, retrieves switching patterns very low [5].
directly from memory so that calculation can
be minimized, but at the same time demands
more memory. This limitation can be
978-1-4244-2179-4/08/$25.00 ©2008 IEEE

Single-phase bridge inverter is made up of 4 which four keys are accepted. The four keys
choppers. The working principle can be which are accepted is combined to form
explained as follows. When MOSFET Q1 and external memory address, in which digital
Q2 conduct simultaneously, voltage Vs equivalent of speed is stored in that location.
appears across the load. When Q3 and Q4 This method doesn’t need any program
conduct simultaneously, voltage –Vs appears execution to convert the entered speed in RPM
across the load. Diodes D1-D4 is used to into its digital equivalent which saves time.
overcome the effect of back emf in case of Alternatively digital data equivalent of RPM
inductive load. Diode D1 and D2 are called can be directly entered, provided a conversion
feedback diodes, because when they conduct chart is available [external look-up table]. This
the energy is feedback to the DC source. The technique will save some more time, since
RMS output voltage is given by communication with memory can be avoided.
Vo = Vs p / Π where P is pulse width.
4.2 ADC INTERFACING: The sensor O/P
which senses the speed of the motor/intensity
3. CONTROLLER BLOCK DIAGRAM varies from zero to five volts, whenever speed
varies from zero to maximum RPM
The Microcontroller based bridge PWM respectively. In order to convert this analog
inverter is as shown in Figure-2. The speed in voltage to digital data an 8-bit ADC is used,
RPM [Rotation per Minute] is entered through whose resolution is 1/28 . This means a
the keyboard and corresponding to the key minimum of 19.5 mv change in voltage
pressed, digital equivalent of that RPM is (corresponding change in RPM) is required to
stored in memory. change the digital state of ADC.

Through speed sensor, speed of the AC motor The variation in speed which produces voltage
is sensed and the analog output given by the changes within 19.5 mv doesn’t produce any
sensor is converted to digital data. change in the digital O/P of the ADC, this
limits the accuracy of the application.
Using 8051 microcontroller ports, the digital
data is accepted and is compared with required 4.3 PWM GENERATION: There is no
speed’s digital data. Proportional Algorithm is inbuilt PWM generator in 8051
used to adjust the duty cycle of the PWM microcontroller. It is implemented using ‘A’
signal in accordance with the error. The register and any other register (R0-R7).
generated PWM signal is used to generate two A count (ON period time) is loaded onto one
gate signals using interrupts required for of the GPR (General purpose register),which
bridge inverter circuit. Gate signals are passed can be called as Duty cycle register and
through gate driver circuit to boost up the gate accumulator is loaded with zero, then ‘A’
signal so that it can drive the MOSFET register is incremented in steps of one and
switches of bridge inverter to the ON state. been compared with duty cycle register.
User can change the speed at any instant of
time in accordance to his requirements. Many If the ‘A’ contents are less than duty cycle
additional features can be further added like register, high level is maintained at port line
sensing the temperature of room and P1.1. When ‘A’ is higher than duty cycle
automatically controlling either the speed of register content a low level is maintained on
the fan or the level of air conditioning port line. The other technique is that, the timer
required. can be used as counter by applying clock
pulses externally and comparing the count in
4. CONTROLLER DESIGN counter with ‘A’ register(duty cycle register),
but it requires external clock source, since
The controller implementation can be 8051 doesn’t have any clock out pin.The
organized under 4 sections as: maximum frequency of PWM is limited to 4
KHz by keeping the maximum time period
4.1 KEYPAD INTERFACE: A 4x4 keypad equal to 256 microseconds but this can be
is interface with 8051 microcontroller, through changed. The AC signal output generated by

PWM bridge inverter depends on the PWM performance of application is tested on various
signal frequency generated. The duty cycle of A.C loads and the plots of the same are as
PWM is varied in accordance with error shown in Figure-3. The design shows good
signal. The error signal is generated by results for the load values of 50 ohm and 100
comparing the required speed with accepted mH/ 10mH. A simple PWM technique is used
digital equivalent speed divided by two when rather than using the most often used
the required speed value is less than the sinusoidal PWM technique (For Single-phase
accepted one, duty cycle register value and inverters) which increases software and
accepted value is decremented by one and this hardware complexity. Also it avoids the usage
process is repeated till accepted value is equal of dead time delay generators, since the
to the required speeds digital value ,when the required gate turn on delay is generated
required speed value is more than the accepted through interrupt. With small modifications
one, duty cycle register values and accepted the same work can be used to automatically
value is incremented by one and this process control light intensity, temperature etc., and
is repeated till accepted value is equal to the the accuracy can be improved further by using
required speed digital values. The frequency high resolution ADCs and the delay involved
can be decreased by introducing proper delay in the software can be overcomed using higher
so that the wave forms takes more time to versions of controllers.
attain the limited period of 256 microseconds.
controlled PWM signal generated itself will be [1]H.Parasuram and B.Ramaswami, “A three
one set of gate signal(g1,g2)and other set of phase sine wave reference generator for
gate signals (g3,g4)is generated as follows. The thyristorized motor controllers” IEEE
controlled PWM signal generated is given to transaction, Industrial electronics, vol IE-23,pp
the external interrupts ,which is initialized as 270-276,August 1976.
falling edge sensitive interrupt type .When [2]J.M.D.Murphy,L.S.Howard & R.G.Hoft, “
falling edge occurs, it causes interrupts, Microprocessor control of PWM inverter
program execution starts from the interrupts induction motor drive”, in Rec of the 1979
service routine meant for that particular IEEE power electron specialist conf.,pp344-
external interrupt. 348.
In the interrupt service routine, delay is created [3]G.S.Buja& P.Fiorini, “Microcomputer
equal to time, given by; 7FH minus duty cycle control of PWM inverters, “IEEE transaction,
register content, after the delay, the port line is Industrial electronics, vol IE-29, pp 212-216,
made high and is retained high for the time August 1982.
duration of duty cycle register content value. [4]Muhammad .H. Rashid, power electronics
So generated gate signal (vg1 vg2, vg3, vg4) are circuits, devices and applications, 3rd edition,
boosted to a sufficient voltage level by GATE Prentice-Hall of India, Private limited, New-
drive circuitry, such that they are capable of Delhi, 2004.
driving MOSFET’S to the ON state, when the [5]V.Jagannathan, Introduction to Power
gate signals are high. electronics ,PrenticeHall of India, Private
For this again a transistor switch (with limited, New-Delhi, 2006.
inverted gate signals as input) is made used. [6]G.S.Buja & Paolo.De.Nardi, “Application
The same DC supply, which is used for of a Signal processor in PWM inverter
inverter can be used to drive transistor by control,IEEE transaction, Industrial
reducing the DC level using voltage dividers. electronics, Vol IE-32, No-1, February 1985.
The other technique is to use opto-isolators. [7]Peng,Yong Kang and others, “ A Novel
Both of the above technique avoids more PWM technique in Digital control” IEEE
usage of DC sources. transaction, Industrial Electronics,Vol
54,February 2007.
The designed application is tested by
designing 60V MOSFET bridge inverter. The





Fig.1 Single phase Inverter

Fig.2. Block diagram of controller

140 theoritical 120

120 WOF L=100mH,R=50ȍ 100

100 WF


40 Theoritical
20 20 Practical
0 0
50.05 150.15 250.25 350.35 Frequency Hz 0 10% 20% 30% 40% 50%

Duty Cycle

WOF L=100 μH,R=50 ȍ

WF L=100 μH,R=50 80

80 ȍ,C=1400 μF


60 40 Theoritical


20 0 10 % 20% 30% 40% 50%

Duty Cycle
50.05 150.15 250.25 350.35 Frequency Hz

Fig.3. Response for Various loads with corresponding duty cycles