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# Accurate Power-Loss Estimation for Continuous-Current-

## Conduction-Mode Synchronous Buck Converters

1
Chia-Hsing Li, 1Yu-Kang Lo, Member, IEEE, 1Huang-Jen Chiu, Senior Member, IEEE
1
Dept. of Electronic Engineering, National Taiwan University of Science and Technology, Taiwan1
2
Tung Yen Chen
2
Dept. of Electrical Engineering, Chung Yuan Christian University

Abstract-- This paper presents an accurate power-loss II. SWITCHING LOSS ANALYSIS
estimation method for continuous-current-conduction-mode The topology of synchronous Buck converter is shown
synchronous Buck converters. Realistic analysis for switching in Fig. 2, where Vin is the input DC voltage, D1 and D2 are
losses on power MOSFET has been investigated.. body diodes, Cout is output capacitor, R is load, L is filter
Considering the thermal characteristic, total power loss on inductor, Rdriver is equivalent resistance of gate driver resister.
power MOSFETs is calculated to predict the maximum The three inter-electrode capacitances Coss, Crss and Cgs is
junction temperature. Theoretical analysis and experimental parasitical capacitor between the drain-source, gate-drain and
results are shown and compared to verify the validity of the gate-source of the power MOSFET. Qg(th),Qgs,Qgd, Qg,Vt and
proposed method. Vmiller can be observed from the Gate Charge characteristic
curves shown in MOSFET datasheet. The theoretical
Index Terms—Power-loss Estimation, Synchronous Buck, waveforms of the switching waveforms of power MOSFET is
Switching Loss, Junction Temperature show in Fig. 3. The switching cycle can be consists of 10
periods (t0-t10). The operation principle of the instantaneous
I. INTRODUCTION switching characteristics can be explained in detail. In order
The switching loss on power MOSFETs becomes
to analyze simply, there are some assumptions as listed
dominant for the total power loss of a below.
continuous-current-conduction-mode (CCM) synchronous
Buck converter as the switching frequencies being increased  Input voltage and driver voltage are constant.
to reduce the size of passive components. There are some  Diode conduction voltages Vd is constant.
problems to estimate the switching losses of synchronous  The gate is being driven with a constant current.
CCM Buck converters. The power MOSFET is typically
assumed as an ideal switch only has two operation modes: on
and off. Instantaneous characteristics of the switches process
are ignored. A simple piece-wise linear model is also usually
adopted to analyze the switching characteristics of the power
MOSFET . It's not accurate without considering the
MOSFET's parasitic. In the literatures -, a complex
method is proposed to estimate the switching loss with the
consideration of parasitic capacitances. A simple yet
reasonably accurate method of estimating switching losses
based on MOSFET’s datasheet information is highly
desirable. Fig.1. shows the switching transient waveforms. In
this paper, a new method for accurate power loss estimation
is proposed with thermal resistance considerations.

## State 1: t0 < t < t1

Referring to Fig. 4(a), the switching interval begins when
the high-side MOSFET (Ron(U)) driver turns on and begins to
supply current to charge Qg(th), high-side MOSFET still turn
off. Inductor current (IL-) flows into low-side MOSEFT
(Ron(L))’s body diode D2 until Vgs1 arrive Vt therefore power
loss Pstage1 as below.
Fig.1. Switching transient waveforms
Therefore the switching interval power loss of Pstage2 as
Vo + I out × Ron( L ) below.
D= (1)
Vin − I load × Ron(U ) + I out × Ron( L ) Qgs1 − Qg1( th )
t2 − t1 = (7)
(Vin − I out × Ron(U ) − Vout ) × D × fs I ch arg e _ H
∆iL = (2)
L Pstage2_1 = 1 × (Vin + Vd ) × I L − × (t2 − t1 ) × f s (8)
2
∆iL 1
I L− = I load − (3) Pstage2_2 = × V × I × (t2 − t1 ) × f s (9)
2 2 d L−
VDRIVER _ H − Vt1 Pstage2 = Pstage2_1 + Pstage2_2 (10)
Ich arg e _ H = (4)
RDRIVER _ H + Rg1
Qg1(th )
t 1 −t 0 = (5)
I ch arg e _ H
Pstage1 = 1 × Vd × I L − × (t 1 −t0 ) × f s (6)
2
State 2: t1 < t < t2
As shown in Fig. 4(b), high-side MOSFET channel
current of Ids1 increases linearly form zero to IL, Meanwhile
Ids2 decreases linearly form IL to zero, then into stage3.

vGS1

vth
t

vGS2

IDS1

t
VDS1

IDS2

VDS2

t
IL

t
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t0 t1 t2
Ts
Qg

Qgs Qgd
vGS1
Qg(th)
Vmiller vGS1 Vmiller
Vt
Vt

## VDS1 Switching losses

Switching losses
ILX
IDS1 ILX
section

t0 t1 t2 t3 t4 t5
Fig.4. Switching paths of 4(a), 4(b), 4(c), 4(d),4(e), 4(f),
Fig. 3 Theoretical waveforms of the switching waveforms 4(g) and 4(h).
State 3: t2 < t < t3 loss of Pstage6 as below.
As shown in Fig. 4(c), High gate voltage Vgs1 source to Pstage6 = Vdiode × I L + × (t 6 −t5 ) × f s (22)
Vmiller, Crss2 and Coss2 through Vin start to charge energy,
subsequently Vds2 voltage increases linearly from zero to Vin,
State 7: t6 < t < t7
meanwhile Crss1 and Coss1 start to discharge energy through
Referring to Fig. 4(g), Low-gate voltage of Vgs2 source
high-side MOSFET channel, subsequently Vds1 voltage
to Vt2 , Low-side MOSFET ’s channel start to share current of
decreases linearly from Vin close to zero, otherwise the
inductor current until Vgs1 sink to Vmiller2 into stage 8.
MOSFET contains an integrated body diode which cause the
Therefore power loss of Pstage7 as below.
body diode’s reverse recovery charge Qrr, the Ids1
instantaneous increases most of switching loss is caused at V −V
I ch arg e _ L = DRIVER _ L t 2 (23)
this moment. Therefore the switching interval power loss of RDRIVER _ L + Rg 2
Pstage3 as below.
Qgd 2
Pcharge = 1 × (Coss 2 + Crss 2 ) × Vin 2 × f s (11) t 7 −t6 = (24)
2 I ch arg e _ L

## Pdischarge = 1 × (Coss1 + Crss1 ) × Vin 2 × f s (12) Pstage7 = 1 × Vdiode × I L + × (t 7 −t6 ) × f s (25)

2 2
PQrr = 1 × Qrr × Vin × f s (13) State 8: t7 < t < t8
2
Qgd 1 Referring to Fig. 4(g), in the interval low-side MOSFET
t3 − t 2 = (14) have turned on complete. Two kind of loss have to consider,
I ch arg e _ H one is gate charging loss Pgate-L the other is low-side
MOSFET Ron(L) conduction loss PMOS-L. In this section just
Pstag3_1 = 1 × Vin × I L − × (t 3 − t 2 ) × f s (15) talk about switching loss about the conduction loss in section
2
Pstage3 = PCharge + Pdischarge + Pstag3_1 + PQrr (16) Ш will be discussed. Power loss of Pstage8 as below
State 4: t3 < t < t4 Pstage8 = 1 × Qg 2 × VDRIVER _ L × f s (26)
2
Referring to Fig. 4(d), in the interval high-side
MOSFET have turned on complete. Two kind of loss have to State 9: t8 < t < t9
consider, one is gate charging loss Pgate-H the other is Referring to Fig. 4(h), low gate voltage Vgs2 sink to
high-side MOSFET Ron(U) conduction loss PMOS-H. In this Vmiller2. Low-side MOSFET’s channel current start to decrease,
section just talk about switching loss about the conduction until Vgs2 sink to Vt2 into stage 10.Therefore the switching
loss in section Ш will be discussed. Power loss of Pstage4 as interval power loss of Pstage9 as below
below V − Vt1
Pstage4 = 1 × Qg1 × VDRIVER _ H × f s (17) I sin k _ L = DRIVER _ H (27)
2 Rsin k _ H + Rg1
Qgd 2
State 5: t4 < t < t5 t 9 −t8 = (28)
Referring to Fig. 4(e), High gate voltage Vgs1 sink to I sin k _ L
Vmiller1 , Crss2 and Coss2 start to discharge energy, subsequently
Vds2 voltage decreases linearly from Vin to zero, meanwhile Pstage9 = 1 × Vin × I L − × (t 9 −t8 ) × f s (29)
2
Crss1 and Coss1 start to charge energy, subsequently Vds1
voltage increases linearly from zero to Vin. Until Vgs1 sink to State10: t9< t < t10
Vt1 into stage 6.Therefore the switching interval power loss of Referring to Fig. 4(h), high and low side’s gate driver
Pstage5 as below turn off which means dead-time specifically specified in most
∆iL buck-control datasheets, Inductor current (IL-) flows into
I L + = I load + (18) low-side MOSEFT (Ron(L))’s body diode D2 therefore power
2 loss of Pstage10 as below.
VDRIVER _ H − Vt1 Pstage10 = Vdiode × I L − × (t10 − t9 ) × f s (30)
I sin k _ H = (19)
Rsin k _ H + Rg 1 Base on Synchronous CCM Buck switching loss
Qgd 1 analysis which can classify as below lists.Pstage1, Pstage2 and
t 5 −t4 = (20) Pstage3 can be classified to high-side MOSFET switching loss
I sin k _ H of turn on. Pstage4 can be classified to high-side MOSFET gate
charging loss. Pstage5 can be classified to high-side MOSFET
Pstage5 = 1 × 1 × Vin × I L + × (t 5 −t4 ) × f s (21) switching loss of turn off. Pstage6 and Pstage10 can be classified
2 2
State 6: t5 < t < t6 can be classified low-side MOSFET switching loss of turn on.
Referring to Fig. 4(f), high and low side’s gate driver Pstage8 can be classified to low-side MOSFET gate charging
turn off which means dead-time specifically specified in most loss. Pstage9 can be classified to low-side MOSFET turn off
buck-control datasheets, Inductor current (IL+) flows into switching loss.
low-side MOSEFT (Ron(L))’s body diode D2 therefore power
III. CONDUCTION LOSS ANALYSIS power loss of Ploss_1st, the junction temperature of MOSFET
In the section conduction loss will be discussed as below. can be calculated as below.
Most of paper analysis conduction loss does not consider TjU _1st = TA +(PLoss(H) _1st × θ JA ) (46)
about thermal. MOFET thermal characteristic are specifically
specified in most MOSFET datasheets. Figure 5 show the TjL _1st = TA +(PLoss(L) _1st × θ JA ) (47)
IPD06N03 and IPD09N03 of Ron vs. thermal characteristic st
Since get the Tj_1 substitute equation (31) and (32),
curve. then get the new Ron(U)(TjU)_1st and Ron(L)(TjL)_1st,
IPD06N03 Ron vs.T(j) IPD09N03 Ron vs.T(j) subsequently substitute (40) and (41) get the Ploss_2st
10 16 high-side and low-side MOSFET Power loss
9 14
Pconduction_H _1st = I rmsh 2 × R on(U) (TjU )_1st (48)
Ron(mohm)
Ron(mohm)

8 12
7 10
Pconduction_L _1st = I rmsL 2 × R on(L) (TjL )_1st (49)
6 8
5 6
PLoss(H) _2st = Pconduction_H _1st +PSwitching_H (50)
4 4
0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180 st st
T(j) ℃ T(j) ℃
PLoss(L) _2 = Pconduction_L _1 +PSwitching_L (51)
st
(a) (b) According power loss of Ploss_2 , the junction
Fig. 5. Ron thermal characteristic of (a) IPD06N03, (b) temperature of Tj_2st can be calculated as below.
IPD09N03 TJU _2st = TA +(PLoss(H) _2st × θ JA ) (52)
According Figure 5 data, Ron relative to Tj can be
described to linearly equations as below. TJL _2st = TA +(PLoss(L) _2st × θ JA ) (53)
st
-6
Ron(U ) (TjU ) = 33.12×10 ×(TjU +20)+0.006+(Ron(U ) -7.5× 10 ) (31) -3 Since get the Tj_2 substitute equation (31) and (32), get
the new Ron(U)(TjU)_2st and Ron(L)(TjL)_2st, subsequently
Ron( L) (TjL ) = 21.87×10-6 ×(TjL +20)+0.004+(Ron( L) -5× 10-3) (32) substitute (40) and (41) get the Ploss_3st high-side and low-side
MOSFET Power loss.
Tj is the key-point for calculate real Ron How to get the
Tj, since switching loss have analysis done. High-side、 Pconduction_H _2st = I rmsh 2 × R on(U) (TjU )_2st (54)
low-side switching loss and dead-time loss can be calculated. st 2
Pconduction_L _2 = I rmsL × R on(L) (TjL )_2 st
(55)
High-side and low-side MOSFET conduction loss can be
described as below, where Ron(U) and R(onL) which are mean PLoss(H) _3st = Pconduction_H _2st +PSwitching_H (56)
ambient temperature 25 degree’s resistance. st st
PLoss(L) _3 = Pconduction_L _2 +PSwitching_L (57)
Ir = ∆i L / 2 (33)
Iterative continues calculated until the junction
Vo + I out × Ron ( L ) t −t temperature stable.
D= = 4 3 (34)
Vin − I load × Ron (U ) + I out × Ron ( L ) Ts
IV. EXPERIMENTAL VERIFICATIONS
t −t Using commercial Control IC RT8123 from Richtek and
D2 = 1− D = 7 6 (35) using commercial N-MOSFET IPD06N03 and IPD09N03
Ts
from Infineon, table1 show the experiment condition and
1 t4 2I r MOSFET parameter to verify the theoretical analysis of the
I rmsh =
Ts ∫t3
(
(t4 − t3 )
t + I out − I r ) 2 dt (36)
switching loss and conduction loss is correct. Table 2 show
the experimental results compared with theoretical analysis.
1 t7 −2 I r Table1. Circuit parameters
I rmsL =
Ts ∫ t6
(
t7 − t6
t + I o + I r ) 2 dt (37)
Parameter Value
Input voltage 12V
I rmsh = (Ir 2 / 3 × D) + (Iout 2 × D) (38) Output voltage 1.2V
2 2 Output current From 4A to 10A
I rmsL = (Ir / 3 × D 2 ) + (Iout × D2 ) (39)
Inductance; DCR ; AC DCR 1uH ;2mΩ ;40mΩ
2
Pconduction_H = I rmsh × R on(U) (40) Output capacitance; ESR 470uF ;30mΩ
2 High Side MOSFET IPD09N03) 8 mΩ
Pconduction_L = I rmsL × R on(L) (41)
Q =2nC ; Qgs1=5nC
(IPD09N03) (Qgth1;Qgs1;Qgd1;Qg1) gth1
PSwitching_H = Pstage1 + Pstage2 +Pstage3 +Pstage5 (42) Qgd1=5nC ; Qg1=30nC
Coss2=474pF
st
PLoss(H) _1 = Pconduction_H +PSwitching_H (44) (IPD09N03) Rg1,Vt1 1 Ω ; Vt1=2V
Low Side MOSFET (IPD06N03) 5 mΩ
PLoss(L) _1st = Pconduction_L + PSwitching_L (45)
(IPD06N03) (Qgd2、Qg2) Qgd2=6nC ; Qg2=50nC
If the junction to ambient thermal resistance θJA and (IPD06N03) (Crss2、Coss2)
Coss2=800pF
maximum ambient temperature TA are known, then according
Experimental result to verify the theoretical analysis is
(IPD06N03) (Qrr) 10nC
correct. Buck converter as their switching frequencies being
(IPD06N03) Rg1 ; Vt2 1 Ω ; Vt2=2V
increased to reduce the size of passive components. As
Control IC (RT8123) N/A
frequencies increases then the switching loss also increase,
Switching Frequency 291K how to reduce the switching loss becomes more important.
Dead-time A 16nS According the theoretical analysis most of switching losses is
Dead-time B 40nS donated while High-Side MOSFET is turned on so there are
RDRIVER_H1=14Ω some methods to reduce which are increasing driving ability
RDRIVER_H1 and RSINK_H1
RSINK_H1=17Ω of high side or using smaller parasitic impedances or using
RDRIVER_H2=14Ω smaller reverse cover recovery charge Qrr.
RDRIVER_H2 and RSINK_H2
RSINK_H2=17Ω
VDRIVE_H=12V ACKNOWLEDGMENT
VDRIVE_H、VDRIVE_L The authors would like to acknowledge the financial
VDRIVE_L=12V
support of the National Science Council of Taiwan through
θ JA 45 ℃
grant number NSC 100-2628-E-011-009-MY3.
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