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Experiment no 01:

OBJECTIVE:

1. Layout design and simulation of 2 input logic gates (NAND & NOR).
2. Layout design and simulation of 3 input logic gates (NAND & NOR).
3. Layout design and simulation of Y=(A+B+C)D .
4. Layout design and simulation of Y=(ABC)+D .
5.Layout design and simulation of Y=(A+B)(C+D) .
6. Layout design and simulation of Y=(AB)+(CD).

Layout design and simulation of 2 input logic gates (NAND & NOR).
Truth table of NAND
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
0 0 1
0 1 1
1 0 1
1 1 0
Simulation and timing diagram :

Truth table of NOR gate


Truth table of NOR
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
0 0 1
0 1 0
1 0 0
1 1 0
Simulation and timing diagram :

Layout design and simulation of 3 input logic gates (NAND & NOR).
Truth table of 3 input NAND
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Simulation and timing diagram :

Truth table of NOR:

A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

Simulation and timing diagram :


Layout design and simulation of Y=(A+B+C)D .
Truth table
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

Simulation and timing diagram :

Layout design and simulation of Y=(ABC)+D .


Truth table
A B C D Y
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

Simulation and timing diagram :


Layout design and simulation of Y=(A+B)(C+D)
Truth table :
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
Simulation and timing diagram :
Layout design and simulation of Y=(AB)+(CD).
Truth table:
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

Simulation and timing diagram :