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5 4 3 2 1

01
PCB STACK UP

BD9 FT3 Kabini Block Diagram


LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : SVCC
DDRIII-SODIMM1
LAYER 5 : IN2 DDRIII-SODIMM2
D Page 10,11 LVDS CONN D
LAYER 6 : IN3 Single Channel DDR III Port 0
RTD2136R LVDS Panel
LAYER 7 : GND Page 24 Page 30
800~1866 MHZ
LAYER 8 : BOT X'TAL
APU For support PRD 1600x900

25MHz

Atheros LVDS CONN


10/100M PCIe-0 PCI-Express eDP Panel
Transformer AR8162B Kabini APU 25W/15W Page 30
Page 26
Page 26
SoC
WLAN Con. PCIe-1 Port 1
RJ45 HDMI CONN
Page 26 Page 25
Page 28

24.5mm X 24.5mm POWER SYSTEM


ISL88732 P34

SATA - HDD Con. SATA 0 SATA


BGA 769 pin TPS51123A P35
C Page 31
PCI-E x4 dGPU TPS51216RUKR P36 C

VRAM DDR3-256MB*4 TPS51211DSCR P37


GFX Mars/Sun VRAM DDRIII
SATA - ODD Con. SATA 1 VRAM DDR3-512MB*4 ISL62771 P38
Pro
Support zero power ODD Page 20, 21 Discharge P39
Page 31 29mm X 29mm ISL62881CHRTZ-T P40
Page 12~19,22
G9661-25ADJF12U P41
USB2_0 USB 2.0 (Port 0 ~ 9) X'TAL
USB/B USB2.0 USB3.0 27.0MHz
Page 23
CHARGER P34
USB 3.0 (Port 0 ~ 1) USB3_0
USB2_1
USB/B USB2_8 USB3.0 w/ S&C +15V
Page 23 +3VPCU
X'TAL Page 23
32.768KHz
USB3_1 +3V_S5
Genesys Logic USB2_5 +3V
Card Reader Con.
Page 29 GL834L Page 29 USB2_9 USB3.0 w/o S&C +5VPCU
Page 23 +5V_S5
USB2_6 X'TAL +5V P35
CCD +1.5V_RTC
48 MHz
Page 30
+SMDDR_VTERM
B
BATTERY +SMDDR_VREF B

USB2_7
WLAN +1.5VSUS
SPI
Page 28 +1.5V_S5
Azalia IHDA +1.5V P36

SPI
Page 8 +0.95V_DUAL
LPC +0.95V
SPI +1.8V_S5
+1.8V P37
Conexant Nuvoton
Audio Codec EC NPCE985L +VDD_CORE
CX20756-11Z Page 27
Page 33
+VDDNB_CORE
P38
Port-B

Port-A

FAN HALL Sensor LED K/B Con. Touch Pad /B Power /B DISCHARGE P39
Con. Con.
MIC JACK HP SPK Con. Page 7 Page 30 Page 29 Page 32 Page 32 Page 32
Page 27 Page 27 Page 27 +VGPU_CORE P40

A A
+1.8V_GPU
+1.5V_GPU
+0.95V_GPU P41

Quanta Computer Inc.


PROJECT : BD9
Size Document Number Rev
Block Diagram A1A

Date: Tuesday, December 25, 2012 Sheet 1 of 41


5 4 3 2 1
5 4 3 2 1

02
Table of Contents

PAGE DESCRIPTION BOI-FUNCTION Power States


D CONTROL D
POWER PLANE VOLTAGE SIGNAL ACTIVE IN
1 Schematic Block Diagram
2 Power Stage
VIN 10V~+19V S0~S5
3-8 Processor CPU
9 Straps CPU +VCCRTC +1.5V S0~S5
10 SO-DIMM 1 DDR
+3V +3.3V MAIND S0
11 SO-DIMM 2 DDR
12 - 19 Mars/Sun Pro(M2) VGA +3V_S5 +3.3V S5_ON S0~S5
20 - 21 VRAM - DDR3 VGA
+3VPCU +3.3V AC/DC Insert enable S0~S5
22 PX5 VGA
23 USB U3B/USB +5V +5V MAIND S0
24 eDP to LVDS(RTD2136R) LDS
+5V_S5 +5V S5_ON S0~S5
25 HDMI/Touch Screen HDM/TSN
26 LAN(1AR8162B) LAN +5VPCU +5V AC/DC Insert enable S0~S5
27 Codec (CX20756-11Z) ADO
28 MINI CARD (WLAN) MNW +WIMAX_P +3.3V IOAC_EN S0
29 CARD READER(GL834L)/LED MMC/LED
+1.5VSUS +1.5V SUSON S0~S3
30 LDS/CRT/CCD LDS/CRT/CCD
31 HDD/ODD HDD/ODD +1.5V +1.5V MAIND S0
C C
32 KB/TouchPad KBC/TPD
+1.8V_S5 +1.8V PE_PWRGD ^ PE_GPIO1 S0~S5
33 EC 985L KBC
34 Charger (ISL88731CHRTZ-T) CHR +0.95V_DUAL +0.95V +0.95V_DUAL_EN S0~S5
35 System 5V/3V PWM
36 DDR 1.5V PWM +0.95V +0.95V MAIND S0
37 +0.95V_DUAL PWM
38 +VCC_CORE PWM +VDD_CORE ~ VRON S0
39 Discharge PWM
+VDDNB_CORE ~ VRON S0
40 GPU_CORE PWM
41 +0.95V_GPU/+1.8V_GPU/+1.5V_GPU/+3V_GPU PWM +VGPU_CORE GPU_MAINON ^ PE_GPIO1 S0

+1.8V_GPU +1.8V GPU_MAIND S0

+0.95V_GPU +0.95V GPU_MAINON ^ PE_GPIO1 S0

+3V_GPU +3.3V GPU_MAIND S0

+1.5V_GPU +1.5V GPU_MAIND S0

GND PLANE PAGE


B GND_SIGNAL B

8769GND

GND ALL

ADOGND

A A

Quanta Computer Inc.


PROJECT : BD9
Size Document Number Rev
A1A
POWER STAGE & BOI-FUNCTION
Date: Tuesday, December 25, 2012 Sheet 2 of 41
5 4 3 2 1
5 4 3 2 1

U22B
PCIE
Coupling Caps Note:
X5R is required. 03
PCIE_RXP_LAN R10 P_GPP_RXP0 P_GPP_TXP0 L2 PCIE_TXP_LAN_C C624 LAN@0.1U/10V_4X PCIE_TXP_LAN
[26] PCIE_RXP_LAN PCIE_TXP_LAN [26]
PCIE_RXN_LAN R8 L1 PCIE_TXN_LAN_C LAN@0.1U/10V_4X PCIE_TXN_LAN
PCIe-LAN [26] PCIE_RXN_LAN
P_GPP_RXN0 P_GPP_TXN0 C621
PCIE_TXN_LAN [26] PCIe-LAN
D PCIE_RXP_WLAN R5 K2 PCIE_TXP_WLAN_C C622 0.1U/10V_4X PCIE_TXP_WLAN D
P_GPP_RXP1 P_GPP_TXP1
[28] PCIE_RXP_WLAN R4 K1 PCIE_TXP_WLAN [28]
PCIE_RXN_WLAN PCIE_TXN_WLAN_C PCIE_TXN_WLAN
PCIe-WLAN [28] PCIE_RXN_WLAN
P_GPP_RXN1 P_GPP_TXN1 C620 0.1U/10V_4X
PCIE_TXN_WLAN [28] PCIe-WLAN
N5 P_GPP_RXP2 P_GPP_TXP2 J2
N4 P_GPP_RXN2 P_GPP_TXN2 J1

N10 P_GPP_RXP3 P_GPP_TXP3 H2


N8 P_GPP_RXN3 P_GPP_TXN3 H1

R109 1.69K/F_4 P_TX_ZVDD W8 P_TX_ZVDD_095 P_RX_ZVDD_095 W7 P_RX_ZVDD R104 1K/F_4


+0.95V +0.95V

PEG_RXP0 L5 P_GFX_RXP0 P_GFX_TXP0 G2 PEG_TXP0_C C619 EV@0.1U/10V_4X PEG_TXP0


[12] PEG_RXP0 L4 G1 PEG_TXP0 [12]
PEG_RXN0 P_GFX_RXN0 P_GFX_TXN0 PEG_TXN0_C C617 EV@0.1U/10V_4X PEG_TXN0
[12] PEG_RXN0 PEG_TXN0 [12]

PEG X 4
PEG_RXP1 J5 P_GFX_RXP1 P_GFX_TXP1 F2 PEG_TXP1_C C618 EV@0.1U/10V_4X PEG_TXP1
[12] PEG_RXP1 J4 F1 PEG_TXP1 [12]
PEG_RXN1 P_GFX_RXN1 P_GFX_TXN1 PEG_TXN1_C C616 EV@0.1U/10V_4X PEG_TXN1
[12] PEG_RXN1 PEG_TXN1 [12]
PEG_RXP2 G5 P_GFX_RXP2 P_GFX_TXP2 E2 PEG_TXP2_C C615 EV@0.1U/10V_4X PEG_TXP2
[12] PEG_RXP2 PEG_TXP2 [12]
PEG_RXN2 G4 P_GFX_RXN2 P_GFX_TXN2 E1 PEG_TXN2_C C613 EV@0.1U/10V_4X PEG_TXN2
[12] PEG_RXN2 PEG_TXN2 [12]
PEG_RXP3 D7 P_GFX_RXP3 P_GFX_TXP3 D2 PEG_TXP3_C C614 EV@0.1U/10V_4X PEG_TXP3
[12] PEG_RXP3 PEG_TXP3 [12]
PEG_RXN3 E7 P_GFX_RXN3 P_GFX_TXN3 D1 PEG_TXN3_C C612 EV@0.1U/10V_4X PEG_TXN3
C [12] PEG_RXN3 PEG_TXN3 [12] C

FT3 REV 0.53

FT3

+1.8V
HDT+ Connector
+1.8V SPEC X with CHECK LIST
J1

R41 1 2 APU_TCK
CPU_VDDIO1 CPU_TCK APU_TCK [5]
*DEBUG@1K_4 3 4 APU_TMS
5 GND1 CPU_TMS 6 APU_TMS [5]
APU_TDI
7 GND2 CPU_TDI 8 APU_TDI [5]
APU_TDO
GND3 CPU_TDO APU_TDO [5]
APU_TRST# R47 DEBUG@0_4 9 10 APU_PWROK_BUF
[5] APU_TRST# 11 CPU_TRST_L CPU_PWROK_BUF 12
R53 DEBUG@10K_4 APU_RST_L_BUF
R55 DEBUG@10K_4 13 CPU_DBRDY3 CPU_RST_L_BUF 14 APU_DBRDY
15 CPU_DBRDY2 CPU_DBRDY0 16 APU_DBRDY [5]
R62 DEBUG@10K_4 DBREQ# R64 *DEBUG/EVB@0_4 APU_DBREQ#
17 CPU_DBRDY1 CPU_DBREQ_L 18 APU_DBREQ# [5]
B APU_TEST19_PLLTEST0 B
GND4 CPU_PLLTEST0 APU_TEST19_PLLTEST0 [5]
19 20 APU_TEST18_PLLTEST1
CPU_VDDIO2 CPU_PLLTEST1 APU_TEST18_PLLTEST1 [5]

*DEBUG@HDT+ HEADER

Debug only

R600 *0_4

C26 *E@1000P/50V_4X Close by HDT+ Conector


APU_TDI R387 *DEBUG@1K_4
Debug only APU_TCK R389 *DEBUG@1K_4
+1.8V
U3 APU_TMS R388 *DEBUG@1K_4
APU_RST# 1 6 APU_RST_L_BUF R28 *DEBUG@1K_4 +1.8V APU_DBREQ# R69 *DEBUG@1K_4
[5] APU_RST# A1 Y1
2 5 +1.8V C44
GND VCC
APU_PWRGD 3 4 APU_PWROK_BUF R25 *DEBUG@1K_4 *DEBUG@0.1U/10V_4X
[5] APU_PWRGD A2 Y2

C21 *DEBUG@74LVC2G07
A *DEBUG@0.1U/10V_4X C23 C20 A
*DEBUG@0.1U/10V_4X *E@1000P/50V_4X
R601 *0_4
Quanta Computer Inc.
PROJECT : BD9
RevB 1221 Add 0 ohm for debug Size Document Number Rev
A1A
APU 1/6(PCIE/GPP)
Date: Tuesday, December 25, 2012 Sheet 3 of 41
5 4 3 2 1
5 4 3 2 1

04
U22A
M_A_A[15:0] MEMORY M_A_DQ[63:0]
[10,11] M_A_A[15:0] M_A_DQ[63:0] [10,11]
M_A_A0 AG38 M_ADD0 M_DATA0 B30 M_A_DQ0
D M_A_A1 W 35 M_ADD1 M_DATA1 A32 M_A_DQ1 D
M_A_A2 W 38 M_ADD2 M_DATA2 B35 M_A_DQ2
M_A_A3 W 34 M_ADD3 M_DATA3 A36 M_A_DQ3
M_A_A4 U38 M_ADD4 M_DATA4 B29 M_A_DQ4
M_A_A5 U37 M_ADD5 M_DATA5 A30 M_A_DQ5
M_A_A6 U34 M_ADD6 M_DATA6 A34 M_A_DQ6
M_A_A7 R35 M_ADD7 M_DATA7 B34 M_A_DQ7
M_A_A8 R38 M_ADD8
M_A_A9 N38 M_ADD9 M_DATA8 B37 M_A_DQ8
M_A_A10 AG34 M_ADD10 M_DATA9 A38 M_A_DQ9
M_A_A11 R34 M_ADD11 M_DATA10 D40 M_A_DQ10
M_A_A12 N37 M_ADD12 M_DATA11 D41 M_A_DQ11
M_A_A13 AN34 M_ADD13 M_DATA12 B36 M_A_DQ12
M_A_A14 L38 M_ADD14 M_DATA13 A37 M_A_DQ13
M_A_BS#[2:0] M_A_A15 L35 M_ADD15 M_DATA14 B41 M_A_DQ14
[10,11] M_A_BS#[2..0] C40 M_A_DQ15
M_DATA15
M_A_BS#0 AJ38 M_BANK0
M_A_BS#1 AG35 M_BANK1 M_DATA16 F40 M_A_DQ16
M_A_DM[7:0] M_A_BS#2 N34 M_BANK2 M_DATA17 F41 M_A_DQ17
[10,11] M_A_DM[7..0] K40
M_DATA18 M_A_DQ18
M_A_DM0 B32 M_DM0 M_DATA19 K41 M_A_DQ19
M_A_DM1 B38 M_DM1 M_DATA20 E40 M_A_DQ20
M_A_DM2 G40 M_DM2 M_DATA21 E41 M_A_DQ21
M_A_DM3 N41 M_DM3 M_DATA22 J40 M_A_DQ22
M_A_DM4 AG40 M_DM4 M_DATA23 J41 M_A_DQ23
M_A_DM5 AN41 M_DM5
M_A_DM6 AY40 M_DM6 M_DATA24 M41 M_A_DQ24
M_A_DM7 AY34 M_DM7 M_DATA25 N40 M_A_DQ25
TP40 Y40 M_DM8 M_DATA26 T41 M_A_DQ26
M_DATA27 U40 M_A_DQ27
C M_A_DQSP0 B33 M_DQS_H0 M_DATA28 L40 M_A_DQ28 C
[10,11] M_A_DQSP0
M_A_DQSN0 A33 M_DQS_L0 M_DATA29 M40 M_A_DQ29
[10,11] M_A_DQSN0 M_A_DQSP1 B40 R40 M_A_DQ30
M_DQS_H1 M_DATA30
[10,11] M_A_DQSP1 A40 T40
M_A_DQSN1 M_DQS_L1 M_DATA31 M_A_DQ31
[10,11] M_A_DQSN1 H41
M_A_DQSP2 M_DQS_H2
[10,11] M_A_DQSP2 H40 AF40
M_A_DQSN2 M_DQS_L2 M_DATA32 M_A_DQ32
[10,11] M_A_DQSN2
M_A_DQSP3 P41 M_DQS_H3 M_DATA33 AF41 M_A_DQ33
[10,11] M_A_DQSP3 P40 AK40
M_A_DQSN3 M_DQS_L3 M_DATA34 M_A_DQ34
[10,11] M_A_DQSN3
M_A_DQSP4 AH41 M_DQS_H4 M_DATA35 AK41 M_A_DQ35
[10,11] M_A_DQSP4
M_A_DQSN4 AH40 M_DQS_L4 M_DATA36 AE40 M_A_DQ36
[10,11] M_A_DQSN4 AP41 AE41
M_A_DQSP5 M_DQS_H5 M_DATA37 M_A_DQ37
[10,11] M_A_DQSP5 AP40 AJ40
M_A_DQSN5 M_DQS_L5 M_DATA38 M_A_DQ38
[10,11] M_A_DQSN5 M_A_DQSP6 BA40 AJ41 M_A_DQ39
M_DQS_H6 M_DATA39
[10,11] M_A_DQSP6
M_A_DQSN6 AY41 M_DQS_L6
[10,11] M_A_DQSN6 AY33 AM41
M_A_DQSP7 M_DQS_H7 M_DATA40 M_A_DQ40
[10,11] M_A_DQSP7 M_A_DQSN7 BA34 AN40 M_A_DQ41
M_DQS_L7 M_DATA41
[10,11] M_A_DQSN7
AA40 M_DQS_H8 M_DATA42 AT41 M_A_DQ42
Y41 M_DQS_L8 M_DATA43 AU40 M_A_DQ43
M_DATA44 AL40 M_A_DQ44
M_A_CLKP0 AC35 M_CLK_H0 M_DATA45 AM40 M_A_DQ45
[10] M_A_CLKP0 M_A_CLKN0 AC34 AR40 M_A_DQ46
M_CLK_L0 M_DATA46
+1.5VSUS [10] M_A_CLKN0 AA34 AT40
M_A_CLKP1 M_CLK_H1 M_DATA47 M_A_DQ47
[10] M_A_CLKP1 AA32
M_A_CLKN1 M_CLK_L1
[10] M_A_CLKN1 AE38 AV41
M_A_CLKP2 M_CLK_H2 M_DATA48 M_A_DQ48
[11] M_A_CLKP2 AE37 AW 40
M_A_CLKN2 M_CLK_L2 M_DATA49 M_A_DQ49
[11] M_A_CLKN2 AA37 BA38
R113 M_A_CLKP3 M_CLK_H3 M_DATA50 M_A_DQ50
[11] M_A_CLKP3
M_A_CLKN3 AA38 M_CLK_L3 M_DATA51 AY37 M_A_DQ51
[11] M_A_CLKN3 AU41 M_A_DQ52
1K/F_4 M_DATA52
M_A_RST# G38 M_RESET_L M_DATA53 AV40 M_A_DQ53
[10,11] M_A_RST#
M_A_EVENT# AE34 M_EVENT_L M_DATA54 AY39 M_A_DQ54
B [10,11] M_A_EVENT# AY38 B
M_DATA55 M_A_DQ55
M_A_CKE0 L34 M0_CKE0
[10] M_A_CKE0 J38 BA36
M_A_CKE1 M0_CKE1 M_DATA56 M_A_DQ56
[10] M_A_CKE1
M_A_CKE2 J37 M1_CKE0 M_DATA57 AY35 M_A_DQ57
[11] M_A_CKE2
M_A_CKE3 J34 M1_CKE1 M_DATA58 BA32 M_A_DQ58
[11] M_A_CKE3 AY31
M_DATA59 M_A_DQ59
M_A_ODT0 AN38 M0_ODT0 M_DATA60 BA37 M_A_DQ60
[10] M_A_ODT0 M_A_ODT1 AU38 AY36 M_A_DQ61
M0_ODT1 M_DATA61
[10] M_A_ODT1
M_A_ODT2 AN37 M1_ODT0 M_DATA62 BA33 M_A_DQ62
[11] M_A_ODT2 AR37 AY32
M_A_ODT3 M1_ODT1 M_DATA63 M_A_DQ63
[11] M_A_ODT3
M_A_CS#0 AJ34 M0_CS_L0 M_CHECK0 V41
+1.5VSUS [10] M_A_CS#0 AR38 W 40
M_A_CS#1 M0_CS_L1 M_CHECK1
[10] M_A_CS#1 AL38 AB40
M_A_CS#2 M1_CS_L0 M_CHECK2
[11] M_A_CS#2
M_A_CS#3 AN35 M1_CS_L1 M_CHECK3 AC40
[11] M_A_CS#3 U41
M_CHECK4
R459 M_A_RAS# AJ37 M_RAS_L M_CHECK5 V40
[10,11] M_A_RAS# AL34 AA41
1K/F_4 M_A_CAS# M_CAS_L M_CHECK6
+MEMVREF_CPU [10,11] M_A_CAS# AL35 AB41
M_A_WE# M_WE_L M_CHECK7
[10,11] M_A_WE#
AD40 M_VREF
+MEMVREF_CPU
AC38 M_VREFDQ M_ZVDDIO_MEM_S AD41 +M_ZVDDIO
+APU_M_VREFDQ_SUS +1.5VSUS
39.2/F_4 R458
FT3 REV 0.53
Place close to APU within 1"
C625 C626 FT3
R460 C631 C628 C775
1K/F_4 C630 *1U/10V_4X *100P/50V_4N
0.47U/6.3V_4X 0.1U/10V_4X 1U/6.3V_4X 39P/50V_4N

A
RevB 1221 Add cap A

Quanta Computer Inc.


PROJECT : BD9
Size Document Number Rev
APU 2/6(DDR3 MEM) A1A

Date: Tuesday, December 25, 2012 Sheet 4 of 41


5 4 3 2 1
5 4 3 2 1

[25]
[25]
INT_HDMI_TXDP2
INT_HDMI_TXDN2
INT_HDMI_TXDP2
INT_HDMI_TXDN2
C603
C602
HM@0.1U/10V_4X
HM@0.1U/10V_4X
INT_HDMI_TXDP2_C
INT_HDMI_TXDN2_C
A9
B9
U22C

TDP1_TXP0
TDP1_TXN0
DISPLAY/SVI2/JTAG/TEST
DP_150_ZVSS
DP_2K_ZVSS
+3V DP_BLON
B16
A21
B17
DP_150_ZVSS
DP_2K_ZVSS
APU_BLON
R442
R434 1
150/F_4
2 2K/F_4
05
APU_BL_EN [30]
[25] INT_HDMI_TXDP1
INT_HDMI_TXDP1 C594 HM@0.1U/10V_4X INT_HDMI_TXDP1_C A10 TDP1_TXP1 +3V DP_DIGON A17 APU_DIGON
APU_DIGON [30] LVDS Back Light Control
[25] INT_HDMI_TXDN1
INT_HDMI_TXDN1 C593 HM@0.1U/10V_4X INT_HDMI_TXDN1_C B10 TDP1_TXN1 +3V DP_VARY_BL A18 APU_VARY_BL
APU_VARY_BL [24,30]
INT_HDMI_AUXP R94 *1.8K_4
INT_HDMI_AUXN R96 *1.8K_4
HDMI INT_HDMI_TXDP0 C601 HM@0.1U/10V_4X INT_HDMI_TXDP0_C A11 TDP1_TXP2
[25] INT_HDMI_TXDP0
[25] INT_HDMI_TXDN0
INT_HDMI_TXDN0 C600 HM@0.1U/10V_4X INT_HDMI_TXDN0_C B11 TDP1_TXN2 +3V TDP1_AUXP D17 INT_HDMI_AUXP
INT_HDMI_AUXP [25]
D +3V TDP1_AUXN E17 INT_HDMI_AUXN
INT_HDMI_AUXN [25] HDMI AUX D
INT_HDMI_TXCP C592 HM@0.1U/10V_4X INT_HDMI_TXCP_C A12 TDP1_TXP3
[25] INT_HDMI_TXCP
INT_HDMI_TXCN C591 HM@0.1U/10V_4X INT_HDMI_TXCN_C B12 TDP1_TXN3 +3V TDP1_HPD H19 INT_HDMI_HPD INT_LVDS_AUXP_C R65 1.8K_4
[25] INT_HDMI_TXCN INT_HDMI_HPD [25]
INT_LVDS_AUXN_C R70 1.8K_4
[24] INT_LVDS_TXP0 INT_LVDS_TXP0 C609 0.1U/10V_4X INT_LVDS_TXP0_C A4 LTDP0_TXP0 +3V LTDP0_AUXP D15 INT_LVDS_AUXP_C C42 0.1U/10V_4X INT_LVDS_AUXP
INT_LVDS_AUXP [24] EDID PU 4.7K +3.3V @ Conn
[24] INT_LVDS_TXN0
INT_LVDS_TXN0 C608 0.1U/10V_4X INT_LVDS_TXN0_C B4 LTDP0_TXN0 +3V LTDP0_AUXN E15 INT_LVDS_AUXN_C C43 0.1U/10V_4X INT_LVDS_AUXN
INT_LVDS_AUXN [24] eDP to LVDS Translator
[24] INT_LVDS_TXP1 INT_LVDS_TXP1 C607 0.1U/10V_4X INT_LVDS_TXP1_C A5 LTDP0_TXP1 +3V LTDP0_HPD H17 INT_LVDS_HPD_Q
INT_LVDS_TXN1 C606 0.1U/10V_4X INT_LVDS_TXN1_C B5 INT_LVDS_AUXP_C R66 *eDP@100K_4
LVDS [24] INT_LVDS_TXN1 LTDP0_TXN1
DAC_RED B14 APU_CRT_RED APU_CRT_RED [30] INT_LVDS_AUXN_C R71 *eDP@100K_4 +3V
INT_LVDS_TXP2 C605 eDP@0.1U/10V_4X INT_LVDS_TXP2_C A6 LTDP0_TXP2 layout trace
[30] INT_LVDS_TXP2
INT_LVDS_TXN2 C604 eDP@0.1U/10V_4X INT_LVDS_TXN2_C B6 A14 APU_CRT_GRE APU_CRT_GRE [30] R place close to APU For eDP Panel
[30] INT_LVDS_TXN2 LTDP0_TXN2 DAC_GREEN
reference GND
[30] INT_LVDS_TXP3 INT_LVDS_TXP3 C599 eDP@0.1U/10V_4X INT_LVDS_TXP3_C A7 LTDP0_TXP3 DAC_BLUE B15 APU_CRT_BLU APU_CRT_BLU [30] APU_CRT_RED R441 150/F_4
[30] INT_LVDS_TXN3 INT_LVDS_TXN3 C597 eDP@0.1U/10V_4X INT_LVDS_TXN3_C B7 LTDP0_TXN3
APU_CRT_GRE R440 150/F_4
+3V DAC_HSYNC G19 APU_CRT_HSYNC
APU_CRT_HSYNC [30]
Reserved for external clock Gen, K15 DISP_CLKIN_H +3V DAC_VSYNC E19 APU_CRT_VSYNC APU_CRT_VSYNC [30] APU_CRT_BLU R439 150/F_4
leave unconnected. H15 DISP_CLKIN_L
+1.8V +1.8V +3V DAC_SCL D19 APU_DDCCLK APU_DDCCLK [30] +3V
SVT G31 SVT +1.8V +3V DAC_SDA D21 APU_DDCDAT
APU_DDCDAT [30]
SVC D27 SVC +1.8V
SVD E29 SVD +1.8V DAC_ZVSS A16 DAC_ZVSS R433 499/F_4
R427 R428
300_4 300_4 APU_SIC B22 SIC +3V TEST4 H27 APU_TEST4 R401 +5V
TP10
APU_SID B21 SID +3V TEST5 H29 APU_TEST5 LDS@1K_4
D25 APU_TEST6 TP13
TEST6
APU_RST# B20 A27 APU_TEST14 TP8
[3] APU_RST# APU_RST_L TEST14
R444 0_4 APU_RST#_R A20 B27 APU_TEST15 TP4 R394
LDT_RST_L TEST15
A26 APU_TEST16 TP7 INT_LVDS_HPD_Q
TEST16
TP5 LDS@10K_4
C APU_PWRGD B19 APU_PWROK TEST17 B26 APU_TEST17 C
[3] APU_PWRGD TP1

3
R435 0_4 APU_PWRGD_R A19 LDT_PWROK TEST18 B28 APU_TEST18_PLLTEST1 LDS@2N7002KDW_115MA
APU_TEST18_PLLTEST1 [3]
C598 C596 C595 TEST19 A28 APU_TEST19_PLLTEST0 APU_TEST19_PLLTEST0 [3]
+3V R51 1K_4 H_PROCHOT A22 PROCHOT_L +3V TEST25_H B24 APU_TEST25_H 5
TP3
R432 1K_4 APU_ALERT# B18 ALERT_L +3V TEST25_L A24 APU_TEST25_L
TP2

6
150P/50V_4N 150P/50V_4N *E@0.1U/10V_4X TEST28_H AV35 APU_TEST28_H Q22B LDS@2N7002KDW_115MA
TP32
[3] APU_TDI
APU_TDI D29 TDI +1.8V TEST28_L AU35 APU_TEST28_L

4
TP29
APU_TDO D31 TDO +1.8V TEST31 E33 APU_TEST31 2 INT_LVDS_HPD
[3] APU_TDO TP9 INT_LVDS_HPD [24,30]
APU_TCK D35 TCK +1.8V
[3] APU_TCK
APU_TMS D33 TMS +1.8V RSVD A29 APU_TEST34 Q21A
[3] APU_TMS TP6
[3] APU_TRST#
APU_TRST# G27 TRST_L +1.8V TEST36 H21 APU_TEST36 R396

1
TP12
[3] APU_DBRDY
APU_DBRDY B25 DBRDY +1.8V TEST37 H25 APU_TEST37 100K_4
TP14
APU_DBREQ# A25 DBREQ_L +1.8V
[3] APU_DBREQ# AJ10
TEST42 APU_TEST42
APU_VDDNB_RUN_FB_H D23 AJ8 APU_TEST43 TP22
VDDCR_NB_SENSE TEST43
[38] APU_VDDNB_RUN_FB_H TP21
APU_VDD_RUN_FB_H G23 VDDCR_CPU_SENSE TEST39 R32 APU_TEST39
[38] APU_VDD_RUN_FB_H TP16
APU_VDDIO_RUN_FB_H E25 VDDIO_MEM_S_SENSE TEST40 N32 APU_TEST40 R392 eDP@0_4
APU_VDDIO_RUN_FB_H TP15
APU_VDD_RUN_FB_L R61 0_4 VSS_SENSE E23 VSS_SENSE TEST41 AP29 APU_TEST41
[38] APU_VDD_RUN_FB_L TP31
VDD_095_FB_H AV33 VDD_095_FB_H DP_STEREOSYNC E21 DP_STEREOSYNC R63 1K_4
VDD_095_FB_H
VDD_095_FB_L AU33 VDD_095_FB_L
VDD_095_FB_L

1.5V & 0.95V SENSE PIN


APU_TEST14 R60 *1K_4
RevB 1219 Change HDMI strap setting
FT3 REV 0.53
APU_TEST16 R59 *1K_4
FT3 APU_TEST17 R50 *1K_4
APU_VDDIO_RUN_FB_H APU_TEST18_PLLTEST1 R79 1K_4 from PD to PU for HDMI No display issue
TP11 APU_TEST19_PLLTEST0 R78 1K_4 +3V
VDD_095_FB_H APU_TEST25_H R58 510/F_4
B TP33 APU_TEST36 R57 *1K_4 B
VDD_095_FB_L R56 *1K_4
TP24 APU_TEST25_L +1.8V
R46 510/F_4 R52
1K_4
APU_TEST37 R95 *1K_4
R103 *1K_4
+1.8V APU_CRT_HSYNC

R54
Read APU Temperature +3V
*1K_4
PROC HOT R42 R49 R48
Note:
To override VID,Remove Rd,Re, Rf, Rg, install Rc
*1K_4 *1K_4 *1K_4
+3V +3V set VID via SVC & SVD option RES Ra, Rb
SVT R36 Rd 0_4 APU_SVT APU_SVT [38]
R410 R409
+3VPCU R34 10K_4 1K_4 1K_4 SVC R44 Re 0_4 APU_SVC APU_SVC [38]
2

Q25B 2N7002KDW_115MA
SVD R43 Rf 0_4 APU_SVD
APU_SVD [38]
3 1 H_PROCHOT 2ND_MBCLK 3 4 APU_SIC
[33] H_PROCHOT_EC# [23,33] 2ND_MBCLK
APU_PWRGD R424 Rg 0_4 CPU_PWRGD_SVID_REG CPU_PWRGD_SVID_REG [38]
Q7
2N7002K_300MA R412 *0_4
2

2N7002KDW_115MA Ra Rb Rc C586
+3V Q25A SVC SVD BOOT VOLTAGE R38 R37 R423
2ND_MBDATA 6 1 APU_SID *220_4 *220_4 *220_4 *0.1U/10V_4X
[23,33] 2ND_MBDATA
+3V_S5 R35 10K_4
A A
2

R406 *0_4 0 0 1.1


3 1
[38] CORE_PWM_PROCHOT#
0 1 1.0
Q6
2N7002K_300MA
1 0 0.9 Quanta Computer Inc.
1 1 0.8 PROJECT : BD9
Size Document Number Rev
A1A
APU 3/6(DP/SVI2/JTAG/Test)
Date: Tuesday, December 25, 2012 Sheet 5 of 41
5 4 3 2 1
5 4 3 2 1

+1.5VSUS 180pF: COG, NP0 U22F +VDD_CORE


06
21 A
Others: X5R 3 A J35 VDDIO_MEM_S_1
POWER
VDDCR_CPU_1 L21
U22G
GND
U22H
GND
L32 VDDIO_MEM_S_2 VDDCR_CPU_2 L23 A8 VSS_1 VSS_63 J3 W 29 VSS_125 VSS_187 AL39
C103 C144 C116 C146 C125 C165 L37 VDDIO_MEM_S_3 VDDCR_CPU_3 L25 C89 C99 C94 C107 C126 C110 A13 VSS_2 VSS_64 J7 W 39 VSS_126 VSS_188 AL41
N35 VDDIO_MEM_S_4 VDDCR_CPU_4 L27 A23 VSS_3 VSS_65 J8 W 41 VSS_127 VSS_189 AM11
D 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 180P/50V_4N 180P/50V_4N 180P/50V_4N R31 VDDIO_MEM_S_5 VDDCR_CPU_5 L29 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 180P/50V_4N 1U/6.3V_4X 1U/6.3V_4X A31 VSS_4 VSS_66 J39 Y1 VSS_128 VSS_190 AM27 D
R37 VDDIO_MEM_S_6 VDDCR_CPU_6 N21 A35 VSS_5 VSS_67 K11 Y2 VSS_129 VSS_191 AM31
U32 VDDIO_MEM_S_7 VDDCR_CPU_7 N23 A39 VSS_6 VSS_68 K13 AA3 VSS_130 VSS_192 AN3
U35 VDDIO_MEM_S_8 VDDCR_CPU_8 N27 B8 VSS_7 VSS_69 K17 AA7 VSS_131 VSS_193 AN7
C162 C92 C179 C153 C109 W 31 VDDIO_MEM_S_9 VDDCR_CPU_9 R21 C131 C121 C132 C147 C117 B13 VSS_8 VSS_70 K19 AA8 VSS_132 VSS_194 AN39
W 32 VDDIO_MEM_S_10 VDDCR_CPU_10 R23 B23 VSS_9 VSS_71 K21 AA11 VSS_133 VSS_195 AP31
180P/50V_4N 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X W 37 VDDIO_MEM_S_11 VDDCR_CPU_11 R27 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X B31 VSS_10 VSS_72 K23 AA15 VSS_134 VSS_196 AR3
AA31 VDDIO_MEM_S_12 VDDCR_CPU_12 U21 B39 VSS_11 VSS_73 K25 AA19 VSS_135 VSS_197 AR13
AA35 VDDIO_MEM_S_13 VDDCR_CPU_13 U23 C1 VSS_12 VSS_74 K27 AA25 VSS_136 VSS_198 AR17
AC32 VDDIO_MEM_S_14 VDDCR_CPU_14 U27 C2 VSS_13 VSS_75 K29 AA29 VSS_137 VSS_199 AR21
C128 C71 C139 C196 AC37 VDDIO_MEM_S_15 VDDCR_CPU_15 W 21 C152 C148 C115 C151 C5 VSS_14 VSS_76 K31 AA39 VSS_138 VSS_200 AR25
AE31 VDDIO_MEM_S_16 VDDCR_CPU_16 W 23 C7 VSS_15 VSS_77 L3 AC3 VSS_139 VSS_201 AR29
0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X AE35 VDDIO_MEM_S_17 VDDCR_CPU_17 W 27 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X C9 VSS_16 VSS_78 L7 AC7 VSS_140 VSS_202 AR39
AG32 VDDIO_MEM_S_18 VDDCR_CPU_18 AA21 C11 VSS_17 VSS_79 L8 AC11 VSS_141 VSS_203 AR41
AG37 VDDIO_MEM_S_19 VDDCR_CPU_19 AA23 C13 VSS_18 VSS_80 L10 AC15 VSS_142 VSS_204 AU1
AJ35 VDDIO_MEM_S_20 VDDCR_CPU_20 AA27 C15 VSS_19 VSS_81 L11 AC19 VSS_143 VSS_205 AU2
AL32 VDDIO_MEM_S_21 VDDCR_CPU_21 AC21 C17 VSS_20 VSS_82 L15 AC25 VSS_144 VSS_206 AU3
AL37 VDDIO_MEM_S_22 VDDCR_CPU_22 AC23 C19 VSS_21 VSS_83 L19 AC29 VSS_145 VSS_207 AU15
AR35 VDDIO_MEM_S_23 VDDCR_CPU_23 AC27 C21 VSS_22 VSS_84 L31 AC31 VSS_146 VSS_208 AU19
VDDCR_CPU_24 AE21 C23 VSS_23 VSS_85 L39 AC39 VSS_147 VSS_209 AU23
VDDCR_CPU_25 AE23 C25 VSS_24 VSS_86 L41 AC41 VSS_148 VSS_210 AU27
AE27 +VDDNB_CORE C27 M1 AE3 AU39
+1.5V_S5 +APU_VDDIO_AZ_S
VDDCR_CPU_26
17 A C29
VSS_25
VSS_26
VSS_87
VSS_88 M2 AE7
VSS_149
VSS_150
VSS_211
VSS_212 AV9
VDDCR_NB_1 L13 C31 VSS_27 VSS_89 N3 AE25 VSS_151 VSS_213 AW 3
L17 C33 N7 AE29 AW 7
R483 0_8
0.1 A VDDCR_NB_2
VDDCR_NB_3 N11 C104 C95 C85 C79 C155 C170 C35
VSS_28
VSS_29
VSS_90
VSS_91 N15 AE32
VSS_152
VSS_153
VSS_214
VSS_215 AW 13
VDDCR_NB_4 N13 C37 VSS_30 VSS_92 N19 AE39 VSS_154 VSS_216 AW 15
C656 C649 C655 C648 C650 VDDCR_NB_5 N17 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 180P/50V_4N 1U/6.3V_4X C39 VSS_31 VSS_93 N25 AG3 VSS_155 VSS_217 AW 17
VDDCR_NB_6 R11 C41 VSS_32 VSS_94 N29 AG5 VSS_156 VSS_218 AW 19
1U/6.3V_4X 1U/6.3V_4X 180P/50V_4N 1U/6.3V_4X 4.7U/6.3V_6X VDDCR_NB_7 R13 D9 VSS_33 VSS_95 N31 AG10 VSS_157 VSS_219 AW 21
C VDDCR_NB_8 R17 D11 VSS_34 VSS_96 N39 AG11 VSS_158 VSS_220 AW 23 C
VDDCR_NB_9 U13 C130 C120 C149 C169 D13 VSS_35 VSS_97 P1 AG13 VSS_159 VSS_221 AW 25
RevB 1219 Change from short pad to mount 0805 VDDCR_NB_10 U17
W 13 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X
E3
E4
VSS_36 VSS_98 P2
R3
AG15
AG19
VSS_160 VSS_222 AW 27
AW 31
VDDCR_NB_11 VSS_37 VSS_99 VSS_161 VSS_223
+1.8V_S5 +APU_VDD18V_S VDDCR_NB_12 W 17 E9 VSS_38 VSS_100 R7 AG25 VSS_162 VSS_224 AW 33
VDDCR_NB_13 AA13 E11 VSS_39 VSS_101 R15 AG29 VSS_163 VSS_225 AW 35
AA17 E13 R19 AG31 AW 37
R82 0_8
0.5 A VDDCR_NB_14
VDDCR_NB_15 AC13 E27
VSS_40
VSS_41
VSS_102
VSS_103 R25 AG39
VSS_164
VSS_165
VSS_226
VSS_227 AW 39
VDDCR_NB_16 AC17 C168 C141 C113 C90 E31 VSS_42 VSS_104 R29 AG41 VSS_166 VSS_228 AW 41
C66 C56 C69 C55 VDDCR_NB_17 AE15 E35 VSS_43 VSS_105 R39 AH1 VSS_167 VSS_229 AY13
C47 VDDCR_NB_18 AE17 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X E38 VSS_44 VSS_106 R41 AH2 VSS_168 VSS_230 AY15
*180P/50V_4N 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 4.7U/6.3V_6X VDDCR_NB_19 AE19 E39 VSS_45 VSS_107 U1 AJ3 VSS_169 VSS_231 AY18
VDDCR_NB_20 AG17 G3 VSS_46 VSS_108 U2 AJ7 VSS_170 VSS_232 AY30
AL10 VDDIO_AZ_ALW_1 VDDCR_NB_21 AG21 G7 VSS_47 VSS_109 U3 AJ15 VSS_171 VSS_233 BA2
AL11 VDDIO_AZ_ALW_2 +1.5V_S5 +VDDIO_18V +1.8V G11 VSS_48 VSS_110 U7 AJ17 VSS_172 VSS_234 BA7
G13 U8 AJ19 BA13
C67 C65 C68 B1 VDD_18_ALW_1 VDD_18_1 A2
1.5 A L1 G15
VSS_49
VSS_50
VSS_111
VSS_112 U11 AJ23
VSS_173
VSS_174
VSS_235
VSS_236 BA15
C57 B2 VDD_18_ALW_2 VDD_18_2 A3 HCB1608KF-181T15_1.5A G17 VSS_51 VSS_113 U15 AJ25 VSS_175 VSS_237 BA18
1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X VDD_18_3 B3 C29 C36 C39 C34 G21 VSS_52 VSS_114 U19 AJ29 VSS_176 VSS_238 BA21
180P/50V_4N VDD_18_4 C3 C40 G25 VSS_53 VSS_115 U25 AJ31 VSS_177 VSS_239 BA25
G29 U29 AJ32 BA31
0.2 A AL13 VDD_33_ALW_1 VDD_33_1 AM15
0.2 A 10U/6.3V_6X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X
G35
VSS_54
VSS_55
VSS_116
VSS_117 U31 AJ39
VSS_178
VSS_179
VSS_240
VSS_241 BA35
+APU_3V_S +VDDIO_3V
AM13 VDD_33_ALW_2 VDD_33_2 AM17 G37 VSS_56 VSS_118 U39 AL3 VSS_180 VSS_242 BA39
C41 G39 VSS_57 VSS_119 W3 AL8 VSS_181 VSSBG_DAC A15
RevB 1219 Change from short pad to mount 0805 AR5
AU4
VDD_095_USB3_DUAL_1 VDD_095_1 AG23
AG27
C38 C33 G41
H11
VSS_58 VSS_120 W5
W 11
AL15
AL17
VSS_182 VSS_243 AL31
AM29
1 A AV7
VDD_095_USB3_DUAL_2
VDD_095_USB3_DUAL_3
VDD_095_2
VDD_095_3 AJ21 1U/6.3V_4X
C35 1U/6.3V_4X
180P/50V_4N H13
VSS_59
VSS_60
VSS_121
VSS_122 W 15 AL19
VSS_183
VSS_184
VSS_244

R505 U3@0_8 +VDD_095_USB3_S AW 5 VDD_095_USB3_DUAL_4 VDD_095_4 AJ27 1U/6.3V_4X H23 VSS_61 VSS_123 W 19 AL25 VSS_185
AL21 H31 W 25 AL29
AE11 VDD_095_ALW_1
VDD_095_5
VDD_095_6 AL23
5 A VSS_62 VSS_124 VSS_186

+VDD_095_GPP FT3 REV 0.53 FT3 REV 0.53


B
20MIL 0.5 A AE13
AJ11
VDD_095_ALW_2 VDD_095_7 AL27
AM23
RevB 1219 Change from short pad to mount 0805 FT3 FT3
B
VDD_095_ALW_3 VDD_095_8
+VDD_095_PHY_S AJ13 AM25 +VDDIO_3V +3V
+0.95V_DUAL R108 0_8 VDD_095_ALW_4 VDD_095_9
0.6 A
+1.5V_RTC_R +1.5V_RTC U10 +VDD_095_GFX R117 EV@0_8 R473 0_8
20MIL VDD_095_GFX_1
VDD_095_GFX_2 W 10
+0.95V
R140 10K_4 AN4 VDDBT_RTC_G VDD_095_GFX_3 AA10 C181 C183 C182
+3VPCU
NCP698SQ15T1G
FT3 REV 0.53
C140 1U/6.3V_4X 1U/6.3V_4X 180P/50V_4N
20MIL C195 FT3 C118
1

RTC_VIN 2 3 0.22U/10V_4X G1 EV@1U/6.3V_4X EV@10U/6.3V_6X


+VCCRTC_2 VIN VOUT
1 4
D31 GND EN *SHORT_PAD
2

R456
BAT54C-7-F_200MA
U29
RevB 1221 Change EV@ +0.95V

10K_4 R514 1K_4 +VDD_095_GPP L29


RevB 1210 Change P/N to AL000698000 HCB1608KF-181T15_1.5A
L28
+BAT

HCB1608KF-181T15_1.5A
20MIL 1.5V level C188 C177 C658 C659 C174 C178 C163 C154 C158
C678
need a LDO from 3V to 1.5V
1

180P/50V_4N 1U/6.3V_4X 10U/6.3V_6X 10U/6.3V_6X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X

1U/10V_4X
CN15

AAA-BAT-054-K01
2

A +VDD_095_USB3_S A
+3V_S5 +APU_3V_S +VDD_095_PHY_S

R488 0_8

C184 C176 C651 C186 C654 C197 C661 C667 C105 C156 C172 C173 C157

1U/6.3V_4X 1U/6.3V_4X 180P/50V_4N 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 10U/6.3V_6X 10U/6.3V_6X *10U/6.3V_6X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X Quanta Computer Inc.
RevB 1219 Change for EOD RevB 1219 Change for EOD
PROJECT : BD9
Size Document Number Rev
RevB 1219 Change from short pad to mount 0805 APU 4/6(POWER/GND/GND) A1A

Date: Thursday, December 27, 2012 Sheet 6 of 41


5 4 3 2 1
5 4 3 2 1

+3V_S5
R498
+3V_S5

*4.7K_4
07
C652 150P/50V_4N
To PCIE device U22D
LAN, WLAN, Cardreader, GPU ACPI/SD/AZ/GPIO/RTC/MISC

5
U28 [28,29,33] PLTRST# PLTRST# R479 33_4 A_RST# AY4 LPC_RST_L +3V_S5 +3V SD_PWR_CTRL BA23
2 PCIE_RST# R477 33_4 PCIE_RST#_R AY9 PCIE_RST_L +3V SD_CLK/GPIO73 AY22
APU_PCIE_RST# 4
[22,26,28] APU_PCIE_RST# 1 C660 150P/50V_4N RSMRST#_R AY5 RSMRST_L +1.8V_S5 +3V SD_CMD/GPIO74 AY23
+3V AY20
D [33] DNBSWON#
DNBSWON# R478 0_4 PWR_BTN# BA8 PWR_BTN_L +3V
SD_CD/GPIO75
SD_WP/GPIO76 BA20 Without SD, D

3
+1.8V_S5
*TC7SH08FU(F)
[9]
[9]
FCH_PWRGD
SYS_RST#
FCH_PWRGD
SYS_RST#
AM19
AY7
PWR_GOOD
SYS_RESET_L/GEVENT19_L +3V_S5 +3V SD_DATA0/GPIO77 BA22 Left Unconnected.
[26,28] PCIE_WAKE#
PCIE_WAKE# AW11 WAKE_L/GEVENT8_L +3V_S5 +3V SD_DATA1/GPIO78 AY21
R496 0_4 +3V SD_DATA2/GPIO79 AY24
[22,33] SLP_S3#
SLP_S3# AY3 SLP_S3_L +3V SD_DATA3/GPIO80 BA24
SLP_S5# BA5 SLP_S5_L +3V
[33] SLP_S5#
+3V SD_LED/GPIO45 AY25
APU_TEST0 AU13 TEST0 +3V_S5 SMB_RUN_CLK 2.2K_4 R493
D7 RB500V-40_100MA APU_TEST1 AY10 TEST1/TMS +3V_S5 +3V SCL0/GPIO43 AU25 SMB_RUN_CLK
SMB_RUN_CLK [10,11]
RSMRST_GATE# 1 2 RSMRST#_R APU_TEST2 AY6 TEST2 +3V_S5 +3V SDA0/GPIO47 AV25 SMB_RUN_DAT
SMB_RUN_DAT [10,11]
SMB_RUN_DAT 2.2K_4 R494
[33] RSMRST_GATE# R210 E@0_4
C281 EC_KBRST# AR23 KBRST_L +3V +3V_S5 SCL1/GPIO227 AY11 SMB_LAN_CLK
[33] EC_KBRST# SMB_LAN_CLK [24,28,32]
EC_A20GATE AR31 GA20IN/GEVENT0_L +3V +3V_S5 SDA1/GPIO228 BA11 SMB_LAN_DAT
[33] EC_A20GATE SMB_LAN_DAT [24,28,32] +3V_S5
+1.8V_S5 RSMRST# *E@0.1U/10V_4X EC_EXT_SCI# AN5 LPC_PME_L/GEVENT3_L +3V_S5
[33] EC_EXT_SCI#
R218 47K_4 GEVENT23# AL7 LPC_SMI_L/GEVENT23_L +3V_S5 +3V GPIO49 AP27
C280 TP23 +3V GPIO50 AY28 BOARD_ID8 SMB_LAN_CLK 2.2K_4 R475
+3V GPIO51 BA28 BOARD_ID3
1U/6.3V_4X AP15 AC_PRES/IR_RX0/GEVENT16_L+3V_S5 +3V DEVSLP[0]/GPIO55 AV23 TP34 SMB_LAN_DAT 2.2K_4 R476
AV13 IR_TX0/GEVENT21_L +3V_S5 +3V GPIO57 AP21 APU_ODD_EN
APU_ODD_EN [31]
BA9 IR_TX1/GEVENT6_L +3V_S5 +3V GPIO58 BA26 BOARD_ID4
BA10 IR_RX1/GEVENT20_L +3V_S5 +3V DEVSLP[1]/GPIO59 AV19 BOARD_ID9
+3V_S5 BOARD_ID5 AV15 IR_LED_L/LLB_L/GPIO184 +3V_S5 +3V GPIO64 AY27
PE_GPIO0 [22]
+3V SPKR/GPIO66 BA27 PCBEEP
PCBEEP [27]
[26] PCIE_CLKREQ#_LAN
PCIE_CLKREQ#_LAN AU29 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60 +3V +3V GPIO68 AU21
PE_GPIO1 [22]
[28] PCIE_CLKREQ#_WLAN
PCIE_CLKREQ#_WLAN AW29 CLK_REQ1_L/GPIO61 +3V +3V GPIO69 AY26 BOARD_ID6 BOARD_ID[1:11]
BOARD_ID[1:11] [8,27,32]
R508 AR27 CLK_REQ2_L/GPIO62 +3V +3V GPIO70 AV21 BOARD_ID7
10K_4 CLK_REQ3# AV27 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63 +3V +3V GPIO71 AM21 BOARD_ID10
[13] PCIE_CLKREQ#_GPU
PCIE_CLKREQ#_GPU R474 EV@0_4 PCIE_CLKREQ#_GPU_R AY29 CLK_REQG_L/GPIO65/OSCIN +3V +3V_S5 GPIO174 BA3 BOARD_ID11
SYS_RST#
[23,33] USB_NORMAL_OC# USB_NORMAL_OC# R489 0_4 USB_NORMAL_OC#_R AY8 USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L +3V_S5 +3V_S5 GEVENT2_L AV17 GEVENT2# GEVENT2# [9]
1

[23,33] USB_SC_OC# USB_SC_OC# R469 0_4 USB_SC_OC#_R AW1 USB_OC1_L/TDI/GEVENT13_L +3V_S5 +3V_S5 GEVENT4_L BA4
G3 ODD_PRSNT# AV1 USB_OC2_L/TCK/GEVENT14_L +3V_S5 +3V_S5 GEVENT7_L AR15 GEVENT7# TP28 +3V
[31] ODD_PRSNT#
*SHORT_PAD [23,33] USB_DB_OC# USB_DB_OC# R471 0_4 USB_DB_OC#_R AY1 USB_OC3_L/TDO/GEVENT15_L +3V_S5 +3V_S5 GEVENT10_L AP17
+3V_S5 GEVENT11_L AP11 GEVENT11# TP30
2

RevA 1025 Add USB_DB_OC# ACZ_BCLK_R AN2 AZ_BITCLK +3V_S5 GEVENT17_L AN8 ODD_MD#
ODD_MD# [31]
ACZ_SDOUT_R AN1 AZ_SDOUT +3V_S5 BLINK/GEVENT18_L AU17 GEVENT18# TP27 R481 Net GPIO Function I/O Power Well DOS
C 5 6 ACZ_SDIN0 AK2 AZ_SDIN0/GPIO167 +3V_S5 GEVENT22_L BA6
RevA 1023 ODD_MD# CRB assign GEVENT17 10K_4 C
4 7 ACZ_SDIN1 AK1 AZ_SDIN1/GPIO168
HDaudio 3 8 ACZ_SDIN2 AM1 AZ_SDIN2/GPIO169 +3V GENINT1_L/GPIO32 BA29 PASSWDCLR PE_PWRGD GPIO33 DGPU_PWRGD I +3.3V "0->1"
interface 2 9 ACZ_SDIN3 AL2 AZ_SDIN3/GPIO170 +3V GENINT2_L/GPIO33 AP23 R200 0_4
PE_PWRGD [33,40,41]

1
are 1 10 ACZ_SYNC_R AM2 AZ_SYNC

+3V_S5 ACZ_RST#_R AL1 AZ_RST_L +3V FANOUT0/GPIO52 AV31 BOARD_ID1 G2 PE_GPIO0 GPIO64 DGPU_RST# O +3.3V "0->1"
R462 *10KX8 +3V FANIN0/GPIO56 AU31 BOARD_ID2 *SHORT_PAD

2
+3V_S5 R216 *1K_4 APU_TEST2 R195 *15K_4 32K_X1 AJ2 X32K_X1 PE_GPIO1 GPIO68 DGPU_PWREN O +3.3V "0->1"
R215 *1K_4 APU_TEST1 R194 *15K_4
R461 20M_4 RTCCLK AV11
RTC_CLK [9,33]
R214 *1K_4 APU_TEST0 R193 *15K_4 32K_X2 AJ1 X32K_X2
FT3 REV 0.53

1 4 FT3
NEED TO CHANGE P/N 2 3
AMD recomanded 15pF
Debug Only C632
Y4
32.768KHZ_10 C633
15P/50V_4C 15P/50V_4C

USE GROUND GUARD FOR 32K_X1 AND 32K_X2

+3V R189 10K_4 PCIE_CLKREQ#_LAN

R188 10K_4 PCIE_CLKREQ#_WLAN

R472 10K_4 PCIE_CLKREQ#_GPU_R

R203 10K_4 CLK_REQ3# CLK Source GPP_Clk Clk_Req GPIO


R202 ZRP@10K_4APU_ODD_EN
GFX GFX_CLKP/N Clk_ReqG GPIO65
RevA 1025 Add 10K PU to +3V
B Lan GPP_CLK0P/N Clk_Req0 GPIO60 Azalia <ADO> To Azalia Local Temp <THM> B

Rset(Kohm)=0.0012T*T-0.9308T+96.147
WLan GPP_CLK1P/N Clk_Req1 GPIO61
ACZ_SDOUT_R R159 33_4
ACZ_SDOUT [27]
+3V_S5 R490 10K_4 PWR_BTN# R513 EV@24.9K/F_4
ACZ_SYNC_R R156 33_4
ACZ_SYNC [27]
R180 10K_4 PCIE_WAKE# U26
ACZ_BCLK_R R158 33_4 R484 150_4 +3VPCU_HW_SD 5 1 R507 IV@24.9K/F_4
ACZ_BITCLK [27] +3VPCU VCC SET
R497 10K_4 USB_NORMAL_OC#
C664 2
R470 10K_4 USB_SC_OC# C235 *22P/50V_4N GND
0.1U/16V_4Y
R468 10K_4 ODD_PRSNT# 4 3
HYST OT# S5_ON [13,33,35]
ACZ_RST#_R R157 33_4
ACZ_RST# [27]
R212 10K_4 ODD_MD# HYST=VCC for 10 G708T1U
ACZ_SDIN0 ACZ_SDIN0 [27] degree Hys. R511 *470K_4 +3VPCU
R602 10K_4 USB_DB_OC#
HYST=GND for 30
degree Hys.
RevB 1224 Add USB/B OC# Pin PU

FAN Control <THM> Local Temp <THM>


S5_ON

+5V VIN +5VPCU

3
+5V Q30B
R422 *10K_4 5
+3V
40 MIL FANPWR = 1.6*VSET
CN11
40 MIL *2N7002KDW_115MA
U5 [33] FANSIG1 FANSIG1 R549 R552 R548

4
3

C54 2.2U/6.3V_4X 2 3 +5V_FAN U32 *IV@NTC_470K_4 *EV@NTC_470K_4


VIN VO 5 1 2 1 8 *499K/F_4
1 GND 6 2 1 OUT VCC
A /FON GND 3 A
7 Q28 2 7
1

4 GND 8 C49 C53 C589 *MMBT2222A_600MA 1 IN- 2 OUT


[33] VFAN1 VSET GND VFAN1 3 6
APE8872M 2.2U/10V_6X 0.01U/25V_4X *0.01U/25V_4X 85205-0300L 1 IN+ 2 IN-
+5V_FAN R531 *100K_4 4 5 R556 R553
GND 2 IN+
*IV@1M_4 *EV@1M_4
D22 2 1 FANSIG1 *LM358 R545

6
*VPORT 0603 220K-V05
RevB 1222 Change for EOD R532 R533 R546 *499K/F_4
Q30A
D2 2 1 +5V_FAN *100K_4 *162K/F_4 *48.7K/F_4 2 Quanta Computer Inc.
*VPORT 0603 220K-V05 *2N7002KDW_115MA
PROJECT :BD9

1
Size Document Number Rev
A1A
APU 5/6(ACPI/SD/AZ/GPIO/RTC/MISC)
Date: Tuesday, December 25, 2012 Sheet 7 of 41
5 4 3 2 1
5 4 3 2 1

08
U22E
CLK/SATA/USB/SPI/LPC
BA14 SATA_TX0P USBCLK/14M_25M_48M_OSC W4 TP17
[31] SATA_TXP0 AY14 SATA_TX0N
[31] SATA_TXN0 AG4 USB_ZVSS R131 11.8K/F_6
SATA HDD BA16 SATA_RX0N
USB_ZVSS

[31] SATA_RXN0 AY16 AL4 USBP0+


SATA_RX0P USB_HSD0P USBP0+ [23]
[31] SATA_RXP0 AL5 USBP0-
USB_HSD0N USBP0- [23] To USB 2.0 Daughter/B
AY19 SATA_TX1P
[31] SATA_TXP1 BA19 AJ4 USBP1+
SATA_TX1N USB_HSD1P USBP1+ [23]
[31] SATA_TXN1 AJ5 USBP1-
SATA ODD USB_HSD1N USBP1- [23] To USB 2.0 Daughter/B
AY17
[31]
[31]
SATA_RXN1
SATA_RXP1
BA17
SATA_RX1N
SATA_RX1P USB_HSD2P AG7
RevA 1023 Add USBP1 for BD9
HUB1
USB_HSD2N AG8
R170 1K/F_4 SATA_CALRN AR19 SATA_ZVSS
R169 1K/F_4 SATA_CALRP AP19 SATA_ZVDD_095 USB_HSD3P AG1
+0.95V
D USB_HSD3N AG2 D

TP41 SATA_LED# BA30 SATA_ACT_L/GPIO67 +3V USB_HSD4P AF1 USBP4+


USBP4+ [25]
USB_HSD4N AF2 USBP4- Touch Screen
USBP4- [25]
AY12 SATA_X1
USB_HSD5P AE1 USBP5+
USBP5+ [29]
Integrated Clock Mode: USB_HSD5N AE2 USBP5- Card Reader
USBP5- [29]
Leave unconnected.
BA12 SATA_X2 USB_HSD6P AD1 USBP6+_CCD
USBP6+_CCD [30]
HUB2
USB_HSD6N AD2 USBP6-_CCD CCD on LVDS
USBP6-_CCD [30]
CLK_PCIE_VGAP RP1 2 1 0X2 INT_CLK_PCIE_VGAP U4 GFX_CLKP USB_HSD7P AC1 USBP7+
[12] CLK_PCIE_VGAP USBP7+ [28]
CLK_PCIE_VGAN 4 3 INT_CLK_PCIE_VGAN U5 GFX_CLKN USB_HSD7N AC2 USBP7- WLAN
[12] CLK_PCIE_VGAN USBP7- [28]
Reference GND [26] CLK_PCIE_LANP
CLK_PCIE_LANP RP2 2 1 0X2 INT_CLK_PCIE_LANP AC8 GPP_CLK0P USB_HSD8P AB1 USBP8+
USBP8+ [23]
Do not change layer [26] CLK_PCIE_LANN
CLK_PCIE_LANN 4 3 INT_CLK_PCIE_LANN AC10 GPP_CLK0N USB_HSD8N AB2 USBP8-
USBP8- [23] USB3.0/2.0 S&C
and cross plane [28] CLK_PCIE_WLANP
CLK_PCIE_WLANP RP3 2 1 0X2 INT_CLK_PCIE_WLANP AE4 GPP_CLK1P USB_HSD9P AA1 USBP9+
USBP9+ [23]
HUB3
CLK_PCIE_WLANN 4 3 INT_CLK_PCIE_WLANN AE5 GPP_CLK1N USB_HSD9N AA2 USBP9- USB2.0/3.0 w/o S&C
[28] CLK_PCIE_WLANN USBP9- [23]
Integrated Clock Mode: AC4 GPP_CLK2P USB_SS_ZVSS AE10 USBSS_CALRN R124 1K/F_4
Leave unconnected. AC5 GPP_CLK2N USB_SS_ZVDD_095_USB3_DUAL AE8 USBSS_CALRP R125 1K/F_4 +0.95V_DUAL
Cardreader pass through PCIE
Leave unconnected. AA5 GPP_CLK3P USB_SS_0TXP T2 USB3_TXP0
USB3_TXP0 [23]
C627 15P/50V_4C 48M_X1 AA4 GPP_CLK3N USB_SS_0TXN T1 USB3_TXN0
USB3_TXN0 [23]
USB3.0 S&C

2
AP13 X14M_25M_48M_OSC USB_SS_0RXP V2 USB3_RXP0
USB3_RXP0 [23]
Y3 USB_SS_0RXN V1 USB3_RXN0
USB3_RXN0 [23]
RevB 1222 Change cap value for vendor suggestion 48MHZ_15 R457 N2 X48M_X1
R1 USB3_TXP1
1M_4 USB_SS_1TXP
USB3_TXP1 [23]
USB_SS_1TXN R2 USB3_TXN1
USB3_TXN1 [23]
USB3.0 Port 2

4
C623 15P/50V_4C 48M_X2 N1 W1 USB3_RXP1
X48M_X2 USB_SS_1RXP
USB_SS_1RXN W2 USB3_RXN1
USB3_RXP1
USB3_RXN1
[23]
[23]
W25Q32BVSSIG:AKE391P0N00
R178 0_4
[28]
[33]
PCLK_DEBUG
PCLK_591
R164 22_4 W25Q64FVSSIQ:AKE3EFP0N07
+3V_S5
[9] LPC_CLK0
LPC_CLK0 R172 22_4 LPC_CLK0_R AY2 LPCCLK0 +3V
C [9] LPC_CLK1
LPC_CLK1 R167 22_4 LPC_CLK1_R AW2 LPCCLK1 +3V +3V SPI_CLK/GPIO162 AU7 FCH_SPI_CLK_R R190 33_4 FCH_SPI_CLK C
+3V SPI_CS1_L/GPIO165 AW9 FCH_SPI_CS0#_R R197 0_4 FCH_SPI_CS0#
[28,33] LAD0
LAD0 AT2 LAD0 +3V_S5 +3V SPI_CS2_L/GPIO166 AR4 TP26 R517 10K_4
[28,33] LAD1
LAD1 AT1 LAD1 +3V_S5 +3V_S5 SPI_DO/GPIO163 AR11 FCH_SPI_SO_R R199 0_4 FCH_SPI_SO
[28,33] LAD2
LAD2 AR2 LAD2 +3V_S5 +3V_S5 SPI_DI/GPIO164 AR7 FCH_SPI_SI
[28,33] LAD3
LAD3 AR1 LAD3 +3V_S5 +3V_S5 SPI_HOLD_L/GEVENT9_L AU11 SPI_HOLD# U30
LFRAME# AP2 LFRAME_L +3V_S5 +3V_S5 SPI_WP_L/GPIO161 AU9 FCH_SPI_WP FCH_SPI_CS0# 1 8 R520
[9,28,33] LFRAME# [33] FCH_SPI_CS0# CE# VDD
TP25 AP1 LDRQ0_L +3V_S5 FCH_SPI_CLK 6 10K_4
[33] FCH_SPI_CLK SCK
SERIRQ AV29 SERIRQ/GPIO48 +3V double check FCH_SPI_SO 5
[33] SERIRQ [33] FCH_SPI_SO SI
[33] CLKRUN#
CLKRUN# AP25 LPC_CLKRUN_L +3V [33] FCH_SPI_SI
FCH_SPI_SI R519 0_4 FCH_SPI_SI_R 2 7 SPI_HOLD#
SO HOLD#
LPCPD# AV2 +3V_S5
For EMI [33] LPCPD# LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L

FT3 REV 0.53


3
WP# VSS
4
+3V_S5 R495 10K_4 C687 C684
FT3 *22P/50V_4N W25Q32BVSSIG 0.1U/10V_4X
PCLK_DEBUG C251 *15P/50V_4C

PCLK_591 C248 *15P/50V_4C


+3V_S5 R524 10K_4 FCH_SPI_WP
RevB 1225 Change from 8M to 4M

BOARD_ID[1:11]
[7,27,32] BOARD_ID[1:11]

R165 UMA@10K_4 BOARD_ID1 R171 EV@10K_4


BOARD ID SETTING +3V
R163 *10K_4 BOARD_ID2 R160 10K_4

Board ID ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 ID10 ID11 ID12 ID13 R510 U3@10K_4 BOARD_ID3 R501 U2@10K_4

R491 *MTN@10K_4 BOARD_ID4 R485 BD9@10K_4


B UMA SKU H B
PX SKU L R492 KBLED@10K_4 BOARD_ID6 R486 *NKBLED@10K_4

VRAM 1GHz H R187 N-Brand@10K_4 BOARD_ID7 R168 *ONKYO@10K_4


VRAM 900M L
R509 NHM@10K_4 BOARD_ID8 R500 HM@10K_4
USB3.0 H
USB2.0 L R198 10K_4 BOARD_ID9 R184 *10K_4 RevC 0130 Change Board ID 9 for Harman-Kardon
14" MTN H R186 Metal@10K_4 BOARD_ID10 R201 Texture@10K_4 Stuff R198, Remove R184
17" BD9 L
W/O S&C H
W S&C L R487 *10K_4 BOARD_ID11 R480 10K_4
+3V_S5

N-METAL (W/O KBLED) H R192 NS&C@10K_4 BOARD_ID5 R179 S&C@10K_4


Always PU METAL (W/ KBLED) L
RevB 1221 Modify Board ID
N-Brand H
Always PU Brand (ONKYO) L
W/O HDMI H
W HDMI L
N-Brand H
RevC 0130 Change Board ID setting Brand(Harman/Kardon) L
Metal/IMR H
TEXTURE L
RSVD H
Reserve PD RSVD L

A A

Quanta Computer Inc.


PROJECT :BD9
Size Document Number Rev
APU 6/7(CLK/SATA/USB/SPI) A1A

Date: Wednesday, January 30, 2013 Sheet 8 of 41


5 4 3 2 1
5 4 3 2 1

STRAPS PINS
09
D D

+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5

R182 R166 R162 R217 R213


*10K_4 10K_4 10K_4 10K_4 *10K_4
+1.8V_S5 +1.8V_S5
LPC_CLK0
[8] LPC_CLK0
LPC_CLK1
[8] LPC_CLK1
LFRAME#
[8,28,33] LFRAME#
RTC_CLK R512
[7,33] RTC_CLK
GEVENT2# D29 *1SS355_100MA 10K_4
C
[7] GEVENT2# [7] SYS_RST# C
C674
*0.1U/10V_4X

5
U27

R183 R173 R161 R196 R191 VRM_PWRGD D32 1SS355_100MA 2 4 R502 *0_4 FCH_PWRGD
[38] VRM_PWRGD FCH_PWRGD [7]
2K/F_4 *2K/F_4 *2K/F_4 *2.2K_4 2.2K_4 *SN74LVC1G17DCKR
C677

3
1U/10V_6X

R506 0_4
MPWROK
REQUIRED [33] MPWROK
D28 1SS355_100MA
STRAPS

LPC_CLK0 LPC_CLK1 LFRAME# RTC_CLK GEVENT2# [33,39] MAINON


D30 *1SS355_100MA

PULL BOOT Internal SPI Normal SPI


Fail Timer CLKGEN ROM Power Timing Voltage
HIGH ENABLE ENABLED ENABLE 1.8V
DEFAULT DEFAULT DEFAULT

BOOT Internal Normal SPI


PWRGD CIRCUIT
B B
PULL Fail Timer CLKGEN LPC Power Timing Voltage
DISABLE DISABLED ROM DISABLE 3.3V
LOW
DEFAULT DEFAULT

A A

Quanta Computer Inc.


PROJECT :BD9
Size Document Number Rev
APU 7/7(STRAP & PWRGD) A1A

Date: Tuesday, December 25, 2012 Sheet 9 of 41


5 4 3 2 1
5 4 3 2 1

DDR_STD(DDR)
[4,11] M_A_A[15:0]
M_A_A[15:0]
M_A_A0
M_A_A1
M_A_A2
98
97
96
JDIM2A

A0
A1
DQ0
DQ1
5
7
15
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ[0..63]
M_A_DQ[0..63] [4,11]
+1.5VSUS

75
76
JDIM2B

VDD1 VSS16
44
48
10
M_A_A3 95 A2 DQ2 17 M_A_DQ3
2.48A 81 VDD2 VSS17 49
M_A_A4 92 A3 DQ3 4 M_A_DQ4 82 VDD3 VSS18 54
M_A_A5 91 A4 DQ4 6 M_A_DQ5 87 VDD4 VSS19 55
M_A_A6 90 A5 DQ5 16 M_A_DQ6 88 VDD5 VSS20 60
M_A_A7 86 A6 DQ6 18 M_A_DQ7 93 VDD6 VSS21 61
D M_A_A8 89 A7 DQ7 21 M_A_DQ8 94 VDD7 VSS22 65 D
M_A_A9 85 A8 DQ8 23 M_A_DQ9 99 VDD8 VSS23 66
M_A_A10 107 A9 DQ9 33 M_A_DQ10 100 VDD9 VSS24 71
M_A_A11 84 A10/AP DQ10 35 M_A_DQ11 105 VDD10 VSS25 72
M_A_A12 83 A11 DQ11 22 M_A_DQ12 106 VDD11 VSS26 127

PC2100 DDR3 SDRAM SO-DIMM


M_A_A13 119 A12/BC# DQ12 24 M_A_DQ13 111 VDD12 VSS27 128
M_A_A14 80 A13 DQ13 34 M_A_DQ14 112 VDD13 VSS28 133
M_A_A15 78 A14 DQ14 36 M_A_DQ15 117 VDD14 VSS29 134
A15 DQ15 39 M_A_DQ16 118 VDD15 VSS30 138

PC2100 DDR3 SDRAM SO-DIMM


M_A_BS#[2:0] M_A_BS#0 109 DQ16 41 M_A_DQ17 123 VDD16 VSS31 139
[4,11] M_A_BS#[2..0] M_A_BS#1 108 BA0 DQ17 51 M_A_DQ18 124 VDD17 VSS32 144
M_A_BS#2 79 BA1 DQ18 53 M_A_DQ19 VDD18 VSS33 145
M_A_CS#0 114 BA2 DQ19 40 M_A_DQ20 199 VSS34 150
[4] M_A_CS#0 121 S0# DQ20 42 +3V VDDSPD VSS35 151
M_A_CS#1 M_A_DQ21
[4] M_A_CS#1 101 S1# DQ21 50 77 VSS36 155
M_A_CLKP0 M_A_DQ22
[4] M_A_CLKP0 M_A_CLKN0 103 CK0 DQ22 52 M_A_DQ23 122 NC1 VSS37 156
[4] M_A_CLKN0 102 CK0# DQ23 57 125 NC2 VSS38 161
M_A_CLKP1 M_A_DQ24
[4] M_A_CLKP1 104 CK1 DQ24 59 NCTEST VSS39 162
M_A_CLKN1 M_A_DQ25
[4] M_A_CLKN1 73 CK1# DQ25 67 198 VSS40 167
M_A_CKE0 M_A_DQ26 [4,11] M_A_EVENT#
[4] M_A_CKE0 74 CKE0 DQ26 69 30 EVENT# VSS41 168
M_A_CKE1 M_A_DQ27 [4,11] M_A_RST#
[4] M_A_CKE1 115 CKE1 DQ27 56 RESET# VSS42 172
M_A_CAS# M_A_DQ28
[4,11] M_A_CAS# 110 CAS# DQ28 58 VSS43 173
M_A_RAS# M_A_DQ29 C27 *E@0.1U/10V_4X
[4,11] M_A_RAS# M_A_WE# 113 RAS# DQ29 68 M_A_DQ30 1 VSS44 178
[4,11] M_A_WE# W E# DQ30 +0.75V_VREF_DQ VREF_DQ VSS45
R499 10K_4 DIMM0_SA0 197 70 M_A_DQ31 126 179
SA0 DQ31 +0.75V_VREF_CA VREF_CA VSS46
R504 10K_4 DIMM0_SA1 201 129 M_A_DQ32 184
SMB_RUN_CLK 202 SA1 DQ32 131 M_A_DQ33 VSS47 185
[7,11] SMB_RUN_CLK SCL DQ33 VSS48
SMB_RUN_DAT 200 141 M_A_DQ34 2 189
[7,11] SMB_RUN_DAT SDA DQ34 VSS1 VSS49
DQ35
143 M_A_DQ35 C5329 placed between JDIM1 and JDIM2 3
VSS2 VSS50
190
M_A_ODT0 116 130 M_A_DQ36 8 195

(204P)
[4] M_A_ODT0 ODT0 DQ36 VSS3 VSS51
Reserve ICT test point M_A_ODT1 120 132 M_A_DQ37 9 196
C [4] M_A_ODT1 ODT1 DQ37 140 M_A_DQ38 13 VSS4 VSS52 C
M_A_DM[7:0] M_A_DM0 11 DQ38 142 M_A_DQ39 14 VSS5
[4,11] M_A_DM[7..0] M_A_DM1 28 DM0 DQ39 147 M_A_DQ40 19 VSS6
M_A_DM2 46 DM1 DQ40 149 M_A_DQ41 20 VSS7

(204P)
M_A_DM3 63 DM2 DQ41 157 M_A_DQ42 +1.5VSUS 25 VSS8
M_A_DM4 136 DM3 DQ42 159 M_A_DQ43 26 VSS9 203
DM4 DQ43 VSS10 VTT1 +SMDDR_VTERM
M_A_DM5 153 146 M_A_DQ44 31 204
M_A_DM6 170 DM5 DQ44 148 M_A_DQ45 32 VSS11 VTT2
M_A_DM7 187 DM6 DQ45 158 M_A_DQ46 +0.75V_VREF_CA R111 +SMDDR_VREF 37 VSS12 205
DM7 DQ46 160 M_A_DQ47 38 VSS13 GND 206
DQ47 1K/F_4 VSS14 GND
M_A_DQSP[7:0] M_A_DQSP0 12 163 M_A_DQ48 43
[4,11] M_A_DQSP[7:0] 29 DQS0 DQ48 165 VSS15
M_A_DQSP1 M_A_DQ49
M_A_DQSP2 47 DQS1 DQ49 175 M_A_DQ50 R122 0_6 MEM_VREFCA_SUS R123 *0_6
M_A_DQSP3 64 DQS2 DQ50 177 M_A_DQ51 DDRSK-20401-TP8D
M_A_DQSP4 137 DQS3 DQ51 164 M_A_DQ52
M_A_DQSP5 154 DQS4 DQ52 166 M_A_DQ53
M_A_DQSP6 171 DQS5 DQ53 174 M_A_DQ54 R112 C150
M_A_DQSP7 188 DQS6 DQ54 176 M_A_DQ55
DQS7 DQ55 1K/F_4 0.47U/6.3V_4X
M_A_DQSN[7:0] M_A_DQSN0 10 181 M_A_DQ56 R27 *0_4
[4,11] M_A_DQSN[7:0] DQS#0 DQ56
M_A_DQSN1 27 183 M_A_DQ57
M_A_DQSN2 45 DQS#1 DQ57 191 M_A_DQ58
M_A_DQSN3 62 DQS#2 DQ58 193 M_A_DQ59 R30 *0_4
M_A_DQSN4 135 DQS#3 DQ59 180 M_A_DQ60 +APU_M_VREFDQ_SUS
M_A_DQSN5 152 DQS#4 DQ60 182 M_A_DQ61
M_A_DQSN6 169 DQS#5 DQ61 192 M_A_DQ62 +3V_S5
M_A_DQSN7 186 DQS#6 DQ62 194 M_A_DQ63 +1.5VSUS
DQS#7 DQ63

DDRSK-20401-TP8D C18 R17


*0_4

2
B R21 U2 *0.1U/10V_4X B
1K/F_4 +0.75V_VREF_DQ +SMDDR_VREF
+APU_M_VREFDQ_SUS 4
DQ_OP-
- V+
1 OP_OUT R18 *0_6 R24 *0_6

R20 *0_6 DQ_OP+ 3


+ V-
*MCP6001RT-E/OT

5
C16 C17
Place these Caps near So-Dimm0. R23 C19 0.1U/10V_4X 0.1U/10V_4X
+1.5VSUS 1K/F_4 0.47U/6.3V_4X R19 0_6
+0.75V_VREF_DQ

R26
*10K_4
C78 C62 C119 C88 C102 C87 C61 C72 C91 C137 C93 C127 C123 C13 C14

10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X *10U/6.3V_6X 1U/10V_4X 1U/10V_4X 1U/10V_4X 1U/10V_4X 10U/6.3V_6X 10U/6.3V_6X 0.1U/10V_4X 1000P/50V_4X

RevB 1219 Change for EOD *0.1U/10V_4X C22

+1.5VSUS
EMI Suggestion
+3V +SMDDR_VTERM
+0.75V_VREF_CA
A A

C238 C242 C269 C263 C264 C270 C274 C261 C76 C75 C51 C52 C74 C70 C83
C159 C160
2.2U/10V_6X 0.1U/10V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 10U/6.3V_6X *10U/6.3V_6X ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N
0.1U/10V_4X 1000P/50V_4X

Quanta Computer Inc.


RevB 1222 Change for EOD PROJECT : BD9
Size Document Number Rev
DDR3 DIMM-0 A1A

Date: Tuesday, December 25, 2012 Sheet 10 of 41


5 4 3 2 1
5 4 3 2 1

DDR_STD(DDR)
[4,10] M_A_A[15:0]
M_A_A[15:0]
M_A_A0
M_A_A1
M_A_A2
98
97
96
JDIM1A

A0
A1
DQ0
DQ1
5
7
15
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ[0..63]
M_A_DQ[0..63] [4,10]
+1.5VSUS

75
76
JDIM1B

VDD1 VSS16
44
48
11
M_A_A3 95 A2 DQ2 17 M_A_DQ3
2.48A 81 VDD2 VSS17 49
M_A_A4 92 A3 DQ3 4 M_A_DQ4 82 VDD3 VSS18 54
M_A_A5 91 A4 DQ4 6 M_A_DQ5 87 VDD4 VSS19 55
M_A_A6 90 A5 DQ5 16 M_A_DQ6 88 VDD5 VSS20 60
M_A_A7 86 A6 DQ6 18 M_A_DQ7 93 VDD6 VSS21 61
D M_A_A8 89 A7 DQ7 21 M_A_DQ8 94 VDD7 VSS22 65 D
M_A_A9 85 A8 DQ8 23 M_A_DQ9 99 VDD8 VSS23 66
M_A_A10 107 A9 DQ9 33 M_A_DQ10 100 VDD9 VSS24 71
M_A_A11 84 A10/AP DQ10 35 M_A_DQ11 105 VDD10 VSS25 72
M_A_A12 83 A11 DQ11 22 M_A_DQ12 106 VDD11 VSS26 127

PC2100 DDR3 SDRAM SO-DIMM


M_A_A13 119 A12/BC# DQ12 24 M_A_DQ13 111 VDD12 VSS27 128
M_A_A14 80 A13 DQ13 34 M_A_DQ14 112 VDD13 VSS28 133
M_A_A15 78 A14 DQ14 36 M_A_DQ15 117 VDD14 VSS29 134
A15 DQ15 39 M_A_DQ16 118 VDD15 VSS30 138

PC2100 DDR3 SDRAM SO-DIMM


M_A_BS#[2:0] M_A_BS#0 109 DQ16 41 M_A_DQ17 123 VDD16 VSS31 139
[4,10] M_A_BS#[2..0] M_A_BS#1 108 BA0 DQ17 51 M_A_DQ18 124 VDD17 VSS32 144
M_A_BS#2 79 BA1 DQ18 53 M_A_DQ19 VDD18 VSS33 145
M_A_CS#2 114 BA2 DQ19 40 M_A_DQ20 199 VSS34 150
[4] M_A_CS#2 121 S0# DQ20 42 +3V VDDSPD VSS35 151
M_A_CS#3 M_A_DQ21
[4] M_A_CS#3 101 S1# DQ21 50 77 VSS36 155
M_A_CLKP2 M_A_DQ22
[4] M_A_CLKP2 M_A_CLKN2 103 CK0 DQ22 52 M_A_DQ23 122 NC1 VSS37 156
[4] M_A_CLKN2 102 CK0# DQ23 57 125 NC2 VSS38 161
M_A_CLKP3 M_A_DQ24
[4] M_A_CLKP3 104 CK1 DQ24 59 NCTEST VSS39 162
M_A_CLKN3 M_A_DQ25
[4] M_A_CLKN3 73 CK1# DQ25 67 198 VSS40 167
M_A_CKE2 M_A_DQ26 [4,10] M_A_EVENT#
[4] M_A_CKE2 74 CKE0 DQ26 69 30 EVENT# VSS41 168
M_A_CKE3 M_A_DQ27 [4,10] M_A_RST#
[4] M_A_CKE3 115 CKE1 DQ27 56 RESET# VSS42 172
M_A_CAS# M_A_DQ28
[4,10] M_A_CAS# 110 CAS# DQ28 58 VSS43 173
M_A_RAS# M_A_DQ29
[4,10] M_A_RAS# M_A_WE# 113 RAS# DQ29 68 M_A_DQ30 1 VSS44 178
[4,10] M_A_WE# W E# DQ30 +0.75V_VREF_DQ VREF_DQ VSS45
R176 10K_4 DIMM1_SA0 197 70 M_A_DQ31 126 179
+3V SA0 DQ31 +0.75V_VREF_CA VREF_CA VSS46
R177 10K_4 DIMM1_SA1 201 129 M_A_DQ32 184
SMB_RUN_CLK 202 SA1 DQ32 131 M_A_DQ33 VSS47 185
[7,10] SMB_RUN_CLK SCL DQ33 VSS48
SMB_RUN_DAT 200 141 M_A_DQ34 2 189
[7,10] SMB_RUN_DAT SDA DQ34 VSS1 VSS49
143 M_A_DQ35 3 190
M_A_ODT2 116 DQ35 130 M_A_DQ36 8 VSS2 VSS50 195

(204P)
[4] M_A_ODT2 ODT0 DQ36 VSS3 VSS51
Reserve ICT test point M_A_ODT3 120 132 M_A_DQ37 9 196
C [4] M_A_ODT3 ODT1 DQ37 140 M_A_DQ38 13 VSS4 VSS52 C
M_A_DM[7:0] M_A_DM0 11 DQ38 142 M_A_DQ39 14 VSS5
[4,10] M_A_DM[7..0] M_A_DM1 28 DM0 DQ39 147 M_A_DQ40 19 VSS6
M_A_DM2 46 DM1 DQ40 149 M_A_DQ41 20 VSS7

(204P)
M_A_DM3 63 DM2 DQ41 157 M_A_DQ42 25 VSS8
M_A_DM4 136 DM3 DQ42 159 M_A_DQ43 26 VSS9 203
DM4 DQ43 VSS10 VTT1 +SMDDR_VTERM
M_A_DM5 153 146 M_A_DQ44 31 204
M_A_DM6 170 DM5 DQ44 148 M_A_DQ45 32 VSS11 VTT2
M_A_DM7 187 DM6 DQ45 158 M_A_DQ46 37 VSS12 205
DM7 DQ46 160 M_A_DQ47 38 VSS13 GND 206
M_A_DQSP[7:0] M_A_DQSP0 12 DQ47 163 M_A_DQ48 43 VSS14 GND
[4,10] M_A_DQSP[7:0] 29 DQS0 DQ48 165 VSS15
M_A_DQSP1 M_A_DQ49
M_A_DQSP2 47 DQS1 DQ49 175 M_A_DQ50
M_A_DQSP3 64 DQS2 DQ50 177 M_A_DQ51 DDRSK-20401-TP4B
M_A_DQSP4 137 DQS3 DQ51 164 M_A_DQ52
M_A_DQSP5 154 DQS4 DQ52 166 M_A_DQ53
M_A_DQSP6 171 DQS5 DQ53 174 M_A_DQ54
M_A_DQSP7 188 DQS6 DQ54 176 M_A_DQ55
M_A_DQSN[7:0] M_A_DQSN0 10 DQS7 DQ55 181 M_A_DQ56
[4,10] M_A_DQSN[7:0] DQS#0 DQ56
M_A_DQSN1 27 183 M_A_DQ57
M_A_DQSN2 45 DQS#1 DQ57 191 M_A_DQ58
M_A_DQSN3 62 DQS#2 DQ58 193 M_A_DQ59
M_A_DQSN4 135 DQS#3 DQ59 180 M_A_DQ60
M_A_DQSN5 152 DQS#4 DQ60 182 M_A_DQ61
M_A_DQSN6 169 DQS#5 DQ61 192 M_A_DQ62
M_A_DQSN7 186 DQS#6 DQ62 194 M_A_DQ63
DQS#7 DQ63

DDRSK-20401-TP4B

B B

Place these Caps near So-Dimm0.


+1.5VSUS
+0.75V_VREF_DQ

RevB 1219 Change for EOD


C106 C98 C60 C64 C77 C96 C80 C100 C58 C112 C97 C142 C50 C12 C15

10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X *10U/6.3V_6X 1U/10V_4X 1U/10V_4X 1U/10V_4X 1U/10V_4X 10U/6.3V_6X 10U/6.3V_6X 0.1U/10V_4X 1000P/50V_4X

RevB 1219 Change for EOD

+3V +1.5VSUS
EMI Suggestion
+SMDDR_VTERM

A +0.75V_VREF_CA A

C246 C252 C275 C266 C276 C265 C279 C262


C108 C143 C63 C84 C59 C129 C73
2.2U/10V_6X 0.1U/10V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 10U/6.3V_6X *10U/6.3V_6X C167 C161
ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N
0.1U/10V_4X 1000P/50V_4X
Quanta Computer Inc.
RevB 1222 Change for EOD PROJECT : BD9
Size Document Number Rev
DDR3 DIMM-1 A1A

Date: Tuesday, December 25, 2012 Sheet 11 of 41


5 4 3 2 1
<VGA>
PART 1 0F 9
U33A

12
PEG_TXP0 AA38 PCIE_RX0P PCIE_TX0P Y33 CPEG_RXP0 C329 EV@0.1U/10V_4X
[3] PEG_TXP0 PEG_RXP0 [3]
PEG_TXN0 Y37 PCIE_RX0N PCIE_TX0N Y32 CPEG_RXN0 C337 EV@0.1U/10V_4X
[3] PEG_TXN0 PEG_RXN0 [3]

PEG_TXP1 Y35 PCIE_TX1P W33 CPEG_RXP1 C327 EV@0.1U/10V_4X


Mars Power-on sequence
[3] PEG_TXP1 PCIE_RX1P PEG_RXP1 [3]
PEG_TXN1 W36 PCIE_TX1N W32 CPEG_RXN1 C331 EV@0.1U/10V_4X
[3] PEG_TXN1 PCIE_RX1N PEG_RXN1 [3]
1 => +3V_GPU
[3] PEG_TXP2
PEG_TXP2 W38 PCIE_RX2P PCIE_TX2P U33 CPEG_RXP2 C321 EV@0.1U/10V_4X
PEG_RXP2 [3]
2 => +VDDC,+VDDCI,+1.5V_GPU,+0.95V_GPU
PEG_TXN2 V37 PCIE_TX2N U32 CPEG_RXN2 C320 EV@0.1U/10V_4X
[3] PEG_TXN2 PCIE_RX2N PEG_RXN2 [3] 3 => +1.8V_GPU
PEG_TXP3 V35 PCIE_RX3P PCIE_TX3P U30 CPEG_RXP3 C322 EV@0.1U/10V_4X
[3] PEG_TXP3 PEG_RXP3 [3]
PEG_TXN3 U36 PCIE_RX3N PCIE_TX3N U29 CPEG_RXN3 C323 EV@0.1U/10V_4X
[3] PEG_TXN3 PEG_RXN3 [3]

U38 PCIE_RX4P PCIE_TX4P T33


T37 PCIE_RX4N PCIE_TX4N T32

T35 PCIE_TX5P T30


PEG
PCIE_RX5P
R36 PCIE_TX5N T29
PCIE_RX5N
Intel platform: Lane0 ~ Lane15
R38 PCIE_RX6P PCIE_TX6P P33 Brazos platform: Lane12 ~ Lane15
P37 PCIE_TX6N P32
PCIE_RX6N
Comal and Sabine platform: Lane8 ~Lane15
P35 PCIE_RX7P PCIE_TX7P P30 Richland and Kabini platform: Lane0 ~ Lane7
N36 PCIE_RX7N PCIE_TX7N P29

N38 NC_PCIE_RX8P NC_PCIE_TX8P N33

PCI EXPRESS INTERFACE


M37 NC_PCIE_TX8N N32
NC_PCIE_RX8N Power Up Reset Sequence
M35 NC_PCIE_RX9P NC_PCIE_TX9P N30
L36 NC_PCIE_RX9N NC_PCIE_TX9N N29

+5VRUN/+3VRUN/VDDR3
L38 NC_PCIE_RX10P NC_PCIE_TX10P L33
K37 NC_PCIE_RX10N NC_PCIE_TX10N L32

K35 NC_PCIE_RX11P NC_PCIE_TX11P L30 RUNPWROK


J36 NC_PCIE_RX11N NC_PCIE_TX11N L29

J38 NC_PCIE_RX12P NC_PCIE_TX12P K33 MVDDQ/VDDC/VDDCI


H37 NC_PCIE_TX12N K32
NC_PCIE_RX12N 1.8V_IO/PCIE_VDDC
H35 NC_PCIE_RX13P NC_PCIE_TX13P J33 20ms max
G36 NC_PCIE_RX13N NC_PCIE_TX13N J32
PWRGOOD
100ms min 100ms min
G38 NC_PCIE_RX14P NC_PCIE_TX14P K30
F37 NC_PCIE_RX14N NC_PCIE_TX14N K29

PCIE_RST#(PERSTB)
F35 NC_PCIE_RX15P NC_PCIE_TX15P H33
E37 NC_PCIE_RX15N NC_PCIE_TX15N H32

PCIE Clock
CLOCK
AB35 PCIE_REFCLKP
[8] CLK_PCIE_VGAP
AA36 PCIE_REFCLKN 100us min 100ms max
[8] CLK_PCIE_VGAN
CALIBRATION R251 *EV@1.27K/F_4
Asic in Reset Hardware Reset Sequence DFG Space Ready
PCIE_CALR_TX Y30 R250 EV@1.69K/F_4

R301 EV@10K_4 AH16 TEST_PG PCIE_CALR_RX Y29 R265 EV@1K/F_4 +0.95V_GPU

[22] PERST#_BUF
PERST#_BUF R249 EV@0_4 PERST#_BUF_R AA30 PERSTB Quanta Computer Inc.
C403 EV@Mars_M2
PROJECT : BD9
*E@0.1U/10V_4X Size Document Number Rev
A1A
Mars_M2/ PEG*8
Date: Tuesday, December 25, 2012 Sheet 12 of 41
<VGA>

AD29
MUTI GFX
U33B
PART 2 0F 9

NC_TXCAP_DPA3P AU24 AVDD


DAC1 Analog Power
1.8V@18mA
L35 Mars@BLM15BD121SN1D_300MA
+1.8V_GPU

13
[15] GENIL_CLK GENLK_CLK
AC29 NC_TXCAM_DPA3N AV23
[15] GENIL_VSYNC GENLK_VSYNC
NC_TX0P_DPA2P AT25 C715 C716 C717
AJ21 SWAPLOCKA NC_TX0M_DPA2N AR24 Mars@0.1U/10V_4X Mars@1U/6.3V_4X Mars@4.7U/6.3V_6X
AK21 DPA
SWAPLOCKB
NC_TX1P_DPA1P AU26
NC_TX1M_DPA1N AV25

AR8 NC_DVPCNTL_MVP_0 NC_TX2P_DPA0P AT27 DAC1 Digital Power


AU8 NC_TX2M_DPA0N AR26 1.8V@117mA
NC_DVPCNTL_MVP_1
AP8
DBG_CNTL0
AW8 NC_DVPCNTL_1 NC_TXCBP_DPB3P AR30 VDD1DI L34 Mars@BLM15BD121SN1D_300MA
AR3 NC_TXCBM_DPB3N AT29
NC_DVPCNTL_2
AR1 NC_DVPCLK
AU1 NC_TX3P_DPB2P AV31 C714 C713 C712
DBG_DATA0
AU3 NC_TX3M_DPB2N AU30 Mars@0.1U/10V_4X Mars@1U/6.3V_4X Mars@4.7U/6.3V_6X
DBG_DATA1 DPB
AW3 DBG_DATA2
Q17A EV@2N7002KDW_115MA AP6 NC_TX4P_DPB1P AR32
DBG_DATA3
[24,33] 3ND_MBCLK 6 1 GPU_SMBCLK AW5 DBG_DATA4 NC_TX4M_DPB1N AT31
AU5
DBG_DATA5
AR6 NC_TX5P_DPB0P AT33
DBG_DATA6
R312 1.8V GPIO AW6 DBG_DATA7 NC_TX5M_DPB0N AU32
2

EV@10K/F_4 AU6 Close to ASIC


DBG_DATA8
AT7 DBG_DATA9 NC_TXCCP_DPC3P AU14 VDDC_CT VDDC_CT VDDC_CT
AV7 NC_TXCCM_DPC3N AV13
DBG_DATA10
AN7
+3V_GPU DBG_DATA11
AV9 DBG_DATA12 NC_TX0P_DPC2P AT15
AT9 NC_TX0M_DPC2N AR14 R285 R266 R283
DBG_DATA13
R315 AR10 DBG_DATA14 R_pu EV@8.45K/F_4 R_pu *EV@8.45K/F_4 01000 for Sun R_pu *EV@10K/F_4
AW10 DPC AU16
EV@10K/F_4 DBG_DATA15 NC_TX1P_DPC1P 11001 11000 00000 for Mars
5

AU10 NC_TX1M_DPC1N AV15


DBG_DATA16
AP10 DBG_DATA17 PS_0 PS_1 PS_2
3 4 GPU_SMBDAT AV11 NC_TX2P_DPC0P AT17
[24,33] 3ND_MBDATA DBG_DATA18
AT11 DBG_DATA19 NC_TX2M_DPC0N AR16
Q17B EV@2N7002KDW_115MA AR12 Ca R_pd R286 Ca R_pd R267 Ca R_pd R284
DBG_DATA20
AW12 NC_TXCDP_DPD3P AU20 C420 EV@2K/F_4 C412 EV@4.75K/F_4 C774 C419 EV@4.75K/F_4
DBG_DATA21
AU12 DBG_DATA22 NC_TXCDM_DPD3N AT19 *EV@0.1U/10V_4X *EV@0.1U/10V_4X Mars@0.68U/6.3V_4X EV@0.082U/16V_4X
AP12
DBG_DATA23
NC_TX3P_DPD2P AT21
NC_TX3M_DPD2N AR20
Tempeature function: Connect to EC
GPU_SMBCLK AJ23 DPD NC_TX4P_DPD1P AU22
RevB 1221 Add for Mars
SMBCLK SMBus
GPU_SMBDAT AH23 NC_TX4M_DPD1N AV21
SMBDATA
NC_TX5P_DPD0P AT23
NC_TX5M_DPD0N AR22
+3V_GPU R307 EV@4.7K_4 GPU_SCL AK26 SCL
R292 EV@4.7K_4 GPU_SDA AJ26 I2C
SDA
R AD39
AD37 T20
GENERAL PURPOSE I/O AVSSN#1
AH20 GPIO_0
[15,40] GPU_GPIO0 AH18 AE36
GPIO_1 G
[15] GPU_GPIO1 T22
AN16 GPIO_2 AVSSN#2 AD35
[15] GPU_GPIO2
T7
T6 B AF37
T21
T5 AH17 GPIO_5_AC_BATT AVSSN#3 AE38
AJ17
GPIO_6_TACH DAC1
R573 EV@10K_4 AK17 GPIO_7_BLON HSYNC AC36
GPU_HSYNC [15]
AJ13 VSYNC AC38
[15] GPU_GPIO8 GPIO_8_ROMSO GPU_VSYNC [15]
AH15
[15] GPU_GPIO9 GPIO_9_ROMSI
AJ16 GPIO_10_ROMSCK
[15] GPU_GPIO10 AK16 AB34
GPIO_11 RSET R252 EV@499/F_4
[15] GPU_GPIO11
AL16 GPIO_12
[15] GPU_GPIO12
AM16 AVDD AD34 AVDD
[15] GPU_GPIO13 GPIO_13
T26 AM14 AVSSQ AE34
[7,33,35] S5_ON GPIO_14_HPD2
AM13 GPIO_15_PWRCNTL_0
[40] GFX_CORE_CNTRL1
3

AK14 VDD1DI AC33 VDD1DI


[40] GFX_CORE_CNTRL5 GPIO_16
T3 AG30 GPIO_17_THERMAL_INT VSS1DI AC34
Q34 AN14
GPIO_18
2 GPIO_19_CTF AM17
GPIO_19_CTF
AL13 GPIO_20_PWRCNTL_1 NC#1 V13 T2
[40] GFX_CORE_CNTRL2 AJ14 U13
*ME2N7002E_200MA NC#2 T1 Ra P/N
R577
[15]
[15]
GPU_GPIO21
GPU_GPIO22
AK13
AN13
GPIO_21
GPIO_22_ROMCSB NC_SVI2
NC_SVI2
AC31
AD30
T13
T14 System Memory Aperture size MLPS
[7] PCIE_CLKREQ#_GPU CLKREQB
1

*EV@100K_4 NC#5 AC32 T15 2K CS22002FB19


T8
NC_SVI2 AD32 T19 R_pu R_pd Bits [3:1]
AG32 NC#7 AF32 T17
[40] GFX_CORE_CNTRL3 GPIO_29
AG33 AA29
[40] GFX_CORE_CNTRL4 GPIO_30 NC#8
NC#9 AG21
T12
T4 PS0[3:1] NC 4.75K 000
3.24K CS23242FB09
AJ19 ROMIDCFG[2:0]
GENERICA
AK19 GENERICB NC_TSVSSQ should be tied 3.4K CS23402FB08
AJ20 to GND on Thames/Whistler/Seymour 8.45K 2K 001
[15] GPU_GENERICC
AK20
AJ24
GENERICC
GENERICD
AF33
128M 000
GENERICE NC_TSVSSQ 4.53K CS24532FB08
On Mars only HPD1 and GPIO_14_HPD2 AH26 PS_0 should be tied to GND on 4.53K 2K 010
are available for display hot-plug detection AH24
GENERICF
GENERICG
Thames/Whistler/Seymour 256M 001
4.75K CS24752FB12
PS_0 AM34 PS_0 6.98K 4.99K 011
+1.8V_GPU
AC30
64M 010
T11 CEC_1 4.99K CS24992FB26
Place close to Chip 4.53K 4.99K 100
T23 AK24
HPD1 MLPS
PS_1 AD31 PS_1 Reserved 011
R310 5.62K CS25622FB18
EV@499/F_4 3.24K 5.62K 101
GPU_VREFG AH13 DBG_VREFG PS_2 AG31 PS_2 6.98K CS26982FB01
3.4K 10K 110
R311 C448
AL21
BACO
AD33
8.45K CS28452FB12
EV@249/F_4 R260 *EV@4.7K_4 PX_EN PS_3 PS_3 4.75K NC 111
PS_3 [15]
EV@0.1U/10V_4X
PS_1,PS_2, PS_3 are NC on
Thames/Whistler/Seymour
10K CS31002FB26
DEBUG DDC/AUX DDC1CLK AM26
DDC1DATA AN26
R256 EV@1K_4 AD28
TESTEN
AUX1P AM27
R255 *EV@5.11K/F_4 AUX1N AL27
+3V_GPU
Ca Bits [5:4] P/N MLPS Bit Bits [5:1]
AM23 JTAG_TRSTB DDC2CLK AM19
T29 AN23 AL19
T25 JTAG_TDI DDC2DATA CH4681K9B00 X5R
AK23 JTAG_TCK 680nF 00 CH4681JEB00 X6S PS_0 11001
T28
AL24 AUX2P AN20
T24 JTAG_TMS
AM24 AUX2N AM20
T27 JTAG_TDO
82nF 01 CH3823K1B00 PS_1 11000
NC_DDCCLK_AUX3P AL30
NC_DDCDATA_AUX3N AM30

THERMAL
10nF 10 CH31003KB11 PS_2 01000
NC_DDCCLK_AUX4P AL29
AF29 DPLUS NC_DDCDATA_AUX4N AM29
T16 AG29
T18 DMINUS NC 11 PS_3 11XXX
NC_DDCCLK_AUX5P AN21
NC_DDCDATA_AUX5N AM21
R290 *EV@10K/F_4 AK32
+3V_GPU GPIO_28_FDO
PU:Disable MLPS NC_DDCCLK_AUX6P AK30
PD:Enable MLPS R291 EV@10K/F_4 AL31 NC_DDCDATA_AUX6N AK29
TS_A
1.8V@8mA
DDCVGACLK AJ30
L8 EV@BLM15BD121SN1D_300MA TSVDD AJ32 DDCVGADATA AJ31
+1.8V_GPU TSVDD
AJ33
on-die thermal sensor power C429 C428 C427
TSVSS
Quanta Computer Inc.
EV@10U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X EV@Mars_M2
PROJECT : BD9
Size Document Number Rev
A1A
Mars_M2/ GPIO_DP_CRT_I2C
Date: Wednesday, January 30, 2013 Sheet 13 of 41
<VGA>
14
DPE/DPF/LVDS

U33G
U33I
PART 7 0F 9

1.8V@20mA for Sun PART 9 0F 9 RSVD AK27 R259 *EV@10K/F_4


LVDS CONTROL RSVD AJ27 R258 *EV@10K/F_4

DPEF_VDD18
0.95V@16mA for Sun
0.95V@330mA for Mars DPLL_VDDC AM32 XTALIN AV33 GPU_XTALIN C433 EV@27P/50V_4N
DP_VDDR
TXCBP_DPB3P AK35

2
1
L11 EV@PBY160808T-501Y-N_1.2A DPLL_VDDC AN31 TXCBM_DPB3N AL36
+0.95V_GPU DP_VDDC
R289
EV@1M/F_4 Y2 TX3P_DPB2P AJ38
C434 C431 C430 AN32 EV@27MHZ_10 TX3M_DPB2N AK37
DP_VSSR
EV@10U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X

3
4
XTALOUT AU34 GPU_XTALOUT R288 EV@0_4 C432 EV@27P/50V_4N TX4P_DPB1P AH35
TX4M_DPB1N AJ36

1.8V@90mA for Sun Memory phase-locked loop power. TX5P_DPB0P AG38


1.8V@130mA for Mars Dedicated analog power pin for the memory PLLs. H7 MPLL_PVDD TX5M_DPB0N AH37
1002 AMD FAE suggest 220ohm H8
MPLL_PVDD
NC_TXOUT_U3P AF35

LVTMDP
+1.8V_GPU L38 EV@FCM1608KF-221T05_500MA MPLL_PVDD XO_IN AW34 T31 NC_TXOUT_U3N AG36

AM10 SPLL_PVDD

PLLS/XTAL
C735 C732 C728
EV@10U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X
TXCAP_DPA3P AP34
AN9 XO_IN2 AW35 T30 TXCAM_DPA3N AR34
SPLL_VDDC
TX0P_DPA2P AW37
TX0M_DPA2N AU35
1.8V@75mA for Sun Engine phase-locked loop power. AN10 SPLL_PVSS
1.8V@75mA for Mars Dedicated analog power pin for the engine and UVD PLLs. TX1P_DPA1P AR37
TX1M_DPA1N AU39
+1.8V_GPU L12 EV@BLM15BD121SN1D_300MA SPLL_PVDD
CLKTESTA AK10 CLKTESTA TX2P_DPA0P AP35
AF30 NC_XTAL_PVDD CLKTESTB AL10 CLKTESTB TX2M_DPA0N AR35
C445 C443 C444 AF31
NC_XTAL_PVSS
EV@10U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X NC_TXOUT_L3P AN36
NC_TXOUT_L3N AP37
C447 C446
*EV@0.1U/10V_4X *EV@0.1U/10V_4X
0.95V@100mA for Sun Engine phase-locked loop power.
0.95V@100mA for Mars Dedicated digital power pin for the engine and UVD PLLs.
1002 AMD FAE suggest 120ohm EV@Mars_M2
EV@Mars_M2
R314 R313
+0.95V_GPU L14 EV@BLM15BD121SN1D_300MA SPLL_VDDC *EV@51.1/F_4 *EV@51.1/F_4

C451 C449 C450


EV@10U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X

DPEF_VDD18 R278 *EV@0_4

R277 *EV@0_4

Quanta Computer Inc.


PROJECT : BD9
Size Document Number Rev
A1A
Mars_M2/ XTAL_LVDS
Date: Tuesday, December 25, 2012 Sheet 14 of 41
<VGA> +3V_GPU
15
CONFIGURATION STRAPS -- SEE EACH DATABOOK FOR STRAP DETAILS
R293 *EV@10K/F_4 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
[13,40] GPU_GPIO0
THEY MUST NOT CONFLICT DURING RESET
R294 EV@10K/F_4
[13] GPU_GPIO1
R303 *EV@10K/F_4 Default Setting
[13] GPU_GPIO2 STRAPS MLPS GPIO PIN DESCRIPTION OF DEFAULT SETTINGS
R302 *EV@10K/F_4
[13] GPU_GPIO9
MLPS_DISABLE NA GPIO_28_FDO Enable MLPS, NA for Thames/Whistler/Seymour 0
R296 EV@10K/F_4 0: Enable MLPS, disable GPIO PINSTRAP
[13] GPU_GPIO11
1: Disable MLPS, enable GPIO PINSTRAP
R297 *EV@10K/F_4
[13] GPU_GPIO12
R298 *EV@10K/F_4 PS_1[4] Control the transmitter full-/half- swing mode
[13] GPU_GPIO13
STRAP_TX_CFG_DRV_FULL_SWING 0: 50% Tx output swing 1
R306 *EV@10K/F_4 1: Full Tx output swing
[13] GPU_GPIO22
R253 *EV@10K/F_4 STRAP_TX_DEEMPH_EN PS_1[5] PCIe transmitter, de-emphasis enable 1
[13] GENIL_VSYNC
0: Tx de-emphasis disabled
R555 *EV@10K/F_4 1: Tx de-emphasis enabled
[13] GPU_HSYNC
R551 *EV@10K/F_4 STRAP_BIF_GEN3_EN_A PCIe GEN3 Capability 0 for Kabini
[13] GPU_VSYNC PS_1[1]
0: GEN3 not supported at power-on
R254 *EV@10K/F_4 1: GEN3 supported at power-on
[13] GENIL_CLK
R305 *EV@10K/F_4 STRAP_BIF_VGA_DIS VGA disable determines whether or not the card will be recognized as the system's 0
[13] GPU_GPIO8 PS_2[4] VGA controler (through the SUBCLASS field in the PCI configuration space)
R304 *EV@10K/F_4 0: VGA controller capacity enabled
[13] GPU_GPIO21
1: The device will not be recognized as the system's VGA controller
R300 *EV@10K/F_4
[13] GPU_GENERICC
ROM_CONFIG[2:0] PS_0[3..1] Serial ROM type or Memory Aperture Size Select
R295 *EV@10K/F_4
[13] GPU_GPIO10
If GPIO22 = 0, defines memory aperture size XXX
If GPIO22 = 1, defines ROM type
100 - 512Kbit M25P05A (ST)
101 - 1Mbit M25P10A (ST)
101 - 2Mbit M25P20 (ST)
VDDC_CT 101 - 4Mbit M25P40 (ST)
101 - 8Mbit M25P80 (ST)
Close to ASIC RevB 1221 Add for 1GHz VRAM 100 - 512Kbit Pm25LV512 (Chingis)
101 - 1Mbit Pm25LV010 (Chingis)

STRAP_BIOS_ROM_EN PS_2[3] Enable external BIOS ROM device 0


10XXX for Mars R274 R275 R272 R276 R273 R598 R599 0: Disabled
R_pu H2G@4.75K/F_4 S1G@8.45K/F_4 S2G@4.53K/F_4 M1G@6.98K/F_4 M2G@4.53K/F_4 H1GG@3.24K/F_4 S1GG@3.4K/F_4 1: Enabled
11XXX for Sun
AUD[1] NA HSYNC 00 - No audio function XX
PS_3 AUD[0] NA VSYNC 01 - Audio for DP only
[13] PS_3
10 - Audio for DP and HDMI if dongle is detected
11 - Audio for both DP and HDMI
HDMI must only be enabled on systems that are legally entitled. It is the
Ca R_pd R264 R262 R263 R596 R597 responsibility of the system designer to ensure that the system is entitled to
C410 H1G@4.75K/F_4 SAM@2K/F_4 MICRON@4.99K/F_4 H1GG@5.62K/F_4 S1GG@10K/F_4 support this feature.
Mars@0.01U/25V_4X
N/A PS_0[4] Reserved for internal use only. Must be 1 at reset 1

RevB 1221 Add for Mars


N/A PS_1[3] Reserved 0
MLPS STRAP_BIF_CLK_PM_EN PS_1[2]
GENLK_CLK
PCIe reference clock power management capability is reported in the PCI
GPIO8
0
0: The CLKREQB power management capability is disabled
R_pu R_pd Bits [3:1] 1: The CLKREQB power management capability is enabled

RESERVED NA GPIO21 Reserved 0


NC 4.75K 000 Ca Bits [5:4] P/N RESERVED NA GENERICC Reserved (for Thames/Whistler/Seymour only) 0

8.45K 2K 001 680nF 00 CH4681K9B00


AUD_PORT_CONN_PINSTRAP[2] PS_3[5] NA STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS XXX
AUD_PORT_CONN_PINSTRAP[1] PS_3[4] NA 111 = 0 usable endpoints
4.53K 2K 010 82nF 01 CH3823K1B00 NA 110 = 1 usable endpoints
AUD_PORT_CONN_PINSTRAP[0] PS_0[5] 101 = 2 usable endpoints
100 = 3 usable endpoints
6.98K 4.99K 011 10nF 10 CH31003KB11 011 = 4 usable endpoints
010 = 5 usable endpoints
001 = 6 usable endpoints
4.53K 4.99K 100 NC 11 000 = all endpoints are usable

3.24K 5.62K 101

3.4K 10K 110


Power Up Reset Sequence
4.75K NC 111

DDR3 Memory TYPE +5VRUN/+3VRUN/VDDR3

Vendor Vendor P/N B/S P/N (QCI P/N) Size MLPS RUNPWROK
Ra P/N

2K CS22002FB19 H5TQ2G63DFR-11C AKD5MGWTW16 * 4 1GB 000 MVDDQ/VDDC/VDDCI


(128M*16) 1.8V_IO/PCIE_VDDC
3.24K CS23242FB09 Hynix
20ms max
H5TC4G63AFR-11C AKD5PGWTW05 * 4 2GB 111
3.4K CS23402FB08 (256M*16) PWRGOOD
100ms min 100ms min
4.53K CS24532FB08
MT41J128M16JT-107G:K AKD5DGSTL00 * 4 1GB
(128M*16) 011 PCIE_RST#(PERSTB)
4.75K CS24752FB12
Micron
4.99K CS24992FB26 MT41K256M16HA-107G:E
(256M*16)
AKD5PGSTL00 * 4 2GB 100 PCIE Clock
5.62K CS25622FB18
100us min 100ms max
K4W2G1646E-BC11 1GB
6.98K CS26982FB01 (128M*16) 001 Asic in Reset Hardware Reset Sequence DFG Space Ready
Samsung
8.45K CS28452FB12
K4W4G1646B-HC11 2GB 010
10K CS31002FB26 (256M*16)
Quanta Computer Inc.
PROJECT : BD9
Size Document Number Rev
A1A
Mars_M2/ STRAPS_Thermal
Date: Tuesday, December 25, 2012 Sheet 15 of 41
16
U33E

<VGA>
PCIe IO power. +1.8V_GPU
(1.5V@930mA/ Sun DDR3) PART 5 0F 9
+1.5V_GPU (1.5V@1.5A/Mars DDR3 128bits) On Mars except for AB37, all other balls can be NC (1.8V@100mA for Sun, Mars)
(1.5V@1.0A Mars DDR3 64bits) MEM I/O
AC7 NC_PCIE_VDDR AA31 PCIE_VDDR L7 EV@HCB1608KF-181T15_1.5A
VDDR1
AD11 VDDR1 NC_PCIE_VDDR AA32
AF7 VDDR1 NC_PCIE_VDDR AA33
C343 C657 C408 C353 C739 C733 AG10 VDDR1 NC_PCIE_VDDR AA34 C372 C364 C359 C354 C377
EV@10U/6.3V_6X EV@10U/6.3V_6X EV@10U/6.3V_6X *EV@4.7U/6.3V_6X *EV@10U/6.3V_6X *EV@10U/6.3V_6X AJ7 VDDR1 NC_PCIE_VDDR W30 EV@0.01U/25V_4X EV@0.1U/10V_4X EV@1U/6.3V_4X *EV@1U/6.3V_4X EV@10U/6.3V_6X
AK8 VDDR1 NC_PCIE_VDDR Y31
AL9 VDDR1 NC_BIF_VDDC V28
G11 VDDR1 NC_BIF_VDDC W29
G14 VDDR1 PCIE_PVDD AB37
G17

PCIE
VDDR1
G20 VDDR1 PCIE_VDDC G30
C332 C333 C330 C336 C350 C394 C341 G23 PCIE_VDDC G31 PCIe digital power supply. +0.95V_GPU
VDDR1
EV@2.2U/6.3V_4X EV@2.2U/6.3V_4X EV@2.2U/6.3V_4X EV@2.2U/6.3V_4X *EV@2.2U/6.3V_4X *EV@2.2U/6.3V_4X EV@2.2U/6.3V_4X G26 PCIE_VDDC H29 (0.95V@2.5A for Sun, Mars)
VDDR1
G29 PCIE_VDDC H30
VDDR1
H10 PCIE_VDDC J29
VDDR1
J7 PCIE_VDDC J30
VDDR1
J9 VDDR1 PCIE_VDDC L28 C325 C324 C326 C340 C345 C302 C298 C287 C308
K11 VDDR1 PCIE_VDDC M28 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@10U/6.3V_6X EV@10U/6.3V_6X
K13 VDDR1 PCIE_VDDC N28
C407 C646 C645 C386 K8 VDDR1 PCIE_VDDC R28
*EV@0.1U/10V_4X *EV@0.1U/10V_4X *EV@0.1U/10V_4X *EV@0.1U/10V_4X L12 VDDR1 PCIE_VDDC T28
L16 PCIE_VDDC U28
VDDR1 +0.95V_GPU
L21 Always connect to PCIE_VDDC for
VDDR1
L23 (0.95V@1.4A for Sun, Mars) both BACO & non-BACO designs.
VDDR1
L26 BIF_VDDC N27
VDDR1 BACO
L7 BIF_VDDC T27
VDDR1
+ M11
VDDR1
C385 C375 C401 C363 C642 N11 C335 C351 C293
VDDR1
*EV@0.1U/10V_4X *EV@0.1U/10V_4X *EV@0.1U/10V_4X *EV@0.1U/10V_4X EV@100U/6.3V_3528P_E45b P7 VDDR1 VDDC AA15 EV@1U/6.3V_4X EV@10U/6.3V_6X EV@1U/6.3V_4X
R11 CORE VDDC AA17
VDDR1
U11 VDDR1 VDDC AA20
U7 VDDR1 VDDC AA22
Y11 VDDR1 VDDC AA24
Y7 VDDC AA27 Dedicated core power, provides power to the internal logic.
VDDR1 +VGPU_CORE
VDDC AB16
Level translation between core and I/O, VDDC AB18 (0.775~1.125V@30A)
excluding memory receivers. VDDC AB21
VDDC_CT VDDC AB23
(1.8V@13mA for Sun, Mars) VDDC AB26
LEVEL
TRANSLATION VDDC AB28 C355 C346 C348 C347 C396
L9 EV@BLM15BD121SN1D_300MA VDDC_CT AF26 VDDC AC17 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X
+1.8V_GPU VDD_CT
AF27 VDD_CT VDDC AC20
AG26 VDD_CT VDDC AC22
C441 C439 C440 AG27 VDDC AC24
VDD_CT
EV@10U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X VDDC AC27
(3.3V@25mA for Sun, Mars) I/O power for 3.3-V pins, such as GPIOs. VDDC AD18
1002 AMD FAE suggest 120ohm I/O VDDC AD21
+3V_GPU AF23 VDDC AD23
VDDR3
L10 EV@BLM15BD121SN1D_300MA VDDR3 AF24 VDDR3 VDDC AD26
AG23 VDDR3 VDDC AF17 C360 C388 C397 C389 C390 C395 C398 C362 C402 C393
AG24 VDDR3 VDDC AF20 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X
C438 C436 C426 C409 VDDC AF22
EV@10U/6.3V_6X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X DVP VDDC AG16
AD12 VDDC AG18
VDDR4
(1.8V@300mA for Mars; NC for Sun) AF11
VDDR4
Power for all DVP pins; DVPDATA_[23:0]—DVO or GPIO. AF12 VDDC AH22
VDDR4
1002 AMD FAE suggest 120ohm AF13 VDDC AH27
VDDR4
VDDC AH28
L37 Mars@FCM1608KF-121T04_400MA VDDR4 VDDC M26
+1.8V_GPU
AF15 VDDC N24 C366 C369 C757 C750 C358 C380 C756 C745 C381 C357
VDDR4
AG11 VDDC R18 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@10U/6.3V_6X EV@10U/6.3V_6X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@10U/6.3V_6X EV@10U/6.3V_6X
VDDR4
C743 C740 C741 AG13 VDDR4 VDDC R21
Mars@10U/6.3V_6X Mars@1U/6.3V_4X Mars@0.1U/10V_4X AG15 VDDR4 VDDC R23
VDDC R26
VDDC T17
VDDC T20
VDDC T22
VDDC T24
VDDC U16
VDDC U18 C373 C406 C405 C368 C367 C391 C379 C344 C404
VDDC U21 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X
VDDC U23
VDDC U26
VDDC V17
VDDC V20
VDDC V22
VDDC V24
VDDC V27 Isolated (clean) core power for the l/O logic.
VDDC Y16
VDDC Y18 (0.775V~1.125V@5A/Sun)
VDDC Y21 +VGPU_CORE
VDDC Y23
VDDC Y26
VDDC Y28 L6 EV@HCB1608KF-121T30_3A

VDDCI AA13 VDDCI L5 EV@HCB1608KF-121T30_3A


VDDCI AB13
VDDCI AC12
VDDCI AC15 C309 C383 C356 C349
VDDCI AD13 *EV@1U/6.3V_4X EV@1U/6.3V_4X *EV@1U/6.3V_4X *EV@1U/6.3V_4X
VDDCI AD16
VDDCI M15
VDDCI M16
VDDCI M18
VOLTAGE VDDCI M23
CORE I/O
ISOLATED

SENESE VDDCI N13


R279 EV@0_4 AF28 VDDCI N15
[40] VGPU_CORE_VCCSSENSE FB_VDDC
VDDCI N17 C334 C338 C371 C376 C370 C339
VDDCI N20 *EV@10U/6.3V_6X *EV@10U/6.3V_6X EV@10U/6.3V_6X EV@1U/6.3V_4X EV@1U/6.3V_4X *EV@1U/6.3V_4X
VCORE_SEN/RTN route a differtial pair. AG28 FB_VDDCI VDDCI N22
VDDCI R12
VDDCI R13
R280 EV@0_4 AH29 VDDCI R16
[40] VGPU_CORE_VSSSENSE FB_GND
VDDCI
VDDCI
T12
T15
Quanta Computer Inc.
V15
VDDCI
VDDCI Y13 PROJECT : BD9
Size Document Number Rev
A1A
EV@Mars_M2
Mars_M2/ MainPower
Date: Tuesday, December 25, 2012 Sheet 16 of 41
<VGA>
17
U33H

PART 8 0F 9

DP_VDDR DP_VDDC (0.95V@280mA/link for Mars)


DP_VDDC AP31
DP_VDDC AP32
DP_VDDC AN33 C729 C727 C726
DP_VDDC AP33
AN24 Mars@10U/6.3V_6X Mars@1U/6.3V_4X Mars@0.1U/10V_4X
NC DPLL_VDDC
AP24 NC NC AP13
AP25 NC AT13 R571 MARS@0_6
NC
AP26 NC NC AP14
AU28 NC AP15
NC
AV29
NC
DP_VDDC AL33 DPLL_VDDC_MARS
DP_VDDC AM33
AP20 NC DP_VDDC AK33 C744 C736 C737
AP21 DP_VDDC AK34
NC
AP22 Mars@10U/6.3V_6X Mars@1U/6.3V_4X Mars@0.1U/10V_4X
NC
AP23 NC
AU18
NC
(1.8V@237mA/link for Mars) AV19 NC (0.95V@280mA/link for Mars)
DPEF_VDD18 DP GND
DP_VSSR AN27
+1.8V_GPU L36 EV@PBY160808T-501Y-N_1.2ADPEF_VDD18 R563 DPEF_VDD18_MARS AH34 DP_VDDR DP_VSSR AP27
MARS@0_6 AJ34 DP_VSSR AP28
DP_VDDR
AF34 DP_VDDR DP_VSSR AW24
C723 C721 C722 AG34 DP_VSSR AW26
DP_VDDR
EV@10U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X AM37 DP_VSSR AN29
DP_VDDR
AL38 DP_VDDR DP_VSSR AP29
DP_VSSR AP30
DP_VSSR AW30
DP_VSSR AW32
DP_VSSR AN17
DP_VSSR AP16 For ESD
DP_VSSR AP17
DP_VSSR AW14
DP_VSSR AW16
DP_VSSR AN19 +0.95V_GPU
DP_VSSR AP18
DP_VSSR AP19
DP_VSSR AW20
CALIBRATION DP_VSSR AW22
Reserve for Mars DP_VSSR AN34 C411 C310
DP_VSSR AP39 EV@39P/50V_4N EV@39P/50V_4N
R570 *EV@150/F_4 AW28 DP_VSSR AR39
NC_DPAB_CALR
DP_VSSR AU37
DP_VSSR AF39
DP_VSSR AH39
R572 *EV@150/F_4 AW18 NC_DPCD_CALR DP_VSSR AK39
DP_VSSR AL34
DP_VSSR AV27
DP_VSSR AR28
R567 EV@150/F_4 AM39 DP_VSSR AV17
DP_CALR
DP_VSSR AR18
DP_VSSR AN38
DP_VSSR AM35

EV@Mars_M2

Quanta Computer Inc.


PROJECT : BD9
Size Document Number Rev
A1A
Mars_M2/ DP_Powers
Date: Tuesday, December 25, 2012 Sheet 17 of 41
<VGA>

AB39
U33F

PART 6 0F 9

GND A3
18
PCIE_VSS
E39 GND A37
PCIE_VSS
F34 PCIE_VSS GND AA16
F39 GND AA18
PCIE_VSS
G33 PCIE_VSS GND AA2
G34 GND AA21
PCIE_VSS
H31 GND AA23
PCIE_VSS
H34 PCIE_VSS GND AA26
H39 GND AA28
PCIE_VSS
J31 PCIE_VSS GND AA6
J34 GND AB12
PCIE_VSS
K31 GND AB15
PCIE_VSS
K34 PCIE_VSS GND AB17
K39 GND AB20
PCIE_VSS
L31 PCIE_VSS GND AB22
L34 GND AB24
PCIE_VSS
M34 GND AB27
PCIE_VSS
M39 PCIE_VSS GND AC11
N31 GND AC13
PCIE_VSS
N34 PCIE_VSS GND AC16
P31 GND AC18
PCIE_VSS
P34 GND AC2
PCIE_VSS
P39 PCIE_VSS GND AC21
R34 GND AC23
PCIE_VSS
T31 PCIE_VSS GND AC26
T34 GND AC28
PCIE_VSS
T39 GND AC6
PCIE_VSS
U31 PCIE_VSS GND AD15
U34 GND AD17
PCIE_VSS
V34 PCIE_VSS GND AD20
V39 GND AD22
PCIE_VSS
W31 GND AD24
PCIE_VSS
W34 PCIE_VSS GND AD27
Y34 GND AD9
PCIE_VSS
Y39 PCIE_VSS GND AE2
GND AE6
GND AF10
GND AF16
GND AF18
GND AF21
GND
GND AG17
F15 GND AG2
GND
F17 GND GND AG20
F19 NC_EVDDQ2 AG22 Mars AG22 NC
GND
F21 GND GND AG6
F23 GND AG9
GND
F25 GND AH21
GND
F27 GND GND AJ10
F29 GND AJ11
GND
F31 GND GND AJ2
F33 GND AJ28
GND
F7 GND AJ6
GND
F9 GND GND AK11
G2 GND AK31
GND
G6 GND GND AK7
H9 GND AL11
GND
J2 GND AL14
GND
J27 GND GND AL17
J6 GND AL2
GND
J8 GND GND AL20
K14
GND
K7 GND AL23
GND
L11 GND GND AL26
L17 GND AL32
GND
L2 GND GND AL6
L22 GND AL8
GND
L24 GND AM11
GND
L6 GND GND AM31
M17 GND AM9
GND
M22 GND GND AN11
M24 GND AN2
GND
N16 GND AN30
GND
N18 GND GND AN6
N2 GND AN8
GND
N21 GND GND AP11
N23 GND AP7
GND
N26 GND AP9
GND
N6 GND GND AR5
R15 GND B11
GND
R17 GND GND B13
R2 GND B15
GND
R20 GND B17
GND
R22 GND GND B19
R24 GND B21
GND
R27 GND GND B23
R6 GND B25
GND
T11 GND B27
GND
T13 GND GND B29
T16 GND B31
GND
T18 GND GND B33
T21 GND B7
GND
T23 GND B9
GND
T26 GND GND C1
U15 GND C39
GND
U17 GND GND E35
U2 GND E5
GND
U20 GND F11
GND
U22 GND GND F13
U24
GND
U27 GND
U6
GND
V11
GND
V16 GND
V18
GND
V21 GND
V23
GND
V26
GND
W2 GND
W6
GND
Y15 GND
Y17
GND
Y20
GND
Y22 GND VSS_MECH A39
Y24 VSS_MECH AW1
GND
Y27 GND VSS_MECH AW39

EV@Mars_M2

Quanta Computer Inc.


PROJECT : BD9
Size Document Number Rev
A1A
Mars_M2/ GND
Date: Tuesday, December 25, 2012 Sheet 18 of 41
<VGA>
[20]

[20]
VMA_DQ[63..0]

VMA_DM[7..0]
VMA_DQ[63..0]

VMA_DM[7..0]
[21]

[21]
VMB_DQ[63..0]

VMB_DM[7..0]
VMB_DQ[63..0]

VMB_DM[7..0]
U33D
19
VMA_RDQS[7..0] U33C VMB_RDQS[7..0]
[20] VMA_RDQS[7..0] [21] VMB_RDQS[7..0] PART 4 0F 9
VMA_WDQS[7..0] PART 3 0F 9 VMB_WDQS[7..0]
[20] VMA_WDQS[7..0] [21] VMB_WDQS[7..0] GDDR5/DDR3
GDDR5/DDR3 VMB_DQ0 C5 DQB0_0 MAB0_0/MAB_0 P8 VMB_MA0
VMA_MA[14..0] VMA_DQ0 C37 MAA0_0/MAA_0 G24 VMA_MA0 VMB_MA[14..0] VMB_DQ1 C3 MAB0_1/MAB_1 T9 VMB_MA1
[20] VMA_MA[14..0] DQA0_0 [21] VMB_MA[14..0] DQB0_1
VMA_DQ1 C35 MAA0_1/MAA_1 J23 VMA_MA1 VMB_DQ2 E3 MAB0_2/MAB_2 P9 VMB_MA2
DQA0_1 DQB0_2
VMA_DQ2 A35 DQA0_2 MAA0_2/MAA_2 H24 VMA_MA2 VMB_DQ3 E1 DQB0_3 MAB0_3/MAB_3 N7 VMB_MA3
VMA_DQ3 E34 MAA0_3/MAA_3 J24 VMA_MA3 VMB_DQ4 F1 MAB0_4/MAB_4 N8 VMB_MA4
DQA0_3 DQB0_4
VMA_BA0 VMA_DQ4 G32 DQA0_4 MAA0_4/MAA_4 H26 VMA_MA4 VMB_BA0 VMB_DQ5 F3 DQB0_5 MAB0_5/MAB_5 N9 VMB_MA5
[20] VMA_BA0 [21] VMB_BA0
VMA_BA1 VMA_DQ5 D33 MAA0_5/MAA_5 J26 VMA_MA5 VMB_BA1 VMB_DQ6 F5 MAB0_6/MAB_6 U9 VMB_MA6
[20] VMA_BA1 DQA0_5 [21] VMB_BA1 DQB0_6

MEMORY INTERFACE A
VMA_BA2 VMA_DQ6 F32 MAA0_6/MAA_6 H21 VMA_MA6 VMB_BA2 VMB_DQ7 G4 MAB0_7/MAB_7 U8 VMB_MA7
[20] VMA_BA2 DQA0_6 [21] VMB_BA2 DQB0_7
VMA_DQ7 E32 DQA0_7 MAA0_7/MAA_7 G21 VMA_MA7 VMB_DQ8 H5 DQB0_8 MAB1_0/MAB_8 Y9 VMB_MA8
VMA_DQ8 D31 MAA1_0/MAA_8 H19 VMA_MA8 VMB_DQ9 H6 MAB1_1/MAB_9 W9 VMB_MA9
DQA0_8 DQB0_9
VMA_DQ9 F30 DQA0_9 MAA1_1/MAA_9 H20 VMA_MA9 VMB_DQ10 J4 DQB0_10 MAB1_2/MAB_10 AC8 VMB_MA10
VMA_DQ10 C30 MAA1_2/MAA_10 L13 VMA_MA10 VMB_DQ11 K6 MAB1_3/MAB_11 AC9 VMB_MA11
DQA0_10 DQB0_11
VMA_DQ11 A30 MAA1_3/MAA_11 G16 VMA_MA11 VMB_DQ12 K5 MAB1_4/MAB_12 AA7 VMB_MA12
DQA0_11 DQB0_12
VMA_DQ12 F28 DQA0_12 MAA1_4/MAA_12 J16 VMA_MA12 VMB_DQ13 L4 DQB0_13 MAB1_5/BA2 AA8 VMB_BA2
VMA_DQ13 C28 MAA1_5/MAA_BA2 H16 VMA_BA2 VMB_DQ14 M6 MAB1_6/BA0 Y8 VMB_BA0
DQA0_13 DQB0_14

MEMORY INTERFACE B
VMA_DQ14 A28 DQA0_14 MAA1_6/MAA_BA0 J17 VMA_BA0 VMB_DQ15 M1 DQB0_15 MAB1_7/BA1 AA9 VMB_BA1
VMA_DQ15 E28 MAA1_7/MAA_BA1 H17 VMA_BA1 VMB_DQ16 M3
DQA0_15 DQB0_16
VMA_DQ16 D27 VMB_DQ17 M5 WCKB0_0/DQMB_0 H3 VMB_DM0
DQA0_16 DQB0_17
VMA_DQ17 F26 DQA0_17 WCKA0_0/DQMA_0 A32 VMA_DM0 VMB_DQ18 N4 DQB0_18 WCKB0B_0/DQMB_1 H1 VMB_DM1
VMA_DQ18 C26 WCKA0B_0/DQMA_1 C32 VMA_DM1 VMB_DQ19 P6 WCKB0_1/DQMB_2 T3 VMB_DM2
DQA0_18 DQB0_19
VMA_DQ19 A26 DQA0_19 WCKA0_1/DQMA_2 D23 VMA_DM2 VMB_DQ20 P5 DQB0_20 WCKB0B_1/DQMB_3 T5 VMB_DM3
VMA_DQ20 F24 WCKA0B_1/DQMA_3 E22 VMA_DM3 VMB_DQ21 R4 WCKB1_0/DQMB_4 AE4 VMB_DM4
DQA0_20 DQB0_21
VMA_DQ21 C24 WCKA1_0/DQMA_4 C14 VMA_DM4 VMB_DQ22 T6 WCKB1B_0/DQMB_5 AF5 VMB_DM5
DQA0_21 DQB0_22
VMA_DQ22 A24 DQA0_22 WCKA1B_0/DQMA_5 A14 VMA_DM5 VMB_DQ23 T1 DQB0_23 WCKB1_1/DQMB_6 AK6 VMB_DM6
VMA_DQ23 E24 WCKA1_1/DQMA_6 E10 VMA_DM6 VMB_DQ24 U4 WCKB1B_1/DQMB_7 AK5 VMB_DM7
DQA0_23 DQB0_24
VMA_DQ24 C22 DQA0_24 WCKA1B_1/DQMA_7 D9 VMA_DM7 VMB_DQ25 V6 DQB0_25
VMA_DQ25 A22 VMB_DQ26 V1 EDCB0_0/QSB_0 F6 VMB_RDQS0
DQA0_25 DQB0_26
VMA_DQ26 F22 EDCA0_0/QSA_0 C34 VMA_RDQS0 VMB_DQ27 V3 EDCB0_1/QSB_1 K3 VMB_RDQS1
DQA0_26 DQB0_27
VMA_DQ27 D21 DQA0_27 EDCA0_1/QSA_1 D29 VMA_RDQS1 VMB_DQ28 Y6 DQB0_28 EDCB0_2/QSB_2 P3 VMB_RDQS2
VMA_DQ28 A20 EDCA0_2/QSA_2 D25 VMA_RDQS2 VMB_DQ29 Y1 EDCB0_3/QSB_3 V5 VMB_RDQS3 QSB[7..0]
DQA0_28 DQB0_29
VMA_DQ29 F20 DQA0_29 EDCA0_3/QSA_3 E20 VMA_RDQS3 VMB_DQ30 Y3 DQB0_30 EDCB1_0/QSB_4 AB5 VMB_RDQS4
VMA_DQ30 D19 EDCA1_0/QSA_4 E16 VMA_RDQS4 VMB_DQ31 Y5 EDCB1_1/QSB_5 AH1 VMB_RDQS5
DQA0_30 DQB0_31
VMA_DQ31 E18 EDCA1_1/QSA_5 E12 VMA_RDQS5 VMB_DQ32 AA4 EDCB1_2/QSB_6 AJ9 VMB_RDQS6
DQA0_31 DQB1_0
VMA_DQ32 C18 DQA1_0 EDCA1_2/QSA_6 J10 VMA_RDQS6 VMB_DQ33 AB6 DQB1_1 EDCB1_3/QSB_7 AM5 VMB_RDQS7
VMA_DQ33 A18 EDCA1_3/QSA_7 D7 VMA_RDQS7 VMB_DQ34 AB1
DQA1_1 DQB1_2
VMA_DQ34 F18 DQA1_2 VMB_DQ35 AB3 DQB1_3 DDBIB0_0/QSB_0B G7 VMB_WDQS0
VMA_DQ35 D17 DDBIA0_0/QSA_0B A34 VMA_WDQS0 VMB_DQ36 AD6 DDBIB0_1/QSB_1B K1 VMB_WDQS1
DQA1_3 DQB1_4
VMA_DQ36 A16 DDBIA0_1/QSA_1B E30 VMA_WDQS1 VMB_DQ37 AD1 DDBIB0_2/QSB_2B P1 VMB_WDQS2
DQA1_4 DQB1_5
VMA_DQ37 F16 DQA1_5 DDBIA0_2/QSA_2B E26 VMA_WDQS2 VMB_DQ38 AD3 DQB1_6 DDBIB0_3/QSB_3B W4 VMB_WDQS3 QSB#[7..0]
VMA_DQ38 D15 DDBIA0_3/QSA_3B C20 VMA_WDQS3 VMB_DQ39 AD5 DDBIB1_0/QSB_4B AC4 VMB_WDQS4
DQA1_6 DQB1_7
VMA_DQ39 E14 DQA1_7 DDBIA1_0/QSA_4B C16 VMA_WDQS4 VMB_DQ40 AF1 DQB1_8 DDBIB1_1/QSB_5B AH3 VMB_WDQS5
VMA_DQ40 F14 DDBIA1_1/QSA_5B C12 VMA_WDQS5 VMB_DQ41 AF3 DDBIB1_2/QSB_6B AJ8 VMB_WDQS6
DQA1_8 DQB1_9
VMA_DQ41 D13 DDBIA1_2/QSA_6B J11 VMA_WDQS6 VMB_DQ42 AF6 DDBIB1_3/QSB_7B AM3 VMB_WDQS7
DQA1_9 DQB1_10
VMA_DQ42 F12 DQA1_10 DDBIA1_3/QSA_7B F8 VMA_WDQS7 VMB_DQ43 AG4 DQB1_11
VMA_DQ43 A12 VMB_DQ44 AH5 ADBIB0/ODTB0 T7
DQA1_11 DQB1_12 VMB_ODT0 [21]
VMA_DQ44 D11 DQA1_12 ADBIA0/ODTA0 J21 VMB_DQ45 AH6 DQB1_13 ADBIB1/ODTB1 W7
VMA_ODT0 [20] VMB_ODT1 [21]
VMA_DQ45 F10 ADBIA1/ODTA1 G19 VMB_DQ46 AJ4
DQA1_13 VMA_ODT1 [20] DQB1_14
VMA_DQ46 A10 VMB_DQ47 AK3 CLKB0 L9 VMB_CLK0
DQA1_14 DQB1_15 VMB_CLK0 [21]
VMA_DQ47 C10 DQA1_15 CLKA0 H27 VMA_CLK0 VMB_DQ48 AF8 DQB1_16 CLKB0B L8 VMB_CLK0#
G13 G27 VMA_CLK0# VMA_CLK0 [20] AF9 VMB_CLK0# [21]
VMA_DQ48 DQA1_16 CLKA0B VMB_DQ49 DQB1_17
VMA_CLK0# [20]
VMA_DQ49 H13 DQA1_17 VMB_DQ50 AG8 DQB1_18 CLKB1 AD8 VMB_CLK1
VMB_CLK1 [21]
VMA_DQ50 J13 CLKA1 J14 VMA_CLK1 VMB_DQ51 AG7 CLKB1B AD7 VMB_CLK1#
DQA1_18 VMA_CLK1 [20] DQB1_19 VMB_CLK1# [21]
VMA_DQ51 H11 CLKA1B H14 VMA_CLK1# VMB_DQ52 AK9
DQA1_19 VMA_CLK1# [20] DQB1_20
VMA_DQ52 G10 DQA1_20 VMB_DQ53 AL7 DQB1_21 RASB0B T10 VMB_RAS0#
G8 K23 VMA_RAS0# AM8 Y10 VMB_RAS1# VMB_RAS0# [21]
Place MVREF dividers and Caps close to ASIC VMA_DQ53 DQA1_21 RASA0B VMB_DQ54 DQB1_22 RASB1B
VMA_RAS0# [20] VMB_RAS1# [21]
VMA_DQ54 K9 DQA1_22 RASA1B K19 VMA_RAS1# Place MVREF dividers and Caps close to ASIC VMB_DQ55 AM7 DQB1_23
VMA_RAS1# [20]
VMA_DQ55 K10 VMB_DQ56 AK1 CASB0B W10 VMB_CAS0#
DQA1_23 DQB1_24 VMB_CAS0# [21]
VMA_DQ56 G9 CASA0B K20 VMA_CAS0# VMB_DQ57 AL4 CASB1B AA10 VMB_CAS1#
DQA1_24 VMA_CAS0# [20] DQB1_25 VMB_CAS1# [21]
+1.5V_GPU VMA_DQ57 A8 DQA1_25 CASA1B K17 VMA_CAS1# +1.5V_GPU VMB_DQ58 AM6 DQB1_26
C8 VMA_CAS1# [20] AM1 P10 VMB_CS0#
VMA_DQ58 DQA1_26 VMB_DQ59 DQB1_27 CSB0B_0
VMB_CS0# [21]
(0.7*VDDR1) VMA_DQ59 E8 DQA1_27 CSA0B_0 K24 VMA_CS0# (0.7*VDDR1) VMB_DQ60 AN4 DQB1_28 CSB0B_1 L10
VMA_CS0# [20]
VMA_DQ60 A6 CSA0B_1 K27 VMB_DQ61 AP3
DQA1_28 DQB1_29
VMA_DQ61 C6 VMB_DQ62 AP1 CSB1B_0 AD10 VMB_CS1#
DQA1_29 DQB1_30 VMB_CS1# [21]
Ra R515 VMA_DQ62 E6 DQA1_30 CSA1B_0 M13 VMA_CS1# Ra R575 VMB_DQ63 AP5 DQB1_31 CSB1B_1 AC10
A5 K16 VMA_CS1# [20]
EV@40.2/F_4 VMA_DQ63 DQA1_31 CSA1B_1 EV@40.2/F_4
CKEB0 U10 VMB_CKE0
VMB_CKE0 [21]
MVREFDA L18 CKEA0 K21 VMA_CKE0 MVREFDB Y12 CKEB1 AA11 VMB_CKE1
MVREFDA VMA_CKE0 [20] MVREFDB VMB_CKE1 [21]
MVREFSA L20 CKEA1 J20 VMA_CKE1 MVREFSB AA12
MVREFSA VMA_CKE1 [20] MVREFSB
WEB0B N10 VMB_WE0#
L27 K26 VMA_WE0# AB11 VMB_WE1# VMB_WE0# [21]
NC_MEM_CALRN0 WEA0B WEB1B
VMA_WE0# [20] VMB_WE1# [21]
Rb R518 C680 N12 NC_MEM_CALRN1 WEA1B L15 VMA_WE1# Rb R576 C731
VMA_WE1# [20]
EV@100/F_4 EV@1U/6.3V_4X AG12 EV@100/F_4 EV@1U/6.3V_4X
NC_MEM_CALRN2
MAB0_8/MAB_13 T8 VMB_MA13
M12 NC_MEM_CALRP1 MAA0_8/MAA_13 H23 VMA_MA13 MAB1_8/MAB_14 W8 VMB_MA14
R240 EV@120/F_4 M27 MAA1_8/MAA_14 J19 VMA_MA14 MAB0_9/MAB_15 U12
MEM_CALRP0
R299 *EV@120/F_4 AH12 NC_MEM_CALRP2 MAA0_9/MAA_15 M21 MAB1_9/RSVD V12
MAA1_9/RSVD M20
+1.5V_GPU +1.5V_GPU DRAM_RST AH11 GPU_DRAM_RST

(0.7*VDDR1) (0.7*VDDR1)
EV@Mars_M2
Ra R219 Ra R580
EV@40.2/F_4 EV@Mars_M2 EV@40.2/F_4

Rb R222 C288 Rb R579 C742


EV@100/F_4 EV@1U/6.3V_4X
Ball Name Thames Seymour Mars EV@100/F_4 EV@1U/6.3V_4X
25mm (max) 5mm (max) 25mm (max)

MEM_CALRN0 243R X X GPU_DRAM_RST R578 EV@10/F_4 R581 EV@51/F_4


MEM_RST# [20,21]

MEM_CALRN1 X 243R X
R574 C746 C747
MEM_CALRN2 243R X X EV@4.99K/F_4 EV@120P/50V_4N *E@0.1U/10V_4X

MEM_CALRP0 243R X 120R


MEM_CALRP1 X 243R X
Place all these componets very close to GPU (within 25mm)
and keep all components close to each other
MEM_CALRP2 243R X X ** This basic topology should be used for DRAM_RAT for DDR3/GDDR5

These Capacitors and Resistor values arre an example only


The series R and || cap values will depend on the DRAM loads
and will have to be calculated for differrent Memory, DRAM loads and board
to pass Reset Signal Spec

Quanta Computer Inc.


PROJECT : BD9
Size Document Number Rev
A1A
Mars_M2/ MEM Interface
Date: Tuesday, December 25, 2012 Sheet 19 of 41
5 4 3 2 1

CHANNEL A: 1024MB DDR3 (128M*16*4pcs) <VGA>


20
VMA_DQ[63..0]
[19] VMA_DQ[63..0]
VMA_DM[7..0]
[19] VMA_DM[7..0]
VMA_RDQS[7..0] QSA[7..0]
[19] VMA_RDQS[7..0]
VMA_WDQS[7..0] QSA#[7..0]
[19] VMA_WDQS[7..0]
U8 U25
U7 U24
VREFC_VMA3 M8 E3 VMA_DQ54 VREFC_VMA4 M8 E3 VMA_DQ46
VREFC_VMA1 M8 E3 VMA_DQ5 VREFC_VMA2 M8 E3 VMA_DQ12 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ50 VREFD_VMA4 H1 VREFCA DQL0 F7 VMA_DQ45
VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ0 VREFD_VMA2 H1 VREFCA DQL0 F7 VMA_DQ14 VREFDQ DQL1 F2 VMA_DQ53 VREFDQ DQL1 F2 VMA_DQ44
VREFDQ DQL1 F2 VMA_DQ6 VREFDQ DQL1 F2 VMA_DQ8 VMA_MA0 N3 DQL2 F8 VMA_DQ49 VMA_MA0 N3 DQL2 F8 VMA_DQ40
VMA_MA0 N3 DQL2 F8 VMA_DQ1 VMA_MA0 N3 DQL2 F8 VMA_DQ11 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ52 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ41
[19] VMA_MA0 A0 DQL3 A0 DQL3 A1 DQL4 A1 DQL4
VMA_MA1 P7 H3 VMA_DQ4 VMA_MA1 P7 H3 VMA_DQ10 VMA_MA2 P3 H8 VMA_DQ51 VMA_MA2 P3 H8 VMA_DQ42
[19] VMA_MA1 A1 DQL4 A1 DQL4 A2 DQL5 A2 DQL5
VMA_MA2 P3 H8 VMA_DQ3 VMA_MA2 P3 H8 VMA_DQ15 VMA_MA3 N2 G2 VMA_DQ55 VMA_MA3 N2 G2 VMA_DQ43
[19] VMA_MA2 A2 DQL5 A2 DQL5 A3 DQL6 A3 DQL6
VMA_MA3 N2 G2 VMA_DQ7 VMA_MA3 N2 G2 VMA_DQ9 VMA_MA4 P8 H7 VMA_DQ48 VMA_MA4 P8 H7 VMA_DQ47
D [19] VMA_MA3 A3 DQL6 A3 DQL6 A4 DQL7 A4 DQL7 D
VMA_MA4 P8 H7 VMA_DQ2 VMA_MA4 P8 H7 VMA_DQ13 VMA_MA5 P2 VMA_MA5 P2
[19] VMA_MA4 A4 DQL7 A4 DQL7 A5 A5
VMA_MA5 P2 VMA_MA5 P2 VMA_MA6 R8 VMA_MA6 R8
[19] VMA_MA5 A5 A5 A6 A6
VMA_MA6 R8 VMA_MA6 R8 VMA_MA7 R2 D7 VMA_DQ32 VMA_MA7 R2 D7 VMA_DQ61
[19] VMA_MA6 A6 A6 A7 DQU0 A7 DQU0
VMA_MA7 R2 D7 VMA_DQ24 VMA_MA7 R2 D7 VMA_DQ20 VMA_MA8 T8 C3 VMA_DQ36 VMA_MA8 T8 C3 VMA_DQ58
[19] VMA_MA7 A7 DQU0 A7 DQU0 A8 DQU1 A8 DQU1
VMA_MA8 T8 C3 VMA_DQ31 VMA_MA8 T8 C3 VMA_DQ19 VMA_MA9 R3 C8 VMA_DQ33 VMA_MA9 R3 C8 VMA_DQ63
[19] VMA_MA8 A8 DQU1 A8 DQU1 A9 DQU2 A9 DQU2
VMA_MA9 R3 C8 VMA_DQ27 VMA_MA9 R3 C8 VMA_DQ23 VMA_MA10 L7 C2 VMA_DQ37 VMA_MA10 L7 C2 VMA_DQ56
[19] VMA_MA9 A9 DQU2 A9 DQU2 A10/AP DQU3 A10/AP DQU3
VMA_MA10 L7 C2 VMA_DQ28 VMA_MA10 L7 C2 VMA_DQ17 VMA_MA11 R7 A7 VMA_DQ34 VMA_MA11 R7 A7 VMA_DQ60
[19] VMA_MA10 A10/AP DQU3 A10/AP DQU3 A11 DQU4 A11 DQU4
VMA_MA11 R7 A7 VMA_DQ25 VMA_MA11 R7 A7 VMA_DQ22 VMA_MA12 N7 A2 VMA_DQ39 VMA_MA12 N7 A2 VMA_DQ59
[19] VMA_MA11 A11 DQU4 A11 DQU4 A12/BC DQU5 A12/BC DQU5
VMA_MA12 N7 A2 VMA_DQ29 VMA_MA12 N7 A2 VMA_DQ16 VMA_MA13 T3 B8 VMA_DQ35 VMA_MA13 T3 B8 VMA_DQ62
[19] VMA_MA12 A12/BC DQU5 A12/BC DQU5 A13 DQU6 A13 DQU6
VMA_MA13 T3 B8 VMA_DQ26 VMA_MA13 T3 B8 VMA_DQ21 VMA_MA14 T7 A3 VMA_DQ38 VMA_MA14 T7 A3 VMA_DQ57
[19] VMA_MA13 A13 DQU6 A13 DQU6 A14 DQU7 A14 DQU7
VMA_MA14 T7 A3 VMA_DQ30 VMA_MA14 T7 A3 VMA_DQ18 M7 M7
[19] VMA_MA14 A14 DQU7 A14 DQU7 A15 A15
M7 M7 +1.5V_GPU +1.5V_GPU
A15 +1.5V_GPU A15 +1.5V_GPU
VMA_BA0 M2 B2 VMA_BA0 M2 B2
VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA1 N8 BA0 VDD#B2 D9 VMA_BA1 N8 BA0 VDD#B2 D9
[19] VMA_BA0 BA0 VDD#B2 BA0 VDD#B2 BA1 VDD#D9 BA1 VDD#D9
VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA2 M3 G7 VMA_BA2 M3 G7
[19] VMA_BA1 BA1 VDD#D9 BA1 VDD#D9 BA2 VDD#G7 BA2 VDD#G7
VMA_BA2 M3 G7 VMA_BA2 M3 G7 K2 K2
[19] VMA_BA2 BA2 VDD#G7 BA2 VDD#G7 VDD#K2 VDD#K2
K2 K2 K8 K8
VDD#K2 K8 VDD#K2 K8 VDD#K8 N1 VDD#K8 N1
VDD#K8 N1 VDD#K8 N1 VMA_CLK1 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9
VDD#N1 VDD#N1 [19] VMA_CLK1 CK VDD#N9 CK VDD#N9
VMA_CLK0 J7 N9 VMA_CLK0 J7 N9 VMA_CLK1# K7 R1 VMA_CLK1# K7 R1
[19] VMA_CLK0 CK VDD#N9 CK VDD#N9 [19] VMA_CLK1# CK VDD#R1 CK VDD#R1
VMA_CLK0# K7 R1 VMA_CLK0# K7 R1 VMA_CKE1 K9 R9 VMA_CKE1 K9 R9
[19] VMA_CLK0# CK VDD#R1 CK VDD#R1 [19] VMA_CKE1 CKE VDD#R9 CKE VDD#R9
VMA_CKE0 K9 R9 VMA_CKE0 K9 R9 +1.5V_GPU +1.5V_GPU
[19] VMA_CKE0 CKE VDD#R9 CKE VDD#R9
+1.5V_GPU +1.5V_GPU
VMA_ODT1 K1 A1 VMA_ODT1 K1 A1
[19] VMA_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMA_ODT0 K1 A1 VMA_ODT0 K1 A1 VMA_CS1# L2 A8 VMA_CS1# L2 A8
[19] VMA_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 [19] VMA_CS1# CS VDDQ#A8 CS VDDQ#A8
VMA_CS0# L2 A8 VMA_CS0# L2 A8 VMA_RAS1# J3 C1 VMA_RAS1# J3 C1
[19] VMA_CS0# CS VDDQ#A8 CS VDDQ#A8 [19] VMA_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMA_RAS0# J3 C1 VMA_RAS0# J3 C1 VMA_CAS1# K3 C9 VMA_CAS1# K3 C9
[19] VMA_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 [19] VMA_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMA_CAS0# K3 C9 VMA_CAS0# K3 C9 VMA_WE1# L3 D2 VMA_WE1# L3 D2
[19] VMA_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 [19] VMA_WE1# WE VDDQ#D2 WE VDDQ#D2
VMA_WE0# L3 D2 VMA_WE0# L3 D2 E9 E9
[19] VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 VDDQ#E9 VDDQ#E9
E9 E9 F1 F1
VDDQ#E9 F1 VDDQ#E9 F1 VMA_RDQS6 F3 VDDQ#F1 H2 VMA_RDQS5 F3 VDDQ#F1 H2
VMA_RDQS0 F3 VDDQ#F1 H2 VMA_RDQS1 F3 VDDQ#F1 H2 VMA_RDQS4 C7 DQSL VDDQ#H2 H9 VMA_RDQS7 C7 DQSL VDDQ#H2 H9
VMA_RDQS3 C7 DQSL VDDQ#H2 H9 VMA_RDQS2 C7 DQSL VDDQ#H2 H9 DQSU VDDQ#H9 DQSU VDDQ#H9
DQSU VDDQ#H9 DQSU VDDQ#H9
VMA_DM6 E7 A9 VMA_DM5 E7 A9
VMA_DM0 E7 A9 VMA_DM1 E7 A9 VMA_DM4 D3 DML VSS#A9 B3 VMA_DM7 D3 DML VSS#A9 B3
C VMA_DM3 D3 DML VSS#A9 B3 VMA_DM2 D3 DML VSS#A9 B3 DMU VSS#B3 E1 DMU VSS#B3 E1 C
DMU VSS#B3 E1 DMU VSS#B3 E1 VSS#E1 G8 VSS#E1 G8
VSS#E1 G8 VSS#E1 G8 VMA_WDQS6 G3 VSS#G8 J2 VMA_WDQS5 G3 VSS#G8 J2
VMA_WDQS0 G3 VSS#G8 J2 VMA_WDQS1 G3 VSS#G8 J2 VMA_WDQS4 B7 DQSL VSS#J2 J8 VMA_WDQS7 B7 DQSL VSS#J2 J8
VMA_WDQS3 B7 DQSL VSS#J2 J8 VMA_WDQS2 B7 DQSL VSS#J2 J8 DQSU VSS#J8 M1 DQSU VSS#J8 M1
DQSU VSS#J8 M1 DQSU VSS#J8 M1 VSS#M1 M9 VSS#M1 M9
VSS#M1 M9 VSS#M1 M9 VSS#M9 P1 VSS#M9 P1
VSS#M9 P1 VSS#M9 P1 MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9
MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9 RESET VSS#P9 T1 RESET VSS#P9 T1
[19,21] MEM_RST# RESET VSS#P9 T1 RESET VSS#P9 T1 VMA_ZQ3 L8 VSS#T1 T9 VMA_ZQ4 L8 VSS#T1 T9
VMA_ZQ1 L8 VSS#T1 T9 VMA_ZQ2 L8 VSS#T1 T9 ZQ VSS#T9 ZQ VSS#T9
ZQ VSS#T9 ZQ VSS#T9
B1 B1
B1 B1 VSSQ#B1 B9 VSSQ#B1 B9
VSSQ#B1 B9 VSSQ#B1 B9 R209 VSSQ#B9 D1 R467 VSSQ#B9 D1
R145 VSSQ#B9 D1 R206 VSSQ#B9 D1 Mars@243/F_4 VSSQ#D1 D8 Mars@243/F_4 VSSQ#D1 D8
Mars@243/F_4 VSSQ#D1 D8 Mars@243/F_4 VSSQ#D1 D8 VSSQ#D8 E2 VSSQ#D8 E2
VSSQ#D8 E2 VSSQ#D8 E2 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 100-BALL 100-BALL
100-BALL 100-BALL SDRAM DDR3 SDRAM DDR3
SDRAM DDR3 SDRAM DDR3 Mars@VRAM _DDR3 Mars@VRAM _DDR3
Mars@VRAM _DDR3 Mars@VRAM _DDR3

TOP Left BOT Left BOT Right TOP Right


Group-A0 VREF Group-A1 VREF
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R146 R205 R148 R142
Mars@4.99K/F_4 Mars@4.99K/F_4 Mars@4.99K/F_4 Mars@4.99K/F_4 R207 R153 R465 R464
Mars@4.99K/F_4 Mars@4.99K/F_4 Mars@4.99K/F_4 Mars@4.99K/F_4

VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2


VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4

R147 C204 R204 C285 R149 C206 R154 C220


R208 C286 R152 C219 R466 C637 R463 C636
Mars@4.99K/F_4 Mars@0.1U/10V_4X Mars@4.99K/F_4 Mars@0.1U/10V_4X Mars@4.99K/F_4 Mars@0.1U/10V_4X Mars@4.99K/F_4 Mars@0.1U/10V_4X
Mars@4.99K/F_4 Mars@0.1U/10V_4X Mars@4.99K/F_4 Mars@0.1U/10V_4X Mars@4.99K/F_4 Mars@0.1U/10V_4X Mars@4.99K/F_4 Mars@0.1U/10V_4X

Group-A0 decoupling CAP Group-A1 decoupling CAP


MEM_A0 CLK
+1.5V_GPU MEM_A1 CLK
+1.5V_GPU

VMA_CLK0 VMA_CLK1

VMA_CLK0# C212 C639 C638 C215 C208 C209 C210 C211 VMA_CLK1#
C250 C247 C239 C236 C232 C244 C240 C237 Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X
Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X
R144 R143
Mars@40.2/F_4 Mars@40.2/F_4 R150 R151
+1.5V_GPU Mars@40.2/F_4 Mars@40.2/F_4
+1.5V_GPU

C202 C218 C640 C213 C223 C226 C228 C217 C216


Mars@0.01U/25V_4X C243 C253 C234 C207 C203 C205 C231 C260 Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X C214
A Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@1U/6.3V_4X Mars@0.01U/25V_4X A

+1.5V_GPU
+1.5V_GPU

C696 C711 C698 C198 C199


C641 C644 C229 C653 C668 Mars@4.7U/6.3V_6X Mars@4.7U/6.3V_6X Mars@4.7U/6.3V_6X Mars@4.7U/6.3V_6X Mars@4.7U/6.3V_6X
Mars@4.7U/6.3V_6X Mars@4.7U/6.3V_6X Mars@4.7U/6.3V_6X Mars@4.7U/6.3V_6X Mars@4.7U/6.3V_6X Quanta Computer Inc.
PROJECT : BD9
Size Document Number Rev
A1A
VRAM_A: DDR3*4PCS
Date: Tuesday, December 25, 2012 Sheet 20 of 41
5 4 3 2 1
5 4 3 2 1

CHANNEL B: 1024MB DDR3 (128M*16*4pcs) <VGA>


21
VMB_DQ[63..0]
[19] VMB_DQ[63..0]
VMB_DM[7..0]
[19] VMB_DM[7..0]
VMB_RDQS[7..0] QSA[7..0]
[19] VMB_RDQS[7..0]
VMB_WDQS[7..0] QSA#[7..0]
[19] VMB_WDQS[7..0]
U12 U31 U14 U34

VREFC_VMB1 M8 E3 VMB_DQ23 VREFC_VMB2 M8 E3 VMB_DQ1 VREFC_VMB3 M8 E3 VMB_DQ55 VREFC_VMB4 M8 E3 VMB_DQ62


VREFD_VMB1 H1 VREFCA DQL0 F7 VMB_DQ16 VREFD_VMB2 H1 VREFCA DQL0 F7 VMB_DQ4 VREFD_VMB3 H1 VREFCA DQL0 F7 VMB_DQ51 VREFD_VMB4 H1 VREFCA DQL0 F7 VMB_DQ61
VREFDQ DQL1 F2 VMB_DQ21 VREFDQ DQL1 F2 VMB_DQ2 VREFDQ DQL1 F2 VMB_DQ54 VREFDQ DQL1 F2 VMB_DQ63
VMB_MA0 N3 DQL2 F8 VMB_DQ17 VMB_MA0 N3 DQL2 F8 VMB_DQ5 VMB_MA0 N3 DQL2 F8 VMB_DQ50 VMB_MA0 N3 DQL2 F8 VMB_DQ60
[19] VMB_MA0 A0 DQL3 A0 DQL3 A0 DQL3 A0 DQL3
VMB_MA1 P7 H3 VMB_DQ22 VMB_MA1 P7 H3 VMB_DQ0 VMB_MA1 P7 H3 VMB_DQ52 VMB_MA1 P7 H3 VMB_DQ59
[19] VMB_MA1 P3 A1 DQL4 H8 P3 A1 DQL4 H8 P3 A1 DQL4 H8 P3 A1 DQL4 H8
VMB_MA2 VMB_DQ19 VMB_MA2 VMB_DQ7 VMB_MA2 VMB_DQ49 VMB_MA2 VMB_DQ58
[19] VMB_MA2 A2 DQL5 A2 DQL5 A2 DQL5 A2 DQL5
VMB_MA3 N2 G2 VMB_DQ20 VMB_MA3 N2 G2 VMB_DQ3 VMB_MA3 N2 G2 VMB_DQ53 VMB_MA3 N2 G2 VMB_DQ57
D [19] VMB_MA3 A3 DQL6 A3 DQL6 A3 DQL6 A3 DQL6 D
VMB_MA4 P8 H7 VMB_DQ18 VMB_MA4 P8 H7 VMB_DQ6 VMB_MA4 P8 H7 VMB_DQ48 VMB_MA4 P8 H7 VMB_DQ56
[19] VMB_MA4 P2 A4 DQL7 P2 A4 DQL7 P2 A4 DQL7 P2 A4 DQL7
VMB_MA5 VMB_MA5 VMB_MA5 VMB_MA5
[19] VMB_MA5 A5 A5 A5 A5
VMB_MA6 R8 VMB_MA6 R8 VMB_MA6 R8 VMB_MA6 R8
[19] VMB_MA6 R2 A6 D7 R2 A6 D7 R2 A6 D7 R2 A6 D7
VMB_MA7 VMB_DQ26 VMB_MA7 VMB_DQ15 VMB_MA7 VMB_DQ41 VMB_MA7 VMB_DQ38
[19] VMB_MA7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
VMB_MA8 T8 C3 VMB_DQ30 VMB_MA8 T8 C3 VMB_DQ10 VMB_MA8 T8 C3 VMB_DQ47 VMB_MA8 T8 C3 VMB_DQ32
[19] VMB_MA8 A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
VMB_MA9 R3 C8 VMB_DQ28 VMB_MA9 R3 C8 VMB_DQ14 VMB_MA9 R3 C8 VMB_DQ40 VMB_MA9 R3 C8 VMB_DQ36
[19] VMB_MA9 L7 A9 DQU2 C2 L7 A9 DQU2 C2 L7 A9 DQU2 C2 L7 A9 DQU2 C2
VMB_MA10 VMB_DQ31 VMB_MA10 VMB_DQ8 VMB_MA10 VMB_DQ46 VMB_MA10 VMB_DQ33
[19] VMB_MA10 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3
VMB_MA11 R7 A7 VMB_DQ24 VMB_MA11 R7 A7 VMB_DQ12 VMB_MA11 R7 A7 VMB_DQ44 VMB_MA11 R7 A7 VMB_DQ37
[19] VMB_MA11 N7 A11 DQU4 A2 N7 A11 DQU4 A2 N7 A11 DQU4 A2 N7 A11 DQU4 A2
VMB_MA12 VMB_DQ27 VMB_MA12 VMB_DQ9 VMB_MA12 VMB_DQ45 VMB_MA12 VMB_DQ35
[19] VMB_MA12 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
VMB_MA13 T3 B8 VMB_DQ25 VMB_MA13 T3 B8 VMB_DQ13 VMB_MA13 T3 B8 VMB_DQ43 VMB_MA13 T3 B8 VMB_DQ39
[19] VMB_MA13 A13 DQU6 A13 DQU6 A13 DQU6 A13 DQU6
VMB_MA14 T7 A3 VMB_DQ29 VMB_MA14 T7 A3 VMB_DQ11 VMB_MA14 T7 A3 VMB_DQ42 VMB_MA14 T7 A3 VMB_DQ34
[19] VMB_MA14 M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7
A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU

VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2


[19] VMB_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9
[19] VMB_BA1 M3 BA1 VDD#D9 G7 M3 BA1 VDD#D9 G7 M3 BA1 VDD#D9 G7 M3 BA1 VDD#D9 G7
VMB_BA2 VMB_BA2 VMB_BA2 VMB_BA2
[19] VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
VMB_CLK0 J7 VDD#N1 N9 VMB_CLK0 J7 VDD#N1 N9 VMB_CLK1 J7 VDD#N1 N9 VMB_CLK1 J7 VDD#N1 N9
[19] VMB_CLK0 K7 CK VDD#N9 R1 K7 CK VDD#N9 R1 [19] VMB_CLK1 K7 CK VDD#N9 R1 K7 CK VDD#N9 R1
VMB_CLK0# VMB_CLK0# VMB_CLK1# VMB_CLK1#
[19] VMB_CLK0# CK VDD#R1 CK VDD#R1 [19] VMB_CLK1# CK VDD#R1 CK VDD#R1
VMB_CKE0 K9 R9 VMB_CKE0 K9 R9 VMB_CKE1 K9 R9 VMB_CKE1 K9 R9
[19] VMB_CKE0 CKE VDD#R9 CKE VDD#R9 [19] VMB_CKE1 CKE VDD#R9 CKE VDD#R9
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU

VMB_ODT0 K1 A1 VMB_ODT0 K1 A1 VMB_ODT1 K1 A1 VMB_ODT1 K1 A1


[19] VMB_ODT0 L2 ODT VDDQ#A1 A8 L2 ODT VDDQ#A1 A8 [19] VMB_ODT1 L2 ODT VDDQ#A1 A8 L2 ODT VDDQ#A1 A8
VMB_CS0# VMB_CS0# VMB_CS1# VMB_CS1#
[19] VMB_CS0# CS VDDQ#A8 CS VDDQ#A8 [19] VMB_CS1# CS VDDQ#A8 CS VDDQ#A8
VMB_RAS0# J3 C1 VMB_RAS0# J3 C1 VMB_RAS1# J3 C1 VMB_RAS1# J3 C1
[19] VMB_RAS0# K3 RAS VDDQ#C1 C9 K3 RAS VDDQ#C1 C9 [19] VMB_RAS1# K3 RAS VDDQ#C1 C9 K3 RAS VDDQ#C1 C9
VMB_CAS0# VMB_CAS0# VMB_CAS1# VMB_CAS1#
[19] VMB_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 [19] VMB_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMB_WE0# L3 D2 VMB_WE0# L3 D2 VMB_WE1# L3 D2 VMB_WE1# L3 D2
[19] VMB_WE0# WE VDDQ#D2 WE VDDQ#D2 [19] VMB_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
VMB_RDQS2 F3 VDDQ#F1 H2 VMB_RDQS0 F3 VDDQ#F1 H2 VMB_RDQS6 F3 VDDQ#F1 H2 VMB_RDQS7 F3 VDDQ#F1 H2
VMB_RDQS3 C7 DQSL VDDQ#H2 H9 VMB_RDQS1 C7 DQSL VDDQ#H2 H9 VMB_RDQS5 C7 DQSL VDDQ#H2 H9 VMB_RDQS4 C7 DQSL VDDQ#H2 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9

VMB_DM2 E7 A9 VMB_DM0 E7 A9 VMB_DM6 E7 A9 VMB_DM7 E7 A9


VMB_DM3 D3 DML VSS#A9 B3 VMB_DM1 D3 DML VSS#A9 B3 VMB_DM5 D3 DML VSS#A9 B3 VMB_DM4 D3 DML VSS#A9 B3
C C
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
VMB_WDQS2 G3 VSS#G8 J2 VMB_WDQS0 G3 VSS#G8 J2 VMB_WDQS6 G3 VSS#G8 J2 VMB_WDQS7 G3 VSS#G8 J2
VMB_WDQS3 B7 DQSL VSS#J2 J8 VMB_WDQS1 B7 DQSL VSS#J2 J8 VMB_WDQS5 B7 DQSL VSS#J2 J8 VMB_WDQS4 B7 DQSL VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9
[19,20] MEM_RST# RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1
VMB_ZQ1 L8 VSS#T1 T9 VMB_ZQ2 L8 VSS#T1 T9 VMB_ZQ3 L8 VSS#T1 T9 VMB_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9

B1 B1 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R238 VSSQ#B9 D1 R534 VSSQ#B9 D1 R247 VSSQ#B9 D1 R564 VSSQ#B9 D1
EV@243/F_4 VSSQ#D1 D8 EV@243/F_4 VSSQ#D1 D8 EV@243/F_4 VSSQ#D1 D8 EV@243/F_4 VSSQ#D1 D8
VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
EV@VRAM _DDR3 EV@VRAM _DDR3 EV@VRAM _DDR3 EV@VRAM _DDR3

BOT Down TOP Down TOP Up BOT Up

Group-B0 VREF Group-B1 VREF


+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B

R241 R243 R540 R529 R244 R282 R560 R541


EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4

VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2 VREFC_VMB3 VREFD_VMB3 VREFC_VMB4 VREFD_VMB4

R239 C328 R242 C352 R536 C697 R530 C695 R245 C382 R281 C415 R562 C719 R542 C704

EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X

Group-B0 decoupling CAP Group-B1 decoupling CAP


MEM_B0 CLK MEM_B1 CLK
+1.5V_GPU +1.5V_GPU

VMB_CLK1

VMB_CLK0 C710 C709 C700 C701 C702 C707 C421 C423 C387 C730 C435 C425 C725 C703 C400 VMB_CLK1#

VMB_CLK0# EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X
R268 R270

R236 R237 EV@40.2/F_4 EV@40.2/F_4


+1.5V_GPU +1.5V_GPU
EV@40.2/F_4 EV@40.2/F_4

A C292 C689 C706 C694 C693 C291 C290 C361 C365 C705 C392 C342 C384 C378 C374 A
C414
C319 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@0.01U/25V_4X
EV@0.01U/25V_4X

+1.5V_GPU +1.5V_GPU

C442 C635 C201 C227 C662 C665 C437 C724 C313 C318 Quanta Computer Inc.
EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X
PROJECT : BD9
Size Document Number Rev
A1A
VRAM_B: DDR3*4PCS
Date: Tuesday, December 25, 2012 Sheet 21 of 41
5 4 3 2 1
5 4 3 2 1

<VGA>
+5V_S5

+3V
There is no restriction on
VDDR3 relative to other rails
22
R583
EV@100K_4

D D

1
C755
EV@4700P/25V_4X
Q35
2
+3V_GPU
EV@ME1303_3A
SLP_S3# 1 2 GPU +3V power
[7,33] SLP_S3#

3
D34 *EV@RB500V-40_100MA 0.5A

3
[7] PE_GPIO1 R584 EV@0_4 2 Q36 R535 EV@0_4
GPU_MAINON [40,41]
C752 C753 C754

1
R585 C758 EV@ME2N7002E_200MA
EV@10U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X
*EV@200K_4 EV@0.1U/10V_4X

RevB 1219 Change for EOD

C C

+3V

C399 EV@0.1U/10V_4X

5
U13
[7] PE_GPIO0 2
4 PERST#_BUF
PERST#_BUF [12]
[7,26,28] APU_PCIE_RST# 1

EV@TC7SH08FU(F)

3
B B

A A

Quanta Computer Inc.

5 4
www.vinafix.vn 3 2
Size

Date:
Document Number
PROJECT : BD9
Mars_M2/ PX5
Tuesday, December 25, 2012 Sheet
1
22 of 41
Rev
A1A
5 4 3 2 1

USB 3.0 Power


23
<USB> <U3B>
switch +3V_S5 +5V_S5 USB w S&C MAXIM solution <SLC>
1015 change Caps to 220uF
R339 U17
URL@10K_4 2 8 +5VSUS_USBP0
3 IN1 OUT3 7
IN2 OUT2 6
USB_SC_EN# 4 OUT1 C468 C469 + C761 C467 C471 R346
[33] USB_SC_EN# EN#
1
GND
C470
9
GND-C OC#
5 *URL@470P/50V_4X *URL@0.1U/10V_4X URL@220U/6.3V_105CS_E18e *URL@10U/6.3V_6X *URL@100U/6.3V_1206 URL@470/F_4
14566/14600/14617
URL@1U/16V_6X
URL@UP7534BRA8-15
R1 R2 R3 R4 R5 R6 R7
RevB 1219 Change for EOD 14566 V V V

3
D 14600 V V D
USB_SC_OC# Q20
USB_SC_OC# [7,33]
14617(no CB2) V V V
2

+5V_S5
14641/14642/14644 V V
URL@ME2N7002E_200MA 14640/14651 V V

1
C463

USB 3.0 CONN <U3B> <USB> <EMI> S&C@0.1U/10V_4X

U16 1015 Close to U2501 USBP8+


[8] USBP8+
USBP8-
[8] USBP8-

R336
R7 *S&C@10K_4 5
VCC TDP
6
7
USBP8+ R586
R587
NS&C@0_4
NS&C@0_4
Right-Low Side TDM
USBP8-

D35 *URL-3@AZ5125-01J USB3.0 Support S&C R335


R1 *S&C@0_4 CB1_CEN#_CB2 1
[33] USB_BUS_SW3 CB1/CEN#/CB2/INT#
R328 S&C@0_4 CB0_SDA 8
[33] USB_BUS_SW2 CB0/SDA
C760 *URL-3@15P/50V_4C R588 *URL-3@300_4
RP5 URL@0X2 +5VSUS_USBP0 1
CN23
SC_SDA R322
R2 *S&C@0_4 DP
3
2
USB_S&C_R
USB_S&C#_R
1 VBUS DM
USB_S&C#_R 2 1 USB_S&C#_R1 2
2 D- R3
USB_S&C_R 4 3 USB_S&C_R1 3
4 3 D+ 9 4 GND_CB1 R325
R4 S&C@0_4 USB_BUS_SW3
4 GND GND GND/CB1/SCL
[8] USB3_RXN0 USB3_RXN0
USB3_RXP0
R324
R327
URL-3@0_4
URL-3@0_4
USB3_RXN0_R
USB3_RXP0_R
5
6 5 SSRX- R321
R5 *S&C@0_4 SC_SCL
[8] USB3_RXP0 6 SSRX+
USB3_TXN0 R334 URL-3@0_4 USB3_TXN0_R C465 URL-3@0.1U/10V_4X USB3_TXN0_C
7
8 7 GND
S&C@MAX14641ETA+T
R326
R6 *S&C@0_4
[8] USB3_TXN0 8 SSTX-
[8] USB3_TXP0 USB3_TXP0 R338 URL-3@0_4 USB3_TXP0_R C466 URL-3@0.1U/10V_4X USB3_TXP0_C 9
9 SSTX+

13
12
11
10
URL-3@C19066-90905-L

13
12
11
10
RevB 1220 Add C.M Choke for EMI suggestion
Delete RP5, Add L15
ESD5
L15 USB3_TXP0_R 1 10 USB3_TXN0_R
USB_S&C#_R 2 1 USB_S&C#_R1 +5VSUS_USBP0 2 1 10 9
USB_S&C_R 3 2 1 4 USB_S&C_R1 3 VDD GND 8
C 3 4 USB_S&C#_R1 4 NC NC1 7 USB_S&C_R1 C
URL@MCM2012B900GBE USB3_RXP0_R 5 4 7 6 USB3_RXN0_R
5 6
*URL-3@AZ1065-06F

RevC 0130 update S&C table

+5V_S5 +5V_S5
SW2 SW3 14600 SW2 SW3 14641
CB0 CB1 Status CB0 CB1 Status

R319
0 0 Auto mode Charger , AM 0 0 2A Auto mode for Apple device Charger , AM2
0 1 Force dedicated charger mode Charger , FM 0 1 Force 1A for Apple device Charger , AP1
Co-Lay USB 2.0 CONN
*S&C@10K_4
<USB> <EMI> 1 0 Pass-Through(USB) mode USB , PM 1 0 Pass-Through(USB) mode USB , PM
2

1
Q19A
6 SC_SCL
1 1 pass-through(USB) with CDP USB , CM 1 1 pass-through(USB) with CDP USB , CM
[5,33] 2ND_MBCLK Emulation Emulation
*S&C@2N7002KDW_115MA CN22
+5VSUS_USBP0 1
1 VBUS
USB_S&C#_R1 2 SW2 SW3 14644 SW2 SW3 14642
2 D-
USB_S&C_R1 3
D13 4 3 D+
+5V_S5 +5V_S5 4 GND CB0 CB1 Status CB0 CB1 Status
*URL-2@AZ5125-01J USB3_RXN0_R 5
5 SSRX-
USB3_RXP0_R 6
7 6 SSRX+ 0 0 2A Auto mode for Apple device Charger , AM2 0 X 2A Auto mode for Apple device Charger , AM2
8 7 GND
USB3_TXN0_C
8 SSTX- 0 1 Force dedicated charger mode Charger , FM 1 0 Pass-Through(USB) mode USB , PM
USB3_TXP0_C 9
9 SSTX+
R320
1 0 Pass-Through(USB) mode USB , PM 1 1 pass-through(USB) with CDP USB , CM
13
12
11
10
Emulation
*S&C@10K_4
1 1 pass-through(USB) with CDP USB , CM
13
12
11
10
URL-2@UARC8-4K1986
Emulation
5

Q19B
4 3 SC_SDA
[5,33] 2ND_MBDATA

*S&C@2N7002KDW_115MA
B B

+3V_S5 +5V_S5
USB 3.0 CONN <U3B> <U2B> <EMI> Right-Up Side
USB3.0/USB2.0 Co-lay
C751 *URU-3@15P/50V_4C R582 *URU-3@300_4 CN19 1015 change Caps to 220uF
RP4 *URU@0X2 +5VSUS_USBP1 1 R318 U15
1 VBUS
[8] USBP9- USBP9- 2 1 USBP9-_R 2 URU@10K_4 2 8 +5VSUS_USBP1
2 D- IN1 OUT3
[8] USBP9+ USBP9+ 4 3 USBP9+_R 3 3 7
4 3 D+ IN2 OUT2 6
USB3_RXN1 R308 URU-3@0_4 USB3_RXN1_R 5 4 GND USB_NORMAL_EN# 4 OUT1 C456 C457 + C759 C455 C459 R323
[8] USB3_RXN1 5 SSRX- [33] USB_NORMAL_EN# EN#
[8] USB3_RXP1 USB3_RXP1 R309 URU-3@0_4 USB3_RXP1_R 6 1
7 6 SSRX+ 9 GND 5 *URU@0.1U/10V_4X *URU@10U/6.3V_6X URU@470/F_4
USB3_TXN1 R316 URU-3@0_4 USB3_TXN1_R C452 URU-3@0.1U/10V_4X USB3_TXN1_C 8 7 GND C454 GND-C OC# *URU@470P/50V_4X URU@220U/6.3V_105CS_E18e *URU@100U/6.3V_1206
[8] USB3_TXN1 8 SSTX-
[8] USB3_TXP1 USB3_TXP1 R317 URU-3@0_4 USB3_TXP1_R C453 URU-3@0.1U/10V_4X USB3_TXP1_C 9 URU@UP7534BRA8-15
9 SSTX+ URU@1U/16V_6X
13
12
11
10

URU-3@C19066-90905-L
RevB 1219 Change for EOD
RevB 1220 Add C.M Choke for EMI suggestion
13
12
11
10

ESD4
Delete RP4, Add L13

3
USB3_TXP1_R 1 10 USB3_TXN1_R
+5VSUS_USBP1 2 1 10 9 USB_NORMAL_OC# Q18
VDD GND USB_NORMAL_OC# [7,33]
L13 3 8
USBP9- 2 1 USBP9-_R USBP9-_R 4 NC NC1 7 USBP9+_R 2
USBP9+ 3 2 1 4 USBP9+_R USB3_RXP1_R 5 4 7 6 USB3_RXN1_R
3 4 5 6
URU@MCM2012B900GBE *URU-3@AZ1065-06F URU@ME2N7002E_200MA

1
USB 2.0 CONN (USB/B) <U2B> <EMI> Co-Lay USB 2.0 CONN <USB> <EMI>
RevB 1220 Add C.M Choke for EMI suggestion
Delete RP24,RP25, Add L26,L27
L27
CN12 USBP1+_R 3 4 USBP1+
USBP1-_R 2 3 4 1 USBP1- CN20
1 +5V_S5 2 1 +5VSUS_USBP1 1
2 1 VBUS
MCM2012B900GBE USBP9-_R 2
3 2 D-
USBP9+_R 3
4 L26 D33 4 3 D+
A 5 USBP0+_R 3 4 USBP0+ USB3_RXN1_R 5 4 GND A
6 3 4 *URU-2@AZ5125-01J 5 SSRX-
USBP0-_R 2 1 USBP0- USB3_RXP1_R 6
7 2 1 7 6 SSRX+
8 MCM2012B900GBE USB3_TXN1_C 8 7 GND
9 USB3_TXP1_C 9 8 SSTX-
10 9 SSTX+
13
12
11
10

11
12 USBP1+_R RP25 4 3 *0X2
USBP1+ [8]
13
12
11
10

13 USBP1-_R 2 1 URU-2@UARC8-4K1986
14 USBP1- [8]
15 USBP0+_R RP24 4 3 *0X2
16 USBP0+ [8]
USBP0-_R 2 1
17 USBP0- [8]
18
19
20
USB_DB_OC#
USB_DB_EN#
[7,33]
[33]
Quanta Computer Inc.
88511-200N R443 10K_4 +3V_S5 PROJECT :BD9
1005 Update FP Size Document Number Rev
RevB 1130 Change R443 PU from USB_DB_OC# to USB_DB_EN# USB2.0/USB3.0 A1A

Date: Wednesday, January 30, 2013 Sheet 23 of 41


5 4 3 2 1
5 4 3 2 1

+3V
40mils
L25 LDS@HCB1608KF-221T20_2A

C590 C587
AVCC33
Close to chip

C585 C578 LDS@0.1U/10V_4X


24
LDS@10U/6.3V_6X LDS@0.1U/10V_4X LDS@0.1U/10V_4X INT_LCD_TXLOUT0- [30]

INT_LCD_TXLOUT0+ [30]

TRAVIS_BL_EN
D +3V D

MODE_CFG1

MODE_CFG0
DVCC33 INT_LCD_TXLOUT1- [30]
80mils

VCCK_V12
MIICSDA
MIICSCL
INT_LCD_TXLOUT1+ [30]
L23 LDS@HCB1608KF-221T20_2A
INT_LCD_TXLOUT2- [30]
C575 C572 C573 C577 C30
INT_LCD_TXLOUT2+ [30]
LDS@0.1U/10V_4X LDS@10U/6.3V_6X LDS@22U/6.3V_6X LDS@0.1U/10V_4X LDS@0.1U/10V_4X

L24 *LDS@TLPC3010C-4R7M Close to PIN17

49

48

47

46

45

44

43

42

41

40

39

38

37
U20
PIN17 R45 LDS@0_6 VCCK_V12

TXO0-

TXO1-

TXO2-
MODE_CFG1

MODE_CFG0

MIICSCL

TXO0+

TXO1+

TXO2+
MIICSDA

VCCK
EPAD_GND

BL_EN
60mils C37 C583
PD at APU side 0918 FAE suggest
C2611 used 22uF X5R LDS@22U/6.3V_6X LDS@0.1U/10V_4X
R421 LDS@1K_4 INT_LVDS_HPD_R 1 36 L2602 used TLPC3010C-4R7M
[5,30] INT_LVDS_HPD DP_HPD TXOC- INT_LCD_TXLCLKOUT- [30]
R420 LDS@100K_4 TEST_MODE 2 35
TEST_MODE TXOC+ INT_LCD_TXLCLKOUT+ [30]
R419 LDS@0_4 AUX_CH_N 3 34 2.2-uH(L2602) 0 Olm(R2618)
[5] INT_LVDS_AUXN AUX_CH_N TXO3-
R418 LDS@0_4 AUX_CH_P 4 33 SWR Connect NC
[5] INT_LVDS_AUXP AUX_CH_P TXO3+
AVCC33 5 32 LDO NC Connect
DP_V33 TXE0- INT_LCD_TXUOUT0- [30]
6 31

RTD2136R