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A Three-phase PWM AC-DC Converter with Low

Switching Frequency and High Power Factor Using

DSP-Based Repetitive Control Technique
Shih-Liang Jung, Hsiang-Sung Huang, and Ying-Yu TZOU,Member, IEEE

Power Electronics and Mechatronics Control Lab.,

Department of Electrical and Control Engineering, National Chiao Tung U'niv., Taiwan, R.O.C.

Abstract- This paper presents a novel digital control system is difficult to sta.bilize if the relative resistance
scheme for PWM AC-DC converters with low switching of the power circuit is low. The hysteresis current
frequency used in high-power applications. The proposed control scheme features as fast dynamic response and
scheme incorporates an inner current loop with an outer easy implementation [41, [5]. There's no dc offset in
voltage loop to improve input power factor and regulate the current at ac side. But the variable switching
the output dc-link voltage. The inner current loop consists
frequency imposes excessive stress on power devices.
of a predictive controller and a repetitive controller. The
outer voltage loop is composed of a digital PI controller Another kind of control strategy named the predictive
and a load current compensator. A PWM AC-DC current control with fixed switching frequency (PCFF)
converter employing DSP control has been constructed to was proposed in [6]. It combines many advantages of
verify the proposed control scheme. A nearly unit input the aforementioned methods such as fixed switching
power factor can be achieved even with a low switching frequency, good transient response, and simplicity. The
frequency. Experimental results confirm the feasibility command for controlling line current is derived based
and features of the proposed repetitive control scheme for on the parameters of the power circuit and the
unit power factor regulation. switching frequency. This implies that the PCFF
algorithm is parameter dependent. Unfortunately, these
I. INTRODUCTION parameters, such as inductor and resistance, vary with
temperature, nonlinearity, and saturation of magnetic
The line disturbance and injected harmonics caused components. The effect of parasitic elements, which
by nonlinear loads have drawn much concern recently can not be measured in advanced, will also be excited
due to the growing demand for high-quality utility as the switching frequency becomes high. The major
power. The conventional diode rectifiers and phase- defeat of PCFF is that the control law requires
controlled rectifiers, which were used for AC-DC relatively high sampling as well as switching frequency
conversion in the past, have the drawbacks of poor (> 3kwz) to guarantee its performance [7]. At low
efficiency and low power factor. To solve these sampling frequency, thle phase delay will result in
problems, PWM AC-DC converter has been adopted in periodic error in ac current waveform and severely
many industrial applications owing to the advantages degrade the control accuracy. The unity power factor
of reduced line current harmonics and reversible power will no longer be obtained under such a condition. This
flow. Moreover, it is possible for a PWM AC-DC renders PCFF unsuitable for high-power applications.
converter to sink nearly sinusoidal current at ac side Repetitive control theory [8]-[ lo], which originates
and thus raise the power factor. However, it's not an from internal model principle [ 1 13, provides a solution
easy task to control the switching devices of the AC- to eliminate periodic errors in a dynamic system. A
DC converter so that both unity power factor and fast number of modified repetitive control schemes have
dynamics can be achieved especially in high power been developed for various industrial applications.
applications where three-phase operation and low Moreover, repetitive control theory has also been
switching frequency are necessary. applied to PWM inverters used for generating high-
Many schemes for controlling PWM AC-DC quality sinusoidal output voltage in AC power sources
converter have been proposed. The phase and [12]. The inherent periodic nature in the operation of a
amplitude control provides good steady-state response ac-to-dc converter makes it a good application of
with reduced current harmonics and low voltage ripple repetitive control theory.
[1]-[3]. However, the response at the instant of load This paper presents a novel fully digital control
transition is beyond what we can accept due to the dc scheme, which can achieve high power factor even
offset contained in ac side current. In addition, the under low switching and low sampling frequency, for a
three-phase AC-DC contverter. The proposed control
This work was supported by the National Science Council,
Taipei, Taiwan, R.O.C. Project no. NSC 85-2213-E-009-127.
scheme consists of two parts: ac current loop and dc
voltage loop. Current loop employs an auxiliary

0 1998 IEEE
0-7803-4489-8/98/$10.00 517
and the power flow can be even reversed. The ratings
A l l

of inductors and switches can be reduced due to a
higher utilization factor. For high-power applications,
the configuration shown in Fig. 1 is usually employed
owing to its advantages of good current quality, high
efficiency, and low EMI.
Because of the coupling effect between each phase,
the dynamic model of the converter shown in Fig. 1
will be somewhat complicated if the system behavior is
Fig. 1. Three-phase PWM AC-DC converter. expressed in terms of phase variables. The three-phase
dependent variables of a 3-phase PWM converter can
be transformed to their corresponding independent
two-axis variables in an orthogonal d-q frame by the

Owing to the mutually decoupling nature, the dynamic

model of a three-phase AC-DC converter on d-q plane
Input stage Output stage
can be treated as two single-phase converters with
CO) independent control. The design can be performed on
Fig 2. (a) Equivalent circuit of a single-phase PWM AC-DC d-q frame using single-phase dynamics. Fig. 2(a)
converter and (b) its block diagram representation. shows the circuit schematics of a single-phase PWM
AC-DC converter and its block diagram representation
repetitive controller to mount upon the well-known is shown in Fig. 2(b). This paper proposes ‘a control
PCFF so that the inherent periodic error caused by low scheme to achieve both unity power factor control and
switching frequency can be suppressed. As to the output voltage regulation. The proposed control
voltage loop, a digital PI controller with load current scheme consists of two parts: an inner current-loop
compensation is designed to regulate the dc-link controller and an outer voltage-loop controller. All the
voltage such that the ripple can be minimized. To control laws described in the following are designed
verify the proposed control scheme, a digital controller based on the decoupled d-q model.
based on DSP TMS32OC14 was constructed to realize
the algorithm. This paper is organized as follows:
section I1 derives the dynamic model of the PWM AC- 111. CURRENT-LOOP
DC converter. Section I11 describes the design of Th current loop of a power converter plays an
current-loop controller. Section IV shows the design important role in its system regulation. Power
process of the voltage-loop controller. Section V converters without current mode control will encounter
illustrates some simulation as well as experimental more challenging control loop design problems in its
results. A short conclusion is given in the last section. voltage regulation, especially load with large
uncertainties. To ease the outer loop design and
eliminate the effect of inductor dynamics, ri current
loop controller is employed for the control of 3-phase
Fig. 1 shows a typical PWM controlled three-phase PWM converters. In addition, the input power factor
AC-DC converter. The input inductors are used to control also depends on the synchronously regulation
suppress line current harmonics and the dc-link of the input current.
capacitor is used to smooth output dc voltage. With A two-layer control scheme, as shown in Fig. 3, was
proper control of the PWM switches, the dc-link developed to regulate the current loop. The predictive
capacitor can be minimized, the output dc voltage can controller in the inner layer is used for the fast current
be regulated, the input power factor can be controlled, tracking and the repetitive controller in the outer layer,

Repetitive sampler

R Y I Irr 1 I I
Digital cnnt~otler Physical system

Fig. 4. Block diagram of inner current loop under predictive control.

Fig. 3. Two-layer architecture of current-loop controller.

adopts repetitive control technique to eliminate

periodic errors caused by low-frequency switching and
other unknown nonlinear effects.
A. Predictive Controller
Fig. 5. Perio'dic signal generator.
Predictive control is an inverse model control
scheme [ 6 ] .The PWh4 output voltage (vJ, as shown in
Fig. 2, can be obtained by B. Repetitive Controller
The basic concept of repetitive control theory
vi = v , -L--i,r,. (3) originates from the internal model principle [ 111. The
dt principle states that the loutput of a control system can
Differentiation of the inductor current can be track the reference input without steady-state error if
approximated by the model that generates the same reference is included
in the closed-loop system. For example, if a system is
di, if. - i, required to track a step input without steady-state error,
-z-, (4)
dt T, the model of the step function, i.e. I/s, should be
included in its loop tranlsfer function. Similarly, if one
where if denotes the current command, i t is the wants to eliminate exogenous disturbances, the same
measured value of inductor current, and T, is the requirements should also be met since the disturbances
sampling period of the current loop. The digital can be viewed as external input to the system
realization of (3) can be expressed as concerned.
To implement a repetitive control system, a periodic
actuating signal used to cancel the periodic disturbance
must be generated. A periodic signal can be generated
It is assumed that both the sampling and switching with a given initial condition as shown in Fig. 5. The
frequencies are high enough so that the controlled positive number N denotes the number of samples
current can reach to its reference command at the next taken in one period. If this periodic signal generator
sampling instant. Fig. 4 shows the block diagram of can be synthesized into a feedback system with
the inner current loop under predictive control. asymptotic stability, it is possible to track a periodic
It follows from the above analysis that the command or reject a cyclic disturbance with the same
predictive control scheme is similar to the deadbeat period. In practical applications, however, a
control scheme. This implies that the effectiveness of disturbance usually contaLins rich high-order harmonics.
the predictive controller is highly depend on the circuit This makes it impossible for the systems with limited
parameters, which is hard to be accurately measured in bandwidth to complelely eliminate the external
practice. Moreover, in high-power applications, where disturbance.
low-frequency switching is a must, the performance of Fig. 6 illustrates the proposed repetitive control
predictive controller will severely degraded due to scheme, where Q(z') represents a band-limit filter and
inevitable phase delay and current distortion. Since the S ( z ' ) is a post-delay filter. The basic servo plant is the
current error caused by the above defeats happens to be current controlled AC-DIC converter. As illustrated in
periodic, we can detect its periodic nature and try to Fig. 6, the repetitive controller functions as an auxiliary
suppress it. In this paper, a practical repetitive control controller that modifies the original actuating signal by
scheme is developed to eliminate periodic current adding a periodic compensation signal. For a periodic
errors. disturbance, the main delay loop will attenuate its
effect to the nominal control loop. However, faster
convergence of the periodic error will result a system
will smaller stability margins. In designing a repetitive

controller, one should make a compromise between the
error convergence rate and the stability margin. AC-DC converter

Compensators Q ( 8 ) and S(Z') in the repetitive control

loop is synthesized to compromise the tradeoff.
The function of band-limit filter Q(z-I) within the

I current-loov I
main delay loop is to relieve the stringent stability
voltage-loop 1-- yo
requirement for the repetitive controller to completely controller *
reject the periodic disturbance. It has the form of
z-I+2+z 1,
Q(z-') = (6)
4 '
Fig. 7. Signal flow diagram of voltage control loop.
which is a weighted moving-average smoothing filter.
This filter has an advantage of zero phase shift and no less than one. With the postdelay filter defined above,
further delay will be introduced. The low-pass the repetitive compensation signal added to the
characteristics of Q ( z ' ) also put more attenuation in nominal control loop can be kept in phase with the
minimizing lower order harmonics. The stability cyclic reference or disturbance so that the periodic
margin can then be greatly improved with a little error can be suppressed on time.
sacrifice in system bandwidth. With narrower
bandwidth, the periodic disturbance can only be
suppressed to some extent rather than thoroughly IV. VOLTAGE-LOOP
The post-delay filter S ( z ' ) compensates both the Fig. 7 shows the control block diagram of the outer
phase delay of the basic servo plant and the main delay voltage loop controller. As shown in this graph, this
loop such that the repetitive control signal can keep the control loop is highly nonlinear due to the
same phase with the cyclic disturbance to be eliminated. multiplication for generating current command. To
It has the form of facilitate further analysis and design, the system
concemed should first be linearized. Based on the
(7) assumption that no power consumed between input
stage and output stage, the following equation, which
where N is the number of samples fetched in one period. concems about the power flow of the converter, can be
M, as defined in the following, is the equivalent delay obtained as
samples of the basic servo plant and the main delay
loop: 3vi + 3-(d -Li 2 ) = ):v( + 2,
dt 2 ro

where v and i denote the rms value of input voltage and

input current, respectively. r, represents the load
where B is the phase delay of the basic servo plant and resistance and v, is the output dc voltage. By adding a
main delay loop at the frequency of the periodic signal. small-signal perturbation and disregarding high-order
The factor g concems about the convergence rate of the terms, we can linearize (9) as
cyclic error and should be set as a positive real number



Fig. 8. Block diagram of outer voltage loop.

Fig. 9. PC-based DSP control of a power converter.
d 1 3 d 31 1-
(-+-)?, =-(LZ-+V)i +--;--io (10)
dt CR, CV, dt cv, c KO,= -.V O
where the uppercase letters represent dc operating
points of the corresponding variables and the lowercase A digital PI controller G!,(z) is employed to regulate the
letters with hat represent their small-signal output dc voltage
perturbations. According to (10), the following transfer
functions can be obtained: G,(z) = K , +-.KiTv
3v The corresponding g i h are designed using a
= T,(s) optimization technique so that the voltage loop can
achieve fast dynamic response [ 131.

A 2 kVA PWM AC-DC converter has been used for
experimental verification. Digital signal processors
from Texas Instruments have been used to realize the
proposed repetitive control scheme for PWM AC-DC
The far away zero of T,(s)has been neglected due to its converters. Fig. 9 shows the system architecture of a
insignificant effect. Fig. 8 depicts the small-signal PC-based DSP control card for the control of PWM
linear model of the voltage loop together with the power converters. The DSP card consists of two DSPs:
proposed compensation scheme. It is noted that the TMS320C14 and TMS3120C52. The TMS32OC14 takes
zero-order holder for digital realization and the sensor charge of the execution of the designed control laws
filter have been included in the model. According to and the management of d l U 0 ports. The TMS320C52
this model, the output voltage can be expressed as is responsible for data monitoring and on-line
parameter tuning.
vo(s)= m ( ~ ) ~ , , ( s ) ~ , ( s ) v +
:(s) (13) A window-based interactive digital control software
was used for the develolpment of the control software.
(K,T,(s) - T*(S))li,(S) Communication between these two processors is
and the output impedance is completed by a set of dual-port RAM. TMS32OC14
fetches feedback signals through multiplexer (ADG508)
and A/D converter (AID 1674), then computes the
required pulsewidth of switching devices according to
the control algorithm. The control parameters are
where stored in dual-port R4M and can be tuned by
TMS32OC52. The host PC can access any data of the
system with the aid of' TMS32OC52 and show the
requested waveform on fhe screen,
Some relevant paraimeters for the experimental
verification are listed in the appendix. To demonstrate
and T, is the sampling period of the outer voltage loop. the proposed control scheme, the P W M switching
To achieve zero output impedance, the gain KOis set as frequency was set at 1.2 kHz and this is relatively low
compared with conventional power factor control

hp stoppal hp Stopped

1 1.00 V / d l Y
Off9eli-50.00 V .
10.00 z I dc

4 8.00 viaiv 4 8.00

Dff6et' 0.000 v Off8St' 0
200.0 I I ac 200.0 ?

-,a,oooo .* 7.00000 -4 3 2 . 0 0 0 0 ms
5.00 mnldlv
CUrrenl .I"l.". .=XI"". average
Vp-p(4) 41.7500 V 41.7500 V 41.7500 V 41.7500 V
4 f 7.510 V

. . . hp stoppea
1 1.00 V / d l v
Off5e1i-50.00 .v
10.00 I I dc

4 8.00 V l d l V
OffSSti 0.000 v 4 8.00 Vldlv
200 0 : I ac o f f 5 e l ' 0.000 v
200.0 , + ac
- 1 7 0000 .* 8.00000 .6 33.0000 I S
5 . 0 0 B51dlY -18.0000 .* 7.00000 -8 32.0000 ms
5 . 0 0 .S/dlY

4 f 0.000 v
Fig. 10. AC-side current response (rectifying mode) (a) without
repetitive controller, and (b) with repetitive controller. Fig. 12. AC-side current response (regeneration mode) (a) without
repetitive controller, and (b) with repetitive controller.

1 3 00 V l d l v
OffSSti 0.000 v
10.00 I I dc

4 1 0 . 0 V/dlY
O f I P B t i 90.00 v
200.0 8 I dc
500 me
1 i i ; 1 :
5 50000 P .
I I 1 I
255 500 mS
50 0 .S/dl"

hp slopped

Fig. 11. X-Y plot of current error in d-q frame.

schemes. Fig. 10 shows the input current response of

the digitally controlled PWM AC-DC converter. It
follows that the proposed repetitive controller does
improve both the tracking performance and power
factor. The input current can be controlled to be in
phase with utility voltage.
Fig. 11 shows the periodic tracking error in d-q
reference frame. It is obvious that the error caused by
low switching frequency has been greatly reduced after Fig. 13. Output dc voltage as load changes from lOORto 5 0 0 .
the repetitive controller applied. Fig. 12 illustrates (a)with load current compensation. (b) without load current
experimental result of the PWM converter when it was compensation.
operating in its regeneration mode. Same performance
can still be achieved even though the power flow is can be observed that the compensation of load current
reversed. With a well-controlled inner current loop, the is effective for output voltage regulation under load
outer voltage loop can be easily designed. Fig. 13 variation. The results illustrated above verify the
shows the dc output voltage of the AC-DC converter superiority of the proposed digital control scheme.
when the load resistance undergoes 100% change. It


This paper presents a novel digital control scheme TABLE I

for PWM AC-DC converters used in high-power RELEVANTPARAMETERS
applications, where low switching frequency is
necessary. Two control loops are involved in the
proposed control scheme. The inner current loop Inductor, L,
concerns about the current tracking performance and I ESRofinductor, a0 1 0.5 I Q I
the power factor at ac side. The outer voltage loop is 940 pF
used to regulate the dc output voltage. The load current 0.1 R
also has been taken as feedback to improve the output

11 1
impedance such that the dc-lmk voltage can be kept Rated load resistance, R, 100 R
constant under a large load disturbance. Simulation and 100 V
experimental results show consistent agreement with 20 V(peak)
the analysis. The proposed digital control scheme does 1.2 kHz
help reducing switching frequency as low as 1.2 lcHz T, 416 fi s
while unity power factor and output voltage regulation
can still be maintained. Experimental results show that Voltage-loop sampling time, T, 2A03 ms
the proposed control scheme is very promising for Control parameter, A4
high-power applications where low frequency Control parameter, N
switching is inevitable. Control parameter, g
Control parameter, Kp 0.4
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