Abstract This paper presents a novel digital control system is difficult to sta.bilize if the relative resistance
scheme for PWM ACDC converters with low switching of the power circuit is low. The hysteresis current
frequency used in highpower applications. The proposed control scheme features as fast dynamic response and
scheme incorporates an inner current loop with an outer easy implementation [41, [5]. There's no dc offset in
voltage loop to improve input power factor and regulate the current at ac side. But the variable switching
the output dclink voltage. The inner current loop consists
frequency imposes excessive stress on power devices.
of a predictive controller and a repetitive controller. The
outer voltage loop is composed of a digital PI controller Another kind of control strategy named the predictive
and a load current compensator. A PWM ACDC current control with fixed switching frequency (PCFF)
converter employing DSP control has been constructed to was proposed in [6]. It combines many advantages of
verify the proposed control scheme. A nearly unit input the aforementioned methods such as fixed switching
power factor can be achieved even with a low switching frequency, good transient response, and simplicity. The
frequency. Experimental results confirm the feasibility command for controlling line current is derived based
and features of the proposed repetitive control scheme for on the parameters of the power circuit and the
unit power factor regulation. switching frequency. This implies that the PCFF
algorithm is parameter dependent. Unfortunately, these
I. INTRODUCTION parameters, such as inductor and resistance, vary with
temperature, nonlinearity, and saturation of magnetic
The line disturbance and injected harmonics caused components. The effect of parasitic elements, which
by nonlinear loads have drawn much concern recently can not be measured in advanced, will also be excited
due to the growing demand for highquality utility as the switching frequency becomes high. The major
power. The conventional diode rectifiers and phase defeat of PCFF is that the control law requires
controlled rectifiers, which were used for ACDC relatively high sampling as well as switching frequency
conversion in the past, have the drawbacks of poor (> 3kwz) to guarantee its performance [7]. At low
efficiency and low power factor. To solve these sampling frequency, thle phase delay will result in
problems, PWM ACDC converter has been adopted in periodic error in ac current waveform and severely
many industrial applications owing to the advantages degrade the control accuracy. The unity power factor
of reduced line current harmonics and reversible power will no longer be obtained under such a condition. This
flow. Moreover, it is possible for a PWM ACDC renders PCFF unsuitable for highpower applications.
converter to sink nearly sinusoidal current at ac side Repetitive control theory [8][ lo], which originates
and thus raise the power factor. However, it's not an from internal model principle [ 1 13, provides a solution
easy task to control the switching devices of the AC to eliminate periodic errors in a dynamic system. A
DC converter so that both unity power factor and fast number of modified repetitive control schemes have
dynamics can be achieved especially in high power been developed for various industrial applications.
applications where threephase operation and low Moreover, repetitive control theory has also been
switching frequency are necessary. applied to PWM inverters used for generating high
Many schemes for controlling PWM ACDC quality sinusoidal output voltage in AC power sources
converter have been proposed. The phase and [12]. The inherent periodic nature in the operation of a
amplitude control provides good steadystate response actodc converter makes it a good application of
with reduced current harmonics and low voltage ripple repetitive control theory.
[1][3]. However, the response at the instant of load This paper presents a novel fully digital control
transition is beyond what we can accept due to the dc scheme, which can achieve high power factor even
offset contained in ac side current. In addition, the under low switching and low sampling frequency, for a
threephase ACDC contverter. The proposed control
This work was supported by the National Science Council,
Taipei, Taiwan, R.O.C. Project no. NSC 852213E009127.
scheme consists of two parts: ac current loop and dc
voltage loop. Current loop employs an auxiliary
0 1998 IEEE
0780344898/98/$10.00 517
and the power flow can be even reversed. The ratings
A l l
I4
of inductors and switches can be reduced due to a
higher utilization factor. For highpower applications,
the configuration shown in Fig. 1 is usually employed
CT
owing to its advantages of good current quality, high
I
efficiency, and low EMI.
Because of the coupling effect between each phase,
the dynamic model of the converter shown in Fig. 1
will be somewhat complicated if the system behavior is
Fig. 1. Threephase PWM ACDC converter. expressed in terms of phase variables. The threephase
dependent variables of a 3phase PWM converter can
be transformed to their corresponding independent
twoaxis variables in an orthogonal dq frame by the
followings
518
Repetitive sampler
Controller
R Y I Irr 1 I I
Inductor
Command,
Digital cnnt~otler Physical system
519
controller, one should make a compromise between the
error convergence rate and the stability margin. ACDC converter

I currentloov I
main delay loop is to relieve the stringent stability
voltageloop 1 yo
requirement for the repetitive controller to completely controller *
yo
reject the periodic disturbance. It has the form of
zI+2+z 1,
Q(z') = (6)
4 '
Fig. 7. Signal flow diagram of voltage control loop.
which is a weighted movingaverage smoothing filter.
This filter has an advantage of zero phase shift and no less than one. With the postdelay filter defined above,
further delay will be introduced. The lowpass the repetitive compensation signal added to the
characteristics of Q ( z ' ) also put more attenuation in nominal control loop can be kept in phase with the
minimizing lower order harmonics. The stability cyclic reference or disturbance so that the periodic
margin can then be greatly improved with a little error can be suppressed on time.
sacrifice in system bandwidth. With narrower
bandwidth, the periodic disturbance can only be
suppressed to some extent rather than thoroughly IV. VOLTAGELOOP
CONTROLLER
rejected.
The postdelay filter S ( z ' ) compensates both the Fig. 7 shows the control block diagram of the outer
phase delay of the basic servo plant and the main delay voltage loop controller. As shown in this graph, this
loop such that the repetitive control signal can keep the control loop is highly nonlinear due to the
same phase with the cyclic disturbance to be eliminated. multiplication for generating current command. To
It has the form of facilitate further analysis and design, the system
concemed should first be linearized. Based on the
(7) assumption that no power consumed between input
stage and output stage, the following equation, which
where N is the number of samples fetched in one period. concems about the power flow of the converter, can be
M, as defined in the following, is the equivalent delay obtained as
samples of the basic servo plant and the main delay
loop: 3vi + 3(d Li 2 ) = ):v( + 2,
(9)
dt 2 ro
520
m.....
I
filter
1
V. EXPERIMENTAL
VERIFICTION
A 2 kVA PWM ACDC converter has been used for
experimental verification. Digital signal processors
from Texas Instruments have been used to realize the
proposed repetitive control scheme for PWM ACDC
The far away zero of T,(s)has been neglected due to its converters. Fig. 9 shows the system architecture of a
insignificant effect. Fig. 8 depicts the smallsignal PCbased DSP control card for the control of PWM
linear model of the voltage loop together with the power converters. The DSP card consists of two DSPs:
proposed compensation scheme. It is noted that the TMS320C14 and TMS3120C52. The TMS32OC14 takes
zeroorder holder for digital realization and the sensor charge of the execution of the designed control laws
filter have been included in the model. According to and the management of d l U 0 ports. The TMS320C52
this model, the output voltage can be expressed as is responsible for data monitoring and online
parameter tuning.
vo(s)= m ( ~ ) ~ , , ( s ) ~ , ( s ) v +
:(s) (13) A windowbased interactive digital control software
A
was used for the develolpment of the control software.
(K,T,(s)  T*(S))li,(S) Communication between these two processors is
and the output impedance is completed by a set of dualport RAM. TMS32OC14
fetches feedback signals through multiplexer (ADG508)
and A/D converter (AID 1674), then computes the
required pulsewidth of switching devices according to
the control algorithm. The control parameters are
where stored in dualport R4M and can be tuned by
TMS32OC52. The host PC can access any data of the
system with the aid of' TMS32OC52 and show the
requested waveform on fhe screen,
Some relevant paraimeters for the experimental
verification are listed in the appendix. To demonstrate
and T, is the sampling period of the outer voltage loop. the proposed control scheme, the P W M switching
To achieve zero output impedance, the gain KOis set as frequency was set at 1.2 kHz and this is relatively low
compared with conventional power factor control
521
hp stoppal hp Stopped
1 1.00 V / d l Y
Off9eli50.00 V .
10.00 z I dc
,a,oooo .* 7.00000 4 3 2 . 0 0 0 0 ms
5.00 mnldlv
CUrrenl .I"l.". .=XI"". average
Vpp(4) 41.7500 V 41.7500 V 41.7500 V 41.7500 V
4 f 7.510 V
. . . hp stoppea
1 1.00 V / d l v
Off5e1i50.00 .v
10.00 I I dc
4 8.00 V l d l V
OffSSti 0.000 v 4 8.00 Vldlv
200 0 : I ac o f f 5 e l ' 0.000 v
200.0 , + ac
 1 7 0000 .* 8.00000 .6 33.0000 I S
5 . 0 0 B51dlY 18.0000 .* 7.00000 8 32.0000 ms
5 . 0 0 .S/dlY
4 f 0.000 v
(b1
Fig. 10. ACside current response (rectifying mode) (a) without
repetitive controller, and (b) with repetitive controller. Fig. 12. ACside current response (regeneration mode) (a) without
repetitive controller, and (b) with repetitive controller.
1 3 00 V l d l v
OffSSti 0.000 v
10.00 I I dc
4 1 0 . 0 V/dlY
O f I P B t i 90.00 v
200.0 8 I dc
!
244
L
500 me
1 i i ; 1 :
5 50000 P .
I I 1 I
255 500 mS
'
50 0 .S/dl"
hp slopped
522
VI. CONCLUSION AIPPENDIX
11 1
impedance such that the dclmk voltage can be kept Rated load resistance, R, 100 R
constant under a large load disturbance. Simulation and 100 V
experimental results show consistent agreement with 20 V(peak)
the analysis. The proposed digital control scheme does 1.2 kHz
help reducing switching frequency as low as 1.2 lcHz T, 416 fi s
while unity power factor and output voltage regulation
can still be maintained. Experimental results show that Voltageloop sampling time, T, 2A03 ms
the proposed control scheme is very promising for Control parameter, A4
highpower applications where low frequency Control parameter, N
switching is inevitable. Control parameter, g
Control parameter, Kp 0.4
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