It gives you full knowledge of logic circuits design which is very helpful for the student to prepare for their semesters.

© All Rights Reserved

21 views

It gives you full knowledge of logic circuits design which is very helpful for the student to prepare for their semesters.

© All Rights Reserved

- Binary, Decimal and Hexadecimal Numbers
- Digital Integrated Circuits – Logic Families
- Digital Electronics
- 37XR Calibration Procedure
- CSC 204 - 3.1 and 3.2 Study Guide
- ch-2
- va903m-3_sm
- Comparison of i c Logic Families
- Electronic Circuit
- Atmos Modbus Protocol 20131212
- EC1312 & EC1362 Syllabus
- Nte 7482
- 68000 - 68010 - 68020 Primer - eBook-ENG.pdf
- Lecture 01
- Dld Lecture 1
- co_int_I_QP
- Ch03 Logic Gates (New).pdf
- ECONV-PT100 Manual.pdf
- question .pdf
- datasheetarchive max232

You are on page 1of 206

This book has been prepared as per Anna University syllabus, 2017 regulation.

EE8351 DIGITAL LOGIC CIRCUITS

OBJECTIVES:

• To study various number systems and simplify the logical expressions using Boolean functions.

UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES

Review of number systems, binary codes, error detection and correction codes (Parity and

Hamming code) - Digital Logic Families -comparison of RTL, DTL, TTL, ECL and MOS families

-operation, characteristics of digital logic family.

1.1 Review of number systems, binary codes

We will see various number systems by briefly describing the parameters that are common to all

number systems. Understanding of these parameters and their relevance to number systems is

fundamental to the understanding of how various systems operate.

Different characteristics that define a number system include the number of independent digits

used in the number system, the place values of the different digits constituting the number and

the maximum numbers that can be written with the given number of digits.

Among the three characteristic parameters, the most fundamental is the number of

independent digits or symbols used in the number system. It is known as the radix or base of the

number system. The decimal number system with which we are familiar is said to have a radix of

10 as it has 10 independent digits. i.e., 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.

Similarly, the binary number system with only two independent digits 0 and 1 is a radix-2

number system. The octal and hexadecimal number systems have a radix (or base) of 8 and 16.

The radix of the number system determines the other two characteristics. The place values of

different digits in the integer part of the number are given as r0, r1, r2, r3 and so on which starts

with the digit adjacent to the radix point.

For the fractional part, these are r-1, r-2, r-3 and so on. Again starting with the digit next to the

radix point where r is the radix of the number system. Also, maximum numbers that can be

written with it digits in a given number system are equal to r n.

Decimal numbers

The invention of decimal number systems is the most important factor in the development of

science and technology. The term decimal comes from the Latin word ten. The decimal number

system uses positional number representation which means that the value of each digit is

determined by its position in a number.

The base of a number system is the number of symbols that the system contains. The decimal

system has ten symbols namely 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. In other words, it has a base of 10. Each

position in the decimal system is 10 times more significant than the previous position.

For example, let us consider the four-digit number 2725:

in the 103 position has a

different value than the

2 in the 101 position. The

value of a decimal number is determined by multiplying each digit of the number by the value of

the position in which the digit appears and then the products are added. Thus, the number 2725

is interpreted as,

In this case, 5 is the least significant digit (LSD) and the leftmost 2 is the most significant digit

(MSD).

In general, in a number system with a base or radix r, the digits used are from 0 to r -1. The

number can be represented as,

...(1)

for n = 0, 1, 2, 3, ...

For numbers between 0 and 1 (i.e., fractions), the following equation holds:

...(2)

where,

Binary numbers

The binary numbers has a radix of 2. As r = 2, only two digits are needed and these are

0 and 1. A binary digit is 0 or 1 which is called as a bit. Like the decimal system, binary is a

positional system except that each bit position corresponds to a power of 2 instead of a power of

10.

In digital systems, the binary number system and other number systems are closely related to it.

However, people use the decimal number system since digital systems provides conversion

between decimal and binary numbers. The decimal value of a binary number can be formed by

multipIying each power of 2 by either 1 or 0 and the values are added.

Advantages:

Logic operations are the backbone of any digital computer though solving a problem on

computer involves an arithmetic operation. The introduction of the mathematics of logic by

George Boole laid the foundation for the modern digital computer.

He reduced the mathematics of logic to a binary notation of '0' and '1'. As the mathematics of

logic was well established and had proved itself to be quite useful in solving all kinds of logical

problem. The mathematics of logic (also known as Boolean algebra) is reduced to a binary

notation where the binary number system had a clear edge over other number systems for use

in computer systems.

Another significant advantage of this number system is that all kinds of data could be

conveniently represented in terms of 0’s and 1’s. Also, basic electronic devices used for

hardware implementation is conveniently and efficiently operated in two distinctly different

modes. For example, a bipolar transistor could be operated either in cut-off or in saturation

mode.

Lastly, the circuits required for performing arithmetic operations such as addition, subtraction,

multiplication, division, etc., is simple when the data involved are represented in the form of 0’s

and 1’s.

Problems

Example 1:

Solution:

Given:

N = 101010

...from above

equation(1)

= 32 + 0 + 8 + 0 + 2 + 0

= 42

An alternative method of converting from binary to decimal begins with the leftmost bit and

works down to the rightmost bit. It starts with a sum of 0. At each step , the current sum is

multiplied by 2 and the next digit to the right is added to it.

Example 2:

Solution:

Given:

N = 11010101

The reverse

process i.e., the

conversion of

decimal to binary is made by decomposing the given decimal number into two numbers where

one corresponds to the positional value which is lower than the original decimal number and a

remainder.

Then the remainder is decomposed into two numbers where a positional value is equal to or

lower than itself and a new remainder. The process is repeated until the remainder is 0. The

binary number is derived by recording 1 in the positions corresponding to the numbers whose

summation is equal to the decimal value.

Example 3:

Solution:

Given:

N = 426

subscript indicates the value of

the radix)

converting a decimal number to binary is based on successive division of the decimal number by

the radix number 2. The

remainders of the divisions when

written in reverse order (with the

first remainder on the right) yields

the binary equivalent to the

decimal number. The process is

described below by converting

35310 to binary.

Thus, 35310 = 1011000012

So far, we have only considered whole numbers. Fractional numbers may be converted in a

similar manner.

Example 4:

Solution:

Given:

where,

a-1 = 1

a-2 = 0

a-3 = 1

a-4 = 0

a-5 = 1

a-6 = 1

Thus,

converted to binary by multiplying it by 2 where the integral (whole number) part of each

product 0 or 1 is retained as the binary fraction.

Example 5:

Solution:

Given:

N = 0.203125

0.20312510 is 0.0011012. The

multiplication by 2 is continued until

the decimal number is exhausted or

the desired accuracy is achieved.

conversion process is stopped too

soon. For example, if we stop after the fourth step, then we are assuming 0.0011 is

approximately equal to 0.20315, whereas, it is actually equal to 0.1875 with an error of about

7.7%.

Octal numbers

Digital systems operate only on binary numbers. Since binary numbers are very long, two

shorthand notations namely octal and hexadecimal are used for representing large binary

numbers. The octal number system uses a base or radix of 8 which has digits from 0 to r - 1 or 8 -

1 or 7.

As in the decimal and binary systems, the positional value of each digit in a sequence of numbers

is definitely fixed. Each position in an octal number is a power of 8 and each position is 8 times

more significant than the previous position.

Example 6:

Solution:

Given:

N = 14.3

decimal number to an octal

number is similar to that used for converting a decimal number to binary except that the decimal

number is successively divided by 8 rather than 2.

Example 7:

Solution:

Given:

N = 278

to octal by progressively multiplying

by 8 where the integral part of each product is retained as the octal fraction. For example,

0.65110 is converted to octal as follows,

a-1 = 5

a-2 = 1

a-3 = 5

a-4 = 2

a-5 = 3

0.65110 = 0.515238

A useful relationship exists between binary and octal numbers. The number of bits required to

represent an octal digit is three. For example, octal 7 can be represented by binary as 111. Thus,

if each octal digit is written as a group of three bits, the octal number is converted into a binary

number.

Example 8:

Solution:

Given:

N = 3248

The most significant 0 is dropped because it is meaningless as 0123 10 is the same as 12310.

The conversion from binary to octal is also straightforward. The binary number is partitioned into

groups of three starting with the least significant digit. Each group of three binary digits is then

replaced by an appropriate decimal digit between 0 and 7.

Example 9:

Let us convert

1100111010012 to

octal.

Solution:

Given:

N = 1100111010012

The octal representation of the binary number is 6351 8. If the leftmost group of a partitioned

binary number does not have three digits, it is padded on the left with 0's. For example, 1101010

is divided as,

number is 1528. In case of a binary fraction, if the bits cannot be grouped into 3-bit segments,

the 0's are added on the right to complete groups of three.

The binary equivalent of a decimal number is obtained by successively dividing the number by 2

and using the remainders as the answer where the first remainder is the lowest significant bit

and so on.

A large number of divisions by 2 are required to convert from decimal to binary if the decimal

number is large. It is more convenient to convert from decimal to octal and then replace each

digit in octal in terms of three digits in binary.

Thus,

It can be verified that the decimal equivalent of 001000001011 2 is 52310.

Addition and

subtraction operations using octal numbers are similar to that used in the decimal systems. In

octal addition, a carry is generated when the sum exceeds 7 10.

For example,

In octal subtraction, a

borrow requires that

810 be added to the

minuend digit and a 1 10

be added to the left adjacent subtrahend digit.

Hexadecimal

numbers

The hexadecimal

numbering

system has a base 16 where there are 16 symbols. The decimal digits 0 to 9 are used as the first

ten digits as in the decimal system followed by the letters A, B, C, D, E and F which represents the

values 10, 11, 12, 13, 14 and 15 respectively.

The below table shows the relationship between decimal, binary, octal and hexadecimal number

systems. The conversion of a binary number to a hexadecimal number consists of partitioning

the binary numbers into groups of 4 bits and representing each group with its hexadecimal

equivalent.

Number equivalents

Example 10:

binary number

Solution:

Given:

1010011011110001 is grouped as 1010 0110 1111 0001 which is shown below in hexadecimal:

A6F1H

The conversion from hexadecimal to binary is straightforward. Each hexadecimal digit is replaced

by the corresponding 4-bit equivalent from the above table. For example, the binary equivalent

of 4AC2H is

Thus, 4AC2H =

01001010111000102

number is 16 times more significant than the previous position. Thus, the decimal equivalent for

1A2DH is given as,

used to describe the data in a computer memory. A computer memory stores a large number of

words each of which is a standard size collection of bits. An 8-bit word is known as a byte. A

hexadecimal digit may be considered as half of a byte.

Two hexadecimal digits constitute one byte where the rightmost 4 bits corresponds to half a

byte and the leftmost 4 bits corresponds to the other half of the byte. A half-byte is called as a

nibble. Hexadecimal addition and subtraction are performed for any other positional number

system.

Example 11:

Solution:

Given:

N1 = 688H

N2 = 679H

Hexadecimal

subtraction carries

digits from left to

right as in octal and

decimal.

Example 12:

Solution:

Given:

N1 = 2A5H

N2 = 11BH

1.1.1 Binary

codes

When

numbers,

alphabets or words are represented by a specific group of symbols, we can say that they are

encoded. The group of symbols used to encode them is called as codes. The digital data is

represented, stored and transmitted as a group of binary digits (bits). The group of bits also

known as binary code represents both numbers and letters of the alphabets as well as many

special characters and control functions. They are classified as numeric or alphanumeric.

Numeric code represents numbers. On the other hand, alphanumeric codes are used to

represent characters, alphabetic letters and numerals. In these codes, a numeral is treated

simply as another symbol rather than as a number or numeric value.

The below figure shows the classification of codes. The codes are broadly classified as,

1. Weighted codes

2. Non-weighted codes

3. Reflective codes

4. Sequential codes

5. Alphanumeric codes

6. Error detecting and correcting codes

Classification of codes

Weighted codes

In weighted codes, each digit position of the number represents a specific weight. For example,

in decimal code, if number is 567, then weight of 5 is 100, weight of 6 is 10 and weight of 7 is 1.

In weighted binary code, each bit has a weight of 8, 4, 2 or 1 and each decimal digit is

represented by a group of four bits as shown in the below figure.

Weighted codes

Non-weighted codes:

not assigned with any

weight to each digit

position i.e., each digit position within the number is not assigned a fixed value. Excess-3 and

gray codes are the non - weighted codes.

Reflective codes

A code is said to be reflective when the code for 9 is the complement for 0, the code for 8 is

complement for 1, 7 for 2, 6 for 3 and 5 for 4. This is described in the below figure.

Reflective codes

Like 2421, codes

5211 and excess-

3 are also reflective. The 8421 code is not reflective. Reflectivity is desirable in a code when the

nine's complement is found such as in the nine's complement subtraction.

Sequential codes

In sequential codes, each succeeding code is one binary number greater than its preceding code.

This greatly aids mathematical manipulation of data. The 8421 and excess-3 are sequential,

whereas, the 2421 and 5211 codes are non sequential.

Alphanumeric codes

The codes which consist of both numbers and alphabetic characters are called as alphanumeric

codes. Most of these codes represent symbols and various instructions are necessary for

conveying information. The most commonly used alphanumeric codes are ASCII (American

Standard Code for Information Interchange), EBCDIC (Extended Binary Coded Decimal

Interchange Code) and Hollerith code.

When the digital information in the binary form is transmitted from one circuit or system to

another circuit or system, an error may occur. This means a signal corresponding to 0 may

change to 1 or vice versa due to the presence of noise. To maintain the data integrity between

transmitter and receiver, extra bit or more than one bit are added in the data. These extra bits

allows the detection and sometimes correction of error takes place in the data. The data with

the extra bits forms the code. Codes which allow only error detection is called as error detecting

codes and codes which allow error detection and correction are called as error detecting and

correcting codes.

1.2 Error detection and error correction codes (Parity and Hamming code)

Error detecting codes

When the digital information in the binary form is transmitted from one circuit or system to

another circuit or system, an error may occur. To maintain the data integrity between transmitter

and receiver, the extra bit or more than one bit are added in the data. The data along with the

extra bits forms the code. Codes which allow only error detection is called as error detecting

codes.

This means a signal corresponding to 0 may change to 1 or vice-versa due to the presence of the

noise. To maintain the data integrity between transmitter and receiver, extra bit or more than

one bit are added in the data.

These extra bits allows the detection and correction of error in the data. The data with the extra

bits forms the code. Codes which allow only error detection is called as error detecting codes

and codes which allow error detection and correction are called as error detecting and

correcting codes.

The most common cause for errors is that the noise creeps into the bit stream during the course

of transmission from transmitter to the receiver.

If these errors are not detected and corrected, the result could be worst as the digital systems

are too much sensitive to errors and it will malfunction due to the slightest of errors in the

transmitted codes.

The various methods of error detection and correction such as addition of extra bits are called as

check bits which are also called as redundant bits as they don’t have any information in them.

The various codes used for error detection and correction code in digital system are as follows,

• Checksum

• Cyclic redundancy check

The method that we have discussed so far can detect errors but it can’t correct them. Error

correction can be handled in 2 ways as follows,

• Once when an error is discovered, the receiver might have the sender to retransmit the entire

data unit. This is termed as backward error correction.

• The receiver can use an error-correcting code which automatically corrects certain errors. This

is known as forward error correction.

It is possible to correct any number of errors automatically. The error-correcting codes are more

sophisticated than the error detecting codes and it needs more redundant bits. The number of

bits required to correct the multiple-bit or burst error is so high. For this same reason, most error

correction is limited to one, 2 or at the most three-bit errors.

The concept of error-correction is easily understood by examining the simplest case of single-bit

errors. A single-bit error is detected by the addition of a parity bit (VRC) with the data.

A single additional bit can detect error but it is not enough to correct that error too. For

collecting an error, one has to know the exact position of error i.e. exactly which bit is in error.

For example, to correct the single-bit error in an ASCII character, the error correction must

determine which one of the seven bits is in error. For this, we have to add some additional

redundant bits.

For calculating the numbers of redundant bits (r) required to correct (d) data bits, let us

determine the relationship between the two. Therefore, we have (d+r) as the total number of

bits which are to be transmitted where r indicates at least d+r+1 different values.

One value means no error and remaining d+r values indicate an error location of the error in

each of d+r locations. So, d+r+1 states must be distinguishable by r bits and r bits indicate 2r

states. Thus, 2r must be greater than d+r+1 i.e. 2r > d+r+1.

Example:

If d is 7, then the smallest value of r that satisfies the above relation is 4. Thus, the total bits

which are to be transmitted is 11 bits (d+r =7+4 =11).

Parity checking

Parity code

It is the simplest technique which is used for detecting and correcting errors. The MSB of an 8-

bits word is used as the parity bit and the remaining 7 bits are used for data or message bits.

Parity bit is added to the transmitted strings of bits during the transmission from the

transmitters to detect any error in the data when they are received at the receiver end.

Parity code

It is an extra bit

added to the string

of data. The parity

of 8-bits transmitted

can be either even parity or odd parity.

Parity checking at the receiver detects the presence of an error if the parity of receiver signal is

different from the expected parity. If it is known that the parity of the transmitted signal is

always even and if the received signal has an odd parity, then the receiver concludes that the

received signal is not correct. When an error is detected, the receiver will ignore the received

byte and request for the retransmission of the same byte to the transmitter.

Parity checking

Even parity

Even parity means the number of 1's in the given word including the parity bit should be even.

When we get an even parity after adding that extra bit, the total numbers of 1's in the string of

the data is even.

Odd parity

Odd parity is defined as the number of 1's in the given word including the parity bit which should

be odd. When we get an odd parity after adding that extra bit into the data string, the total

number of 1's in the data should be odd.

We can understand it with an example when we have an eight bit ASCII code namely 01000001.

If the added bit is 0, then the number will become 001000001. In odd parity, the total number of

1's in the number is even so we get an even parity. Repeatedly if we add 1 to the number, the

number will become 101000001.

The number of 1's is 3 which is odd so we have got an odd parity. Even parity is used which has

a convention.

The parity checks are capable of detecting the single bit error. It fails if there are two changes in

the data and it is the biggest drawback of this system. Hence, there are several other codes to

detect and correct more than one bit errors.

The parity bit can be set to 0 and 1 depending on the type of the parity required.

For even parity, this bit is set to 1 or 0, whereas, the number of the 1 bits in the entire word is

even which is shown in the below figure (a).

For odd parity, this bit is set to 1 or 0, whereas, the number of the 1 bits in the entire word is odd

which is shown

in the below

figure (b).

Parity bit

Hamming code

Let us examine the manipulation with these bits to discover which bit is in error. The method

developed by R.W.Hamming gives a practical solution. The solution or coding scheme developed

by him is called as Hamming code. The Hamming code can be applied to data units of any length

which uses the relationship between the data bits and the redundant bits.

The basic method for error detection by using Hamming code is as follows:

• To each group of m information bits, k parity bits are added to form (m+k) bit code as

represented in the below figure.

• At the receiving end, the parity bits can be recalculated. The decimal value of the k parity bits

provides the bit-position in error.

• The k parity bits are placed in positions 1, 2, 2K-1 and K parity checks which are performed on

selected digits of each codeword.

Use of Hamming

code for error

collection for a 4-bit

data

represents how the

Hamming code is

used for the

correction of 4-bit

numbers (d4d3d2d1)

with the help of

three redundant

bits (r3r2r1). For

example, consider

data 1010. First r1 (0) is determined by considering the parity of the bit positions 1, 3, 5 and 7.

Then, the parity bits r2 is calculated by considering the bit positions 2, 3, 6 and 7. Finally, the

parity bits r4 is calculated by considering the bit positions 4, 5, 6 and 7 as shown in the above

figure.

If any corruption occurs in any of the transmitted code 1010010, the bit position in the error can

be found out by calculating the r3r2r1 at the receiving end. For example, if the received code word

is 1110010, the recalculated value of the r3r2r1 is 110 that indicates that bit position in error is 6

with a decimal value of 110.

Parity generator:

1.3 Digital Logic Families - comparison of RTL, DTL, TTL, ECL and MOS families -operation,

characteristics of digital logic family

Logic families can be categorized according to the technologies they are built with. In earlier

days, we had a vast number of technologies which are listed below.

DL: Diode Logic

Since NAND and NOR gates are universal gates, they can be used to construct the entire digital

circuit instead of different gates.

• Power dissipation

• Noise immunity

• Operating temperature

• Fan-in

If the supply voltage is increased on the propagation delay of the CMOS gates, propagation time

decreases.

1.3.1 Comparison of RTL, DTL, TTL, ECL and MOS families-operation

1. Low speed

It is a first and high power

logic family dissipation

It is used before the development

which

RTL (Resistor Transistor of IC with common emitter 2. Low fan out

1. requires a

Logic) configuration. Logic 1: 1-3.6 V and with poor noise

minimum

Logic 0: 0.2V immunity and

number of

transistors operating speed

< 4MHz

1. It is the

first circuit

configuration

designed in

IC.

2. It is very

small in size

No low and

It uses diodes and transistors where and high

DTL (Diode Transistor constant output

2. input is fed through diodes followed reliability at

Logic) impedance in

by transistor at the output side. very low

both states.

price.

3. It has

greater fan

out and

improved

noise

margins.

1. It has fast

switching

time with

larger fan Large current

It uses the totem pole output of all out. spike when

TTL (Transistar-Transistor transistors. Function of diodes in 2. Areas of switching from

3.

Logic) DTL is performed by multi-emitter silicon chip is low to high with

transistor at input. reduced. 3. less noise

interface

with other

logic families.

It is the

fastest logic

1. It requires

family which

large silicon area

is used in

It is a non saturated logic/current with high power

very high

ECL (Emitter Coupled mode logic. Compliment output dissipation. 2.

4. frequency

Logic) eliminates the need of inverter. Voltage levels

applications.

Logic 1: -0.8 and Logic 0: -1.7 are inconvenient

There is no

with low noise

noise spikes

margins.

and the fan

out is large.

Power

Larger

dissipation is

It uses pMOS, nMOS or both with propagation due

lower with

MOS Logic (Metal Oxide high packaging density. It is easy to to high output

5. shorter rise

Semiconductor Logic) design and fabricate is drawn due to impedance.

and fall times

gate dielectric. Noise margin is

and fan-out is

around 1 V.

large.

The characteristics of IC digital logic families are compared by analyzing the circuit of basic gate

in each family. The most important parameters that are evaluated and compared are fan-out,

power dissipation, propagation delay and noise margin.

• Fan-out specifies the number of standard loads that the output of a gate can drive without

impairing its normal operation.

• Power dissipation is the supplied power required to operate the gate. This parameter is

expressed in milliwatts (mW) which represent the actual power dissipated in the gate.

• Propagation delay: It is the average transition delay time for a signal to propagate from input to

output when the binary signals changes its value.

• Noise margin is the maximum noise voltage added to the input signal of a digital circuit that

does not cause an undesirable change in the circuit output.

The basic circuit of the TTL logic family is the NAND gate. The Schottky TTL is a later

improvement that reduces the propagation delay but results in an increase in power dissipation.

The fan out of standard TTL is 10. The noise margin is more than 0.4V.

The basic circuit of the ECL family is the NOR gate. The special advantage of ECL gates is their low

propagation delay. The power dissipation is high and the noise margin is low where ECL offers

the highest speed of any family.

The basic circuit of CMOS is the inverter from which both NAND and NOR gates can be

constructed. The special advantage of CMOS is its extremely low power dissipation. The major

disadvantage of CMOS is its high propagation delay.

Diode Transistor Logic (DTL) is a class of digital circuits that is the direct ancestor of transistor-

transistor logic. It is called because the logic gating function (e.g., AND) is performed by a diode

network and the amplifying function is performed by a transistor.

The average power dissipation of a CMOS device whose output is continuously changing is called

as active power dissipation.

Completely specified function:

All the combinations of states and inputs and their output values are specified.

Sequential circuits in which some of the states or output values are left.

Resistor-transistor logic (RTL) is a class of digital circuits which is built using resistors as the input

network and bipolar junction transistors (BJT) as switching devices.

The primary advantage of RTL technology is that it involves a minimum number of transistors

which was an important consideration before integrated circuit technology as transistors were

the most expensive component to produce.

Limitations:

The obvious disadvantage of RTL is its high current dissipation when the transistor conducts to

overdrive the output biasing resistor. This requires that more current is supplied and heat is

removed from the RTL circuits. In contrast, TTL circuits minimize both of these requirements.

DTL takes diode logic gates and adds a transistor to the output to provide logic inversion and to

restore the signal to its full logic levels.

Diode-transistor logic:

Diode-Transistor Logic (DTL) is a class of digital circuits which is built from bipolar junction

transistors (BJT), diodes and resistors. It is the direct ancestor of transistor-transistor logic. It is

called as diode-transistor logic because the logic gating function (e.g., AND) is performed by a

diode network and the amplifying function is performed by a transistor.

Advantages of DTL:

One advantage of digital circuits when compared to analog circuits is that signals represented

digitally can be transmitted without degradation due to noise. For example, a continuous audio

signal transmitted as a sequence of 1’s and 0’s can be reconstructed without error where the

noise picked up in transmission is not enough to prevent identification of the 1’s and 0’s. An

hour of music can be stored on a compact disc as about 6 billion binary digits.

In a digital system, a more precise representation of a signal can be obtained by using more

binary digits to represent it. This requires more digital circuits to process the signals where each

digit is handled by the same kind of hardware. In an analog system, additional resolution

requires fundamental improvements in the linearity and noise characteristics of each step of the

signal chain.

Disadvantages:

In some cases, digital circuits uses more energy than analog circuits to accomplish the same

tasks to produce more heat. In portable or battery-powered systems, this can limit the use of the

digital systems.

For example, battery-powered cellular telephones uses a low-power analog front-end to amplify

and tune in the radio signals from the base station. However, a base station has grid power and it

can use power-hungry. Such base stations can be easily reprogrammed to process the signals

used in new cellular standards.

Comparison of logic

family

collector output

configuration

The multiple emitters in transistor θ 1 are connected to the inputs, a resistor is connected to +Vcc

which must be inserted externally to the IC package for the output to pull up to a high voltage

level when θ3 is off where the output acts as an open circuit.

The two voltage levels of the TTL gate are 0.2V for the low level and it varies from 2.4V to 5V for

high level. If any input is low, the corresponding base emitter junction in θ1 is forward biased.

The voltage at the base of θ1 is equal to the input voltage 0.2V plus a VBE drop of 0.7V or 0.9V.

In order to turn ON θ 3, at least 1.8V is required. So the output transistor θ 3 is OFF and output Y is

at +Vcc. If all the inputs are high, both θ2 and θ3 is conducted and saturated.

The base voltage of θ1 is equal to the voltage across its base collector PN junction plus V BE drops

in θ2 and θ3. The base emitter junctions of θ1 are reverse biased where θ1 is in OFF state.

configuration

TTL inverter with tristate

output

three output states as

follows:

1) A low level state when the lower transistor in the pole is ON and the upper transistor is OFF.

2) A high level state when the lower transistor is OFF and the upper transistor is ON.

3) A third state (high impedance) when both transistors in the pole are OFF.

The circuit diagram of three state inverter is shown in the below figure.

Transistors Q1 – Q5 forms a totem pole and transistors Q 6 – Q8 forms an open collector. The two

circuits are connected together through a diode D 1.

When control input at C is in the low level state, Q 8 is in OFF state. So, D1 does not conduct and

emitter in Q1 is connected to Q8 which has no conduction path. Under this condition, transistor

Q8 has no effect on the gate and the output Y depends on the data input at A.

When the control input is high, Q 8 turns ON. The voltage is at the base if Q 5 is one diode drop

plus VCE (Q8). This voltage turns OFF Q5 and Q4.

At the same time, the low input to one of the emitters of Q 1 forces transistors Q2 and Q3 to turn

OFF. Thus, both Q3 and Q4 are turned OFF and the output of the circuit behaves like an open

circuit with a high output impedance.

tristate output

ECL:

Emitter Coupled

Logic (ECL) is a non-

saturated digital logic

family. The basic

component of the

ECL gate is a current

switch or difference

amplifier with an out-of-phase output for which ECL is called as Current Mode Logic (CML).

It consists of a difference amplifier input circuit which is a bias circuit and emitter - follower

outputs. The outputs provide both OR and NOR functions.

The Vcc terminal is connected to ground and -5.2 V from the power supply to V EE for best

operation. The two voltage levels are about -0.8 V for the HIGH state and about -1.8 V for the

LOW state.

Circuit operation:

If all inputs are at the Low level, all input transistors turn OFF and Q 5 conducts. The base of each

input is at a Low level of -18 V. The current in R 1 is negligible and the NOR output is one V BE drop

below the ground at -0.8 V or at the HIGH level.

If any input is HIGH, the corresponding transistor is turned ON and Q 5 is turned OFF. Since, VBB =

-1.3 V, the base voltage of Q5 is only 0.3 V more positive than its emitter.

The OR output of the gate is one V BE drop below the ground or -0.8 V which is in the High state.

The NOR output is one VBE drop below this level or at -1.8V which is the LOW state.

ECL

HIGH-level input current, IIH:

This is the current flowing into (taken as positive) or out of (taken as negative) an input when a

HIGH-level input voltage is equal to the minimum HIGH-level output voltage. In the case of

bipolar logic families such as TTL, the circuit design is in such a way where the current flows into

the input pin and it is therefore specified as positive. In the case of CMOS logic families, it could

be either positive or negative and only an absolute value is specified in this case.

The LOW-level input current is the maximum current flowing into (taken as positive) or out of

(taken as negative) the input of a logic function when the voltage applied at the input equals to

the maximum LOW-level output voltage specified for the family. In the case of bipolar logic

families such as TTL, the circuit design is such that, this current flows out of the input pin and it is

therefore specified as negative. In the case of CMOS logic families, it could be either positive or

negative. In this case, only an absolute value is specified.

This is the maximum current flowing out of an output when the output is in the logic HIGH state.

It is normally shown as a negative number. It informs us about the current sourcing capability of

the output. The magnitude of I0H determines the number of inputs the logic function can drive

when its output is in the logic HIGH state. For example, for the standard TTL family, the minimum

guaranteed IOH is - 400μA which can drive 10 standard TTL inputs which require 40μA in the HIGH

state.

This is the maximum current flowing into the output pin of a logic function when the input

conditions are such that the output is in the logic LOW state. It shows the current sinking

capability of the output. The magnitude of IOL determines the number of inputs the logic function

can drive when its output is in the logic LOW state. For example, for the standard TTL family, the

minimum guaranteed IOL is 16 mA which can drive 10 standard TTL inputs with each requiring

1.6mA in the LOW state.

This is the minimum voltage level that needs to be applied at the input to be recognized as a

legal HIGH level for the specified family. For the standard TTL family, a 2 V input voltage is a legal

HIGH logic state.

This is the maximum voltage level applied at the input that is recognized as a legal LOW level for

the specified family. For the standard TTL family, an input voltage of 0.8 V is a legal LOW logic

state.

This is the minimum voltage on the output pin of a logic function when the input conditions

establishes logic HIGH at the output of the specified family. In the case of the standard TTL family

of devices, the HIGH level output voltage is as low as 2.4V and it is treated as a legal HIGH logic

state. For a given logic family, the VOH specification is always greater than the V IH specification to

ensure the output-to-input compatibility when the output of one device feeds the input of

another.

LOW-level output voltage, VOL:

This is the maximum voltage on the output pin of a logic function when the input conditions

establishes logic LOW at the output for the specified family. In the case of the standard TTL

family of devices, the LOW-level output voltage is as high as 0.4V and it is treated as a legal LOW

logic state. It may be mentioned here that, for a given logic family, the V OL specification is always

smaller than the VIL specification which ensures output-to-input compatibility when the output

of one device feeds the input of another.

High

level

input

and

output

current

and

voltage

requirements

Low

level

input

and

output

current

and

voltage

requirements

Supply current, Icc:

The supply current occurs when the output is HIGH, LOW and in the high-impedance state, it is

designated as ICCH, ICCL and ICCZ.

Fan out:

It specifies the number of standard loads that the output of the gate can drive without affecting

its normal operation. A standard load is defined as the amount of current needed by an input of

another gate in the same family as shown in the below figure. Sometimes, the term loading is

used instead of fan out. This term is derived from the fact that the output of the gate can supply

a limited amount of current above which it ceases to operate properly and it is said to be

overloaded. The output of the gate is connected to the inputs of similar gates.

decided by number of loads

connected to the output of

the gate of same logic family

Each input consumes a

certain amount of power

from gate input so that

each additional

connection is added to

load the gate. These

loading rules are listed for

family of standard digital

circuits. The rules specify the maximum amount of loading allowed for each output in the circuit.

Exceeding the specified maximum load causes a malfunction because the circuit cannot supply

the power demanded from it. Thus, fan out is the maximum number of inputs that can be

connected to the output of the gate and it is expressed by a number. The fanout capabilities of a

gate must be considered while simplifying Boolean functions. Non inverting amplifiers or buffers

provides additional driving capabilities for heavy loads.

Fan in

inputs of a logic gate.

It is decided by the

input current sinking

capability of a logic

gate as shown in the

below figure.

Fan in of logic gate

Power dissipation:

This is the power supply required to operate the gate. It is expressed in milli-watt (mW) and it

represents the actual power dissipated in the gate. It is the number that represents power

delivered to gate from the power supply. The total power dissipated in the digital system is the

sum of power dissipated in each digital IC.

This is the time that elapses between 10% and 90 % of the final signal level when the signal

makes a transition from logic LOW to logic HIGH.

This is the time that elapses between 90 and 10 % of the signal level when the signal makes a

transition from logic LOW to logic HIGH

The propagation delay is the time delay between the occurrence of change in the logical level at

the input before it is reflected at the output. It is the time delay between the specified voltage

points on the input and output waveforms. Propagation delays are separately defined for LOW-

to-HIGH and HIGH-to-LOW transitions at the output. Enable and disable time delay occurs

during transition between the high-impedance state and defined logic LOW or HIGH states.

Parameters of propagation delay

a. Propagation delay, tpLH:

This is the time delay between the specified voltage points on the input and output waveforms

with the output changing from LOW to HIGH.

This is the time delay between the specified voltage points on the input and output waveforms

with the output changing from HIGH to LOW.

It is the average transition delay time for a signal to propagate from input to output when the

binary signals changes its value. The signal through gate takes a certain amount of time to

propagate from the inputs to the output. The interval of time is defined as the propagation delay

of the gate. Propagation delay is expressed in nanoseconds(ns)(1ns = 10-9 s).

The signals travelling from input to output of the system pass through a number of gates. The

propagation delay of the system is the sum of the propagation delays of all these gates. When

the speed of operation is important, each gate must have a small propagation delay and the

digital circuit must have minimum number of gates between input and output.

For a tristate device, this time delay is between the specified voltage points on the input and

output waveforms with the tristate output changes from the logic HIGH level to the high-

impedance state.

For a tristate device, this time delay is between the specified voltage points on the input and

output waveforms with the tristate output changes from the logic LOW level to the high-

impedance state.

For a tristate device, the time delay between the specified voltage points on the input and

output waveforms with the tristate output changes from the high-impedance state to the logic

HIGH level is known as enable time from the HIGH state.

Power dissipation:

The power dissipation for a logic family is specified in terms of power consumption per gate and

it is the product of supply voltage V cc and supply current Icc. The supply current is taken as the

average of the HIGH-level supply current I CCH and the LOW-level supply current I CCL.

Speed-power product:

The speed of a logic circuit is increased and the propagation delay is reduced at the expense of

power dissipation. When a bipolar transistor switches between cut-off and saturation, it

dissipates the least power but it has a large switching time delay. When the transistor is

operated in the active region, power dissipation goes up while the switching time decreases.

It is always desirable to have low values for both propagation delay and power dissipation

parameters. A figure-of-merit is used to evaluate different logic families where the speed-power

product is expressed in picojoules which is the product of the propagation delay (measured in

nanoseconds) and the power dissipation per gate (measured in milliwatts).

Noise margin:

This is the maximum noise voltage added to the input signal of digital circuit that does not cause

an undesirable change in the output of the circuit. There are two types of noise to be considered

as follows,

b. AC noise: This is caused by random pulse that may be created by other switching signals.

Noise margin

This is a quantitative measure of noise immunity offered by the logic family. When the output of

a logic device feeds the input of another device of the same family, a legal HIGH logic state at the

output of the feeding device is treated as a legal HIGH logic state by the input of the device being

fed. Similarly, a legal LOW logic state of the feeding device is treated as a legal LOW logic state by

the device being fed. The legal HIGH and LOW voltage levels for a given logic family are different

for outputs and inputs.

The above figure shows the generalized case of legal HIGH and LOW voltage levels for output. As

we can see from the two diagrams that there is a disallowed range of output voltage levels from

VOL(max) to VOH(min) and an indeterminate range of input voltage levels from VIL(max) to

VIH(min). Since VIL(max) is greater than VOL(max), the LOW output state has a positive voltage

spike which is equal to (VIL(max) - VOL(max)) and which is a legal LOW input. Similarly, VOH(min)

is greater than VIH (min) and the HIGH output state tolerates a negative voltage spike which is

equal to (VOH(min) - VIH (min)) which is a legal HIGH input. Here, (VIL(max) - VOL(max)) and

(VOH(min) - VIH (min)) are known as the LOW-level and HIGH-level noise margin.

UNIT II COMBINATIONAL CIRCUITS

Combinational logic - representation of logic functions-SOP and POS forms, K-map

representations - minimization using K maps - simplification and implementation of

combinational logic - multiplexers and demultiplexers - code converters, adders, subtractors,

Encoders and Decoders.

2.1 Combinational logic - representation of logic functions-SOP and POS forms

With combinational logic, the circuit produces the same output regardless of the order the

inputs are changed. There are circuits which depend on the change in input and these circuits

are known as sequential logic.

The practical circuits will have a mix of combinational and sequential logic where sequential logic

is in a order and combinational logic performs functions like arithmetic, logic or conversion.

A combinational circuit is the one in which the output at any time depends only on the present

combination of inputs at that point of time with total disregard to the past state of the inputs.

Logic gate is the most basic building block of the combinational logic.

The logical function performed by a combinational circuit is fully defined by a set of Boolean

expressions. The other category of logic circuits is called as sequential logic circuits which

comprise of both memory elements such as flip-flops and logic gates.

Due to the presence of memory elements, the output in a sequential circuit depends not only on

the present input but also on the past state of inputs.

Generalized

combinational circuit

The above figure shows

the schematic

representation of a

generalized combinational circuit having n input variables and m output variables or simply

outputs. Since the number of input variables is n, there are 2n possible combinations of bits at

the input.

Each output can be expressed in terms of the input variable by a Boolean expression with the

result where the generalized system of the above figure can be expressed by m Boolean

expressions.

Problems

1. Let us assume that the input frequency of a 7497 binary rate multiplier is 64 KHz. Let us

determine its output if the multiplier word is 1011.

Solution:

Given:

To find:

Formula to be used:

where,

M = 1 x 23 + 0 x 22 + 1 x 21 + 1 x 20 = 11

functions

Three representations of logic functions are as follows,

A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs

and one output.

At any given moment, every terminal is in any one of the two binary conditions is low (0) or high

(1) which is represented by different voltage levels.

The logic state of a terminal changes when the circuit processes the data.

In most logic gates, the low state is approximately zero volts while the high state is

approximately five volts positive. There are seven basic logic gates namely AND, OR, NOT, XOR,

XNOR, NAND and NOR.

AND

The AND gate is named because if 0 is called "false", then 1 is called "true" where the gate acts

in the same way as the logical "and" operator.

The output is "true" when both inputs are "true". Otherwise, the output is "false".

Truth table:

0 0 0

0 1 0

1 0 0

1 1 1

OR

The OR gate gets its name from the fact that it behaves like the logical inclusive "or".

The output is "true" if either or both of the inputs are "true" and if both the inputs are "false",

then the output is "false".

Symbol of OR gate

Truth table:

0 0 0

0 1 1

1 0 1

1 1 1

NOT

A logical inverter also called as a NOT gate differentiates it from other types of electronic inverter

devices which have only one input. It reverses the logic state.

Truth table:

Input Output

1 0

0 1

NAND

The NAND gate operates as an AND gate followed by a NOT gate. It acts in the similar manner of

the logical operation "and" followed by a negation. The output is "false" if both inputs are "true".

Otherwise, the output is "true".

Truth table:

0 0 1

0 1 1

1 0 1

1 1 0

NOR

Its output is "true" if both the inputs are "false". Otherwise, the output is "false".

Truth table:

0 0 1

0 1 0

1 0 0

1 1 0

Universal gates:

The NAND and NOR gates are called as the universal gates. These gates are used to perform any

type of logic operations.

Implementation of the Boolean expression for EXOR gate using NAND and NOR gates:

EX-OR gate expression is given as .

Step 2: Bubbles

on the output

of AND gate

and input of OR

gate are added.

Step 3: Then it

is replaced by a

NAND symbol.

NOR

Step 1: In AOI

logic, bubbles are added at the output of OR gate and input of the AND gate.

Step 2:

Inverters are

added in the

line that

received bubbles and removes double inversions.

Step 3: Then it is replaced by a NOR Symbol.

NOR gate

using TTL

logic:

TTL logic

When A = 0

and B = 0, Q1

and Q2 is in OFF

condition.

∴ Q3 and Q4 will also be in OFF condition. Therefore, the output level at Vcc has a high voltage.

ON condition and the output has a low voltage.

Truth table:

A B Output

0 0 1

0 1 0

1 0 0

1 1 0

Exclusive-OR

The XOR (exclusive-OR) gate acts in the same way as the logical "either/or."

The output is "true" if either but not both the inputs are "true". The output is "false" when both

the inputs are "true" or if both the inputs are "false".

Another way of analyzing this circuit is that the output is 1 when the inputs are different but 0 if

the inputs are the same.

Symbol of Exclusive-OR

Truth table:

0 0 0

0 1 1

1 0 1

1 1 0

Exclusive-NOR

The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an inverter. Its output is

"true" if the inputs are the same and "false" if the inputs are different.

Symbol of XNOR

Truth table:

0 0 1

0 1 0

1 0 0

1 1 1

A Sum-of-Products Boolean expression is a set of Boolean terms that are added together where

each term is a multiplicative combination of Boolean variables.

The product terms include all the input variables which are called as minterms.

In a sum-of-products expression, a product of all the input variables (or their inverses) for each

row of the truth table is formed where the result is logic 1. The output is the logical sum of these

minterms.

The sum-of-products expressions are easy to generate by determining which rows of the table

have an output of 1 by writing one product term for each row and then all the product terms are

added. This creates a Boolean expression which is represented in the below truth table. The

sum-of-products expressions are implemented as a set of AND gates (products) by feeding into a

single OR gate (sum).

Truth table:

A B C W

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

Product of

Sums (POS):

An alternative to a sum-of-products expression results in all "high" (1) output conditions in the

truth table to generate the product-of-sums or POS expression which accounts for all "low" (0)

output conditions.

POS Boolean expressions are generated from the truth tables by determining the rows of the

table which have an output of 0 by writing the one sum term for each row and then finally

multiplying all the sum terms. This creates a Boolean expression which is represented in the

below truth table.

These “sum” terms include all the input variables (or their inverses) called as maxterms. In the

POS implementation, the output variable is the logical product of maxterms. Product-of-sums

expressions implement a set of OR gates (sums) by feeding into a single AND gate (product).

Truth table:

A B C Z

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 1

Problems

x'y'z' +x'y'z' + x'yz + xy'z + xyz

Solution:

Given:

= x'y' + yz + xy'z

= y'(x' + z)+yz

= y'x' + y'z+yz

= y'x' + z(y'+y)

= y'x' + z

Solution:

Given:

p'q'r + p'qr' + p'qr + pqr' + pq'r'

Solution:

Given:

= qr' + p ⨁ r

expressed as a sum of its minterms is equivalent to a function expressed as a product of its

maximum terms.

Solution:

Given:

SOP:

5. Let us show

that a function

expressed as a sum of its minterms is equivalent to a function expressed as a product of its

maximum terms.

Solution:

Given:

POS:

6. Let us express

the function in

canonical SOP

form.

Solution:

Given:

Y =

m7 +

m6 + m 5 + m 3 + m 5 + m 1

Y = Σ(1, 4, 5, 6, 7)

canonical POS form.

Solution:

Given:

Product of Sum (POS)

Y = M 2 M3

M0 = M 0

M2 M 3

Y = π(0, 2, 3)

8. Let us minimize and implement the following multiple output functions in SOP form.

Solution:

Given:

The K

maps

are

filled

by

ones

and don't cares using the above expression. After reduction, let us find that CD occurs both in f1

and f2 which can be shared.

Implementation of logic

circuit

given expression Y =

AC + AB + BC in

canonical SOP form.

Solution:

Given:

Y = AC + AB + BC

Solution:

Given:

Y = AC + AB + BC

2.2 K-map representations - minimization using K maps - simplification and implementation of

combinational logic

A Karnaugh map (or) K-map is a pictorial form of truth table in which the map diagram is made

up of cells with each cell representing one minterm or maxterm of the function. It provides a

simple straight forward procedure for minimizing Boolean function.

Five

variable

K-map

Six

variable

K-map

i) It is restricted in its capability because they are useful for simplifying only the Boolean

expression represented in standard form.

ii) It is limited to six variable map (i.e) more than six variables involves reduced expressions.

• K-maps converts the truth table of a Boolean equation into minimized SOP form.

• K-maps has easy and simple basic rules for the simplification.

• The K-map method is faster and more efficient than other simplification techniques of Boolean

algebra.

• All rows in the K-map are represented by using a square shaped cells in which each square

represent a minterm.

• It is easy to convert a truth table to k-map and k-map to sum of products to form an equation.

There are 2 forms in converting a Boolean equation into K-map. They are as follows,

Un-optimized form

Optimized form

Unoptimized form: It converts the number of 1’s into an equal number of product terms

(minterms) in an SOP equation.

In some logic circuits, certain input conditions will never occur, therefore, the corresponding

output will never appear. In such cases, the output level is not defined which may be either high

or low. These output levels are indicated by either ‘X’ or ‘d’ in the truth table and are known as

don’t care conditions or incompletely specified functions.

For SOP, we enter 1’s corresponding to the combinations of input variables which produces high

output and we enter 0's in the remaining cells of the K-map.

In such situation, we have freedom to assume '0' or '1' as output for each of three combination s

in K-map. It is represented as X mark in the corresponding cell.

Problems

Solution:

Given:

following function using K -

map and also implement

the function using logic

gates f(A, B, C) =π(0, 4, 6).

Solution:

Given:

f(A, B, C) =π(0, 4, 6)

3. Let us

reduce

the

following

Solution:

Given:

F = m2 + m3 + m4 + m6 + m7 + m9 + m11 + m13

expression using K - map, f =

x'y'z + w'xyz' + wxz + w'xyz.

Solution:

Given:

expression for the following

logic equation f(A, B, C, D) =

Σm(0, 8, 11, 12, 15) + d(1, 2,

4, 7, 10, 14) where d

represents a don’t care

condition. Let us also represent the simplified expression using logic gates.

Solution:

Given:

f(A, B, C, D) = Σm(0, 8, 11, 12, 15) + d(1, 2, 4, 7, 10, 14)

Boolean function F(w, x, y,

z) = Σ (1, 3, 7, 11, 15) using

K - map which has the

don't care conditions as

d(w, x, y, z) = Σ(0, 2, 5).

Solution:

Given:

d(w, x, y, z) = Σ(0, 2, 5)

Simplification of combinational logic circuits using Boolean algebra:

Complex combinational logic circuits must be reduced without any change in the function of the

circuit. Reduction of a logic circuit means that the same logic function has fewer gates and

inputs.

The first step in reducing a logic circuit is to write the Boolean equation for the logic function.

The next step is to apply as many laws and rules to reduce the number of terms and variables in

the expression.

To apply the rules of Boolean Algebra, we should first remove any parentheses or brackets. After

the removal of the parentheses, common terms or factors are removed by leaving the terms that

can be reduced by the rules of Boolean algebra.

The final step is to draw the logic diagram for the reduced Boolean expression.

Multiplexer is a combinational circuit which has 2N inputs and 1 output with n-selection lines.

Block diagram of

multiplexer

Applications of

multiplexer

implementation of

combinational circuits.

generators.

Data routing:

Multiplexers are used to route the data from one of several sources to one destination.

Control sequences:

F(x, y, z) = Σ(1, 2, 6, 7)

4:1 MUX

2x2 multiplexer:

Multiplication of

binary number is

performed in the

same way as in

decimal numbers. The

multiplicand is multiplied by each bit of the multiplier which starts from the least significant bit.

Each such multiplication forms a partial product. Successive partial products are shifted one

position to the left. The final product is obtained from the sum of the partial products.

The multiplication of 2 bit number is considered. The multiplicand bits are B1 and B0, the

multiplier bits are A1 and A0 and the product is C3 C2 C1 C0. The first partial product is formed by

multiplying A0 by B1B0. The multiplication of two bits such as A0 and B0 produces 1 if both bits are

1, otherwise, it produces 0. This is identical to AND operation where the partial product is

implemented with AND gates as follows,

2 x 2 multiplexer

The second partial product

is formed by multiplying A1

by B1B0 and it is shifted one

position to left. The two

partial products are added with two half adder circuits. The LSB of the product does not have

to go through an adder since it is formed by the output of the first AND gate.

Demultiplexers

In addition to the data input, there must be other inputs to control the transmission of the data

to the appropriate data output line at any given time. This demultiplexer circuit having eight

output lines is shown in the below figure (a). For the same number of control inputs, it has same

number of AND gates. But now each AND gate output is an output of the circuit. Each gate has

its own separate data input where single data line forms one of the inputs to each AND gate

where the other AND inputs are control inputs.

When the word formed by the control inputs C 2C1C0 is the binary equivalent of decimal k, then

the data input x is routed to output D k. For a demultiplexer which has n control inputs, each AND

gate output corresponds to a minterm of n variables. For a given combination of control inputs,

only one minterm can take the value 1 where the data input is routed to the AND gate

corresponding to this minterm. For example, if the logical expression for the output D3 is

xC2'C1C0, then C2C1C0 =

011 where D3 = x and

all other Di are equal

to 0.

Demux circuit

table for the eight-

output demultiplexer

is given in the below

truth table:

Truth table

C2 C1 C0 D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 x 0 0 0 0 0 0 0

0 0 1 0 x 0 0 0 0 0 0

0 1 0 0 0 x 0 0 0 0 0

0 1 1 0 0 0 x 0 0 0 0

1 0 0 0 0 0 0 x 0 0 0

1 0 1 0 0 0 0 0 x 0 0

1 1 0 0 0 0 0 0 0 x 0

1 1 1 0 0 0 0 0 0 0 x

decoder using two 4-

line-to 16-line decoders

decoders are the largest

available circuits in IC’s,

larger inputs are

needed for the

expansion. This is made

possible by using

enable input terminal. The above figure(a) shows a 5-line-to 32-line decoder and the below

figure(b) shows a 8-line-to 256-line decoder using 4-line-to 16-line decoders. Similarly, an m-line-

to-n-line decoder can be implemented. However, if only a few codes of a large number need be

recognised, the alternative approach such as the one shown in the below figure (c) can be used.

This is connected to detect the digital number 00011111.

(b) 8-line-to

256-line

decoder

using two 4-

line-to 16-

line decoders

The most-

significant 4-

bits are

applied at

ABCD inputs

and the

least-

significant

bits are

applied at

EFGH inputs.

The output goes low when the most-significant bits are 0001 and the least-significant bits are

1111. The circuit can be expanded to detect other 8-bit codes.

(c) An

alternative

approach to

decode

combinations

Higher

order

multiplexing

with OR gate

The 16-to-1

multiplexers

are the

largest

available IC’s. Hence, to meet the larger input needs, there must be a provision for expansion.

This can be achieved with the help of enable or strobe inputs where multiplexers stacks or

trees are designed. Two commonly used methods for this purpose are shown in the above

figure(a) and in the below figure(b).

The circuit of the above figure (a) uses two 16:1 multiplexers (M1and M2) for the realization of a

32:1 multiplexer. The lower order of 16 data input lines (I0-I15) is applied at the data input

terminals of the multiplexer M1 and the higher order 16 data input lines (I15-I31) is applied at the

data input terminals of the multiplexer M2.

with 2:1 mux

For a 32:1

multiplexer,

the number

of select

input lines is

5. The 5-bit

select

inputs are

ABCDE. The

most-

significant

select input

bit A is applied at G 1 and is applied at G 2. B, C, D and E are connected to S 3, S2, S1 and S0 inputs of

both the multiplexers. The output F of the multiplexer is obtained by using an OR gate where F =

Y1+ Y2.

When A = 0, the multiplexer M1 is enabled and M2 is disabled which allows one of the lower

order 16 bits to Y1 depending on the value of BCDE where Y2= 0. Therefore, F = Y1. Similarly, when

A = 1, M2 is enabled and M1 is disabled and F = Y2. The above figure(b) uses a 2:1 multiplexer

instead of an OR gate. Where A = 0, F = Y1 and when A = 1, F = Y2. Thus, both the circuits perform

similar operation. These two general techniques can be used to expand an n input multiplexer

without any difficulty.

Problems

Solution:

Given:

f(A, B, C) = Σm(0, 3, 5)

Formula to be used:

Variables n = 3 (A, B, C)

Implementation table:

I0 I1 I2 I3

Ā 1 2

A 4 6 7

Ā A 0 Ā

I0 = Ā, I1 = A, I2 = 0, I3 = Ā

Implementation of multiplexer:

2. Let us implement

F(x, y, z) = Σ(1, 2, 6,

7) using 4 × 1 MUX.

Solution:

Given:

F(x, y, z) = Σ(1, 2, 6, 7)

3. Let us

implement the

following boolean

function using 8:1

multiplexer

Solution:

Given:

expression is not in

standard SOP form. The conversion to SOP is given as,

SI. No. Minterms A B C D Y

0 0 0 0 0 0

1 0 0 0 1 1

2 0 0 1 0 0

3 0 0 1 1 1

4 0 1 0 0 1

5 0 1 0 1 1

6 0 1 1 0 1

7 0 1 1 1 0

8 1 0 0 0 0

9 1 0 0 1 0

10 1 0 1 0 0

11 1 0 1 1 1

12 1 1 0 0 0

13 - 1 1 0 1 0

14 1 1 1 0 0

15 ABCD 1 1 1 1 1

Implementation table

D0 D1 D2 D3 D4 D5 D6 D7

0 1 2 3 4 5 6 7

A 8 9 10 11 12 13 14 15

Y 0 0 1 A

Implementation of MUX

4. Let us

implement the

following function

with a multiplexer.

F(A, B, C) = Σ(1, 2,

4, 5)

Solution:

Given:

F(A, B, C) = Σ(1, 2,

4, 5)

Two of the

variables B and C are applied to the selection lines S1 and S0 respectively.

The truth table of multiplexer is given as follows,

Minterm A B C F

0 0 0 0 0

1 0 0 1 1

2 0 1 0 1

3 0 1 1 0

4 1 0 0 1

5 1 0 1 1

6 1 1 0 0

7 1 1 1 0

Implementation table

The multiplexer

implementation is given

as,

2.4 Code converters

coded in one form or

another to represent or to

use it as required. For

instance, a number nine is coded in decimal using symbol (9) d. Same is coded in natural-binary

as(1001)b. When digital computers deal with binary numbers, natural-binary representation of

numbers are inefficient and some other (binary) code must be used to process the numbers.

Gray code is a non-weighted code. It has a very special feature where only one bit will change. A

binary number can be converted to gray code by using the following steps:

• Add this bit to the next position by recording the sum and neglecting any carry.

• Gray code is used in applications where the normal sequence of binary number produces an

error or ambiguity during transition from one number to the next.

• It is used for entering the binary data and displaying certain information.

• It is very important for the efficient use of microprocessors and other digital circuits.

BCD to Excess - 3 code encoder:

Excess - 3 code is a modified form of a BCD number. It can be derived from the natural BCD code

by adding 3 to each coded number.

Truth table:

B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 0 1 1 0 0

Simplification of K-Map:

BCD to

Excess 3

code

converter

Problems

1. Let us

solve the

maximum

number of

outputs for

a decoder

with a 6 bit

data word.

Solution:

For a 6 bit data word, the maximum number of output for a decoder is 2 6 = 32 outputs.

Solution:

Given:

Binary 1011:

Half adder

addition of two bits is a half adder. A half-adder is an arithmetic circuit block which can be used

to add two bits. Such a circuit has two inputs that represent the two bits to be added and two

outputs with one which produces the SUM output and the other produces the CARRY. The below

figure shows the truth table of a half adder that shows all possible input combinations and the

corresponding outputs.

The Boolean expressions for the SUM and CARRY outputs are shown in the below equations:

Truth table

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Half adder

Full adder

The circuit that performs the addition of three bits is called as a full adder.

Implementation

of full adder

using half adders

Applications of

full adders

• Full adder

reduces the

complexity of the circuit.

• This is used to construct a ripple carry counter to add n-bit numbers. Thus, it is used in the

arithmetic and logic unit.

• This can be used in processor chip such as Snapdragon, Intel Pentium or Exynos for CPU part

which consists of an ALU. Therefore, this block performs addition, subtraction, multiplication

etc.,

• A full adder adds the binary numbers and accounts for values carried in as well as out.

• A one-bit full adder adds three one-bit numbers which are written as A, B and Cin where A and

B are the operands and Cin is a bit carried in from the previous less significant stage.

Truth table:

Input Output

A B Cin S C

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

2.5.1 Subtractors

Half subtractor

A half-subtractor is a combinational circuit which is used to subtract one binary digit from

another to produce a DIFFERENCE output and a BORROW output.

The BORROW output specifies whether a = 1 has been borrowed to perform the subtraction.

The truth table of a half-subtractor is shown below. The Boolean expressions for the two outputs

are given by the below equations.

DIFFERENCE bit:

D = X XOR Y = X ⊕ Y

BORROW bit:

B = not-X AND Y =

Half subtractor

Full subtractor

A full subtractor

performs the

subtraction function on two bits such as a minuend and a subtrahend and also whether a = 1 is

borrowed by the previous adjacent lower minuend bit or not is taken into consideration.

There are three bits to be handled at the input of a full subtractor where the two bits are

subtracted and a borrow bit is designated as Bin.

There are two outputs namely the DIFFERENCE output D and a BORROW output Bo.

The BORROW output bit tells whether the minuend bit needs to borrow a =1‘ from the next

possible higher minuend bit.

The truth table of a full subtractor is given below. The Boolean expressions are given by the

equations for two output variables as follows,

Truth table:

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

An encoder is the digital circuit that performs the inverse operation of a decoder. An encoder has

2n input lines and n output lines. In an encoder, the output lines generate the binary code

corresponding to the input value. An encoder is a combinational circuit that performs the inverse

operation of a decoder. When the device output code has fewer bits than the input code, the

device is called as an encoder e.g., 2n-to-n priority encoders. It is a 2n-to-n binary encoder where

it has only one of 2n inputs = 1 and the output is the n-bit binary number corresponds to the

active input.

The below figure shows the general structure of the encoder circuit where the decoded

information is presented as 2n inputs to produce n possible outputs.

The decimal to BCD

encoder has ten input

lines and four output

lines. The decoded

decimal data acts as an input for encoder and encoded BCD output is available on the four

output lines.

The above figure shows the logic symbol for decimal to BCD encoder for IC 74xx147. It has nine

input lines and four output lines. Both input and output lines are asserted as active low. It is

important to note that there is no input line for decimal zero. When this condition occurs, all

output lines are 1. The function table for the 74xx147 is shown below.

Truth table for decimal to BCD encoder:

value

1 2 3 4 5 6 7 8 9 D C B A

0 1 1 1 1 1 1 1 1 1 1 1 1

1 0 1 1 1 1 1 1 1 1 1 1 1 0

2 x 0 1 1 1 1 1 1 1 1 1 0 1

3 x x 0 1 1 1 1 1 1 1 1 0 0

4 x x x 0 1 1 1 1 1 1 0 1 1

5 x x x x 0 1 1 1 1 1 0 1 0

6 x x x x x 0 1 1 1 1 0 0 1

7 x x x x x x 0 1 1 1 0 0 0

8 x x x x x x x 0 1 0 1 1 1

9 x x x x x x x x 0 0 1 1 0

x denotes don’t care condition. Let us draw the interfacing diagram of ten key keypad interface

to a digital system using decimal to BCD encoder.

Ten key keypad interface using decimal to BCD encoder

Decoders

A decoder is a combinational circuit that converts binary information from n input lines to a

maximum of 2n output lines. A decoder is a multiple input multiple output logic circuit that

converts coded inputs into coded outputs where the input and output codes are different.

n-to-2n-line decoder:

Each AND gate has only n (in this case three) inputs and there are 2 n (in this case eight) outputs.

Since there is no data input line to control, control inputs serve that function which are the data

inputs to be decoded. The below circuit is an example of an n-to-2n-line decoder. Each output

represents the minterm. Output k is 1 whenever the combination of the input variable values is

the binary equivalent of decimal k. The data input line from the demultiplexer in the below

figure is not removed but retained and viewed as an enable input where the decoder operates

only when the enable x is 1.

An n-to-2n-line decoder with an enabled input is used as a demultiplexer where the enable

becomes the serial data input and the data inputs of the decoder become the control inputs of

the demultiplexer. Decoders are available as integrated circuits (MSI) where n = 3 and n = 4.

There is no theoretical reason why n can‘t be increased to higher values. However, there will be

always some practical limitations on the fan-in decoders of higher order and are often designed

using lower-order decoders which are interconnected with a network of other gates.

n-to-2n-line decoder

3 to 8 line decoder:

3 inputs are decoded into eight outputs where each output represents one of the minterms of

the 3 input variable.

EN A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 X X X 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 1

1 0 0 1 0 0 0 0 0 0 1 0

1 0 1 0 0 0 0 0 0 1 0 0

1 0 1 1 0 0 0 0 1 0 0 0

1 1 0 0 0 0 0 1 0 0 0 0

1 1 0 0 0 0 0 1 0 0 0 0

1 1 0 1 0 0 1 0 0 0 0 0

1 1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0

3 to 8 line

decoder

Difference

between

decoder and

demultiplexer:

Decoder Demultiplexer

(ii) It is used as a distributor switch to

(ii) Application: It is used as a code converter.

implement Boolean expressions.

(iii) There are no selection lines.

selection.

Step 1:

The design involves analysis of the common cathode 7-segment display. The 7-segment display

consists of an arrangement of LEDs in an ‘H’ form. A truth table is constructed with the

combination of inputs for each decimal number. Example, the decimal number 1 would

command a combination of b and c.

7 Segment LED

Step 2:

table listing the 7 display input

signals, decimal number and the

corresponding 4 digit binary

numbers. Hence, the truth table

for the decoder design depends

on the type of 7-segment display.

For a common cathode seven-segment display, the output of decoder or segment driver should

be active high in order to glow the segment. The truth table of a BCD to seven-segment decoder

with common cathode display is shown below. There are 7 different output columns

corresponding to each of the 7 segments in the truth table. Here, the column for segment ‘a’

shows the different combinations for which it is to be illuminated. Hence, ‘a’ is active for the

digits 0, 2, 3, 5, 6, 7, 8 and 9.

Digit A B C D a b c d e f g

0 0 0 0 0 0 0 0 0 0 0 1

1 0 0 0 1 1 0 0 1 1 1 1

2 0 0 1 0 0 0 1 0 0 1 0

3 0 0 1 1 0 0 0 0 1 1 0

4 0 1 0 0 1 0 0 1 1 0 0

5 0 1 0 1 0 1 0 0 1 0 0

6 0 1 1 0 0 1 0 0 0 0 0

7 0 1 1 1 0 0 0 1 1 1 1

8 1 0 0 0 0 0 0 0 0 0 0

9 1 0 0 1 0 0 0 0 1 0 0

From the above truth table, the equation obtained are as follows:

a = F1 (A, B, C, D) = ∑m (0, 2, 3, 5, 7, 8, 9)

b = F2 (A, B, C, D) = ∑m (0, 1, 2, 3, 4, 7, 8, 9)

c = F3 (A, B, C, D) = ∑m (0, 1, 3, 4, 5, 6, 7, 8, 9)

d = F4 (A, B, C, D) = ∑m (0, 2, 3, 5, 6, 8)

e = F5 (A, B, C, D) = ∑m (0, 2, 6, 8)

f = F6 (A, B, C, D) = ∑m (0, 4, 5, 6, 8, 9)

g = F7 (A, B, C, D) = ∑m (2, 3, 4, 5, 6, 8, 9)

Thus , these are the Boolean expressions for each output functions.

Step 3:

It involves constructing the K- map for each output term and then simplifying them for obtaining

a logic combination of the inputs for each output.

K-Map simplification

From the above simplification,

Step 4:

drawing a combinational logic

circuit for each output signal.

The combinational logic circuit can be drawn using 4 inputs (A, B, C, D)and a 7-segment display

(a, b, c, d, e, f, g) as output.

UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS

Sequential logic- SR, JK, D and T flip flops - level triggering and edge triggering -counters -

asynchronous and synchronous type - Modulo counters - Shift registers -design of synchronous

sequential circuits – Moore and Melay models- Counters, state diagram; state reduction; state

assignment.

3.1 Sequential logic

In digital circuit theory, sequential logic circuit is a type of logic circuit whose output depends not

only on the present value of its input signals but on the sequence of the past inputs. This is in

contrast to combinational logic whose output is a function of only the present input.

The sequential circuits are classified into two types based on the timing of their signals. They are,

2) Asynchronous sequential circuit

A synchronous sequential circuit is a system whose behaviour can be defined from the

knowledge of its signals at discrete instants of time.

The information stored in memory elements at any given time defines the present state of

sequential circuit. The present state and the external inputs determine the output and next state

of the sequential circuits.

Secondary variables:

The delay elements provide a short term memory for the sequential circuit. The present state

and the next state variables in the asynchronous sequential circuits are known as secondary

variables.

Comparison of combinational and sequential circuit:

1. The output depends only on the input present 1. The output depends not only on the inputs

at that input. but also on the past outputs.

Sequential logic:

Combinational circuits and systems create an output based on input variables only. Sequential

circuits use current input variables and past input variables by storing the information and

putting back into the circuit on the next clock cycle.

External inputs from outside the circuit design are not controlled by the circuit. Internal inputs

are a function of previous output states.

The internal inputs and the outputs are referred to as secondaries. Secondary inputs are the

state variables produced by the storage elements, whereas, secondary outputs are excitations

for the storage elements.

There are two types of sequential circuit called as synchronous and asynchronous circuits.

Synchronous types use a pulsed or level input and a clock input to drive the circuit.

Asynchronous sequential circuits do not use a clock signal as synchronous circuits where the

circuit is driven by the pulses of the inputs.

A pulsed output is an output that lasts for the duration of a particular input pulse but it can be

less in some cases. For the clocked sequential circuits, the output pulse is the same duration as

the clock pulse.

A level output refers to an output that changes the state at the start of an input or clock pulse

and remains in that state until the next input or clock pulse.

Flip-flop

In electronics, a latch or a flip-flop is a circuit which has two stable states which can be used to

store the state information.

A flip-flop is a bistable multivibrator which changes the state by applying signals to one or more

control inputs which will have one or two outputs.

called as a flip flop. It maintains

its output state either at 1 or 0

till it is directed by an input signal to change its state.

• SR flip-flop

• RS flip-flop

• D flip-flop

• JK flip-flop

• T flip-flop

SR flip flop

The circuit remains in a particular output state indefinitely until something is done to change its

output status. If the LOW and HIGH outputs are regarded as 0 and 1, then the output can either

be 0 or 1. Since either 0 or 1 can be held indefinitely until the circuit is appropriately triggered to

go to the other state, the circuit has memory. It is capable of storing one binary digit or one bit

of digital information.

We can find that, when one of the transistors was in saturation, the other was in cut-off. This

implies that if we had the outputs from the collectors of both the transistors, then the two

outputs would be complementary. In the flip-flops of various types that are available in IC form,

we will see that all these devices offer complementary outputs which are usually designated as

Q and Q’. The R-S flip-flop is the most basic flip-flops. The letters R and S stand for RESET and

SET. When the flip-flop is SET, its Q output goes to 1 state and when it is RESET, it goes to a 0

state. The Q output is the complement of Q output at all times.

Operation of RS flip-flop:

• When R input is high and S input is low, the Q output of flip-flop is reset.

• When R input is low and S input is high, the Q output of flip-flop is set.

• When both the inputs R and S are high, the output is unpredictable.

• When both the inputs R and S are low, the output does not change.

Truth table:

S R Q(t + 1) A B Y

0 0 Indeterminate 0 0 1

0 1 Set 0 1 1

1 0 Reset 1 0 1

1 1 NC 1 1 0

Logic diagram of SR flip-flop

JK flip flop

A J-K flip-flop is an R-S flip-flop except for one of the entries in the function table. In case of R-S

flip-flop, its input combination S = R = 1 and the input combination S = R = 0 are prohibited.

In the case of a J-K flip-flop with active HIGH inputs, the output of the flip-flop toggles goes to

the other state for J = K = 1. The output toggles for J = K = 0 in the case of the flip-flop having

active LOW inputs. Thus, the J-K flip-flop overcomes the problem of a forbidden input

combination of the R-S flip-flop. The below figure shows the circuit symbol of level-triggered J-K

flip-flops with active HIGH and active LOW inputs with their function tables.

The characteristic tables for a J-K flip-flop with active HIGH J and K inputs and a J-K flip-flop with

active LOW J and K inputs are shown in the below figure. The corresponding Karnaugh maps are

shown in below figure for the characteristics table. The characteristic equations for the Karnaugh

maps of below figure are given as follows,

inputs

Truth table

SET 1 0 1 1

RESET 0 1 1 0

NO CHANGE 0 0 1 Qn

TOGGLE 1 1 1

inputs

Truth table

SET 0 1 1 1

RESET 1 0 1 0

NO CHANGE 1 1 1 Qn

TOGGLE 0 0 1

JK flip-flop is an universal flip-flop. When configured in various ways, JK flip flop is capable of

operating like most other types of flip-flops.

Operation of JK flip-flop:

• When K input is high and J input is low, the Q output of the flip-flop is reset.

• When K input is low and J input is high, the Q output of the flip-flop is set.

• When both the inputs K and J are high, it is possible to set or reset the flip-flop (i.e.,) the

output toggle on to the next positive clock edge.

• When both the inputs K and J are low, the output does not change.

State diagram:

flop

State table:

Q J K Q(t + 1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

Q2 Q1 Q0

0 0 0

0 0 1

0 1 1

1 1 1

1 1 0

1 0 0

0 0 0

State diagram:

State table:

PS NS JK Input

Q2 Q1 Q0 Q0 + 1 Q2 + 1 Q1 + 1 J2 K2 J1 K1 J0 Ko

0 0 0 1 0 0 0 X 0 X 1 X

0 0 1 1 0 1 0 X 1 X X 0

0 1 0 0 0 0 0 X X 1 0 X

0 1 1 1 1 1 1 X X 0 X 0

1 0 0 0 0 0 X 1 0 X 0 X

1 0 1 0 0 0 X 1 0 X X 1

1 1 0 0 1 0 X 0 X 1 0 X

1 1 1 0 1 1 X 0 X 0 X 1

K - Map:

Logic

diagram

D flipflop

A D flip-flop also called as a delay flip-flop can be used to provide temporary storage of one bit of

information. The below figure shows the symbol of the circuit and the function table of a

negative edge-triggered D flip-flop.

When the clock is active, the data bit (0 or 1) present at the D input is transferred to the output.

In the D flip-flop, the data transfer from D input to Q output occurs on the negative(HIGH-to-

LOW) transition of the clock input where D input acquires a new status.

Function table

Truth table

Qn D Qn+1

0 0 0

0 1 1

1 0 0

1 1 1

K-map

Operation of D flip-flop:

occurrence of clock pulse, if D=1,

the output Q is set and if D=0, the output is reset.

State diagram of D-

flipflop

State table:

Q D Q(t + 1)

0 0 0

0 1 1

1 0 0

1 1 1

In D flip-flop, its next state is always equal to the D input and it is independent of the present

state.

T flipflop

The output of a toggle flip-flop is also called as a T flip-flop which changes its state every time

when it is triggered at its T input which is called as the toggle input. Its output becomes 1 if it

was 0 and 0 if it was 1.

If we consider the T input as active when HIGH, the characteristic table of such a flip-flop is

shown below. The characteristic equations written from the Karnaugh maps are as follows:

T flip-flop

T Qn Qn+1

↑ 0 1

↑ 1 0

Truth table

Qn T Qn+1

0 0 0

0 1 1

1 0 1

1 1 0

T flip-flop

T Qn Qn+1

↓ 0 1

↓ 1 0

Truth table

Qn T Qn+1

0 0 1

0 1 0

1 0 0

1 1 1

Operation of T flip-flop:

When the value of T = 1, the output switches to the complement state (i.e) the output toggles.

When T = 0, the state of the flip-flop remains unchanged. Therefore, for 0 to 0 and 1 to 1

transitions, T must be 0 and for 0 to 1 and 1 to 0 transitions, it must be 1.

Level triggering:

In the level triggering, the output state is allowed to change according to input when active level

(either positive or negative) is maintained at the enable input.

• Positive level triggered: The output of latch responds to the input changes only when its

enable input is 1 (HIGH).

Positive level triggering

• Negative level triggered: The output of latch responds to the input changes only when its

enable input is 0 (Low).

Negative level

triggering

The below figure

shows the circuit

and symbol for negative level triggered SR latch.

(a) Negative

level triggered

SR latch (b)

Logic symbol

Edge

triggering

In the edge triggering, the output responds to the changes in the input only at the positive or

negative edge of the clock pulse at the clock input.

• Positive edge triggering: Here, the output responds to the changes in the input only at the

positive edge of the clock pulse at the clock input.

Positive edge

triggering

• Negative edge

triggering: Here,

the output responds to the changes in the input only at the negative edge of the clock pulse at

the clock input.

Negative edge triggering

3.3.1 Counters

Counters in digital circuits are used to perform three functions as follows,

• Timing:

Building a precision digital clock is an example where a low frequency clock cannot be achieved

with a crystal oscillator.

• Sequencing:

Starting of a rocket motor is an example where the energizing of ignition, fuel pumps etc., must

follow a critical sequence.

• Counting:

Measuring the traffic flow on a road is an application in which the total number of vehicles

passing a certain point needs be counted.

Binary counter

A register that goes through a prescribed sequence of states on the application of input pulses is

called as a counter. A counter that follows the binary number sequence is called as a binary

counter

Lockout condition

• A counter follows the sequence of the derived states. If it enters into an unused or unwanted

state, then it is expected to return back to a desired state.

• If the next state of an unwanted state is again an unwanted state, then the counter is said to be

in the lockout condition.

When a stable count value is important across several bits, synchronous counters are utilized.

Either the D-type or the more complex J-K type flip flops are also used but each stage is clocked

simultaneously by a common clock signal.

The logic gates between each stage of the circuit control the data flow from stage to stage so

that the desired count behaviour is realized. Synchronous counters can be designed to count up

or count down or both according to a direction input and it is presetable through a set of parallel

jam inputs. Most types of hardware-based counters are of this type.

The simplest way of implementing the logic for each bit of an ascending counter is to toggle

when all of the less significant bits are at a logic high state.

For example, bit 1 toggle when bit 0 is at logic high and bit 2 toggles when both bit 1 and bit 0

are logic high, bit 3 toggles when bit 2 is at logic high level where bit 1 and bit 0 are all at logic

high level and so on.

Comparison between synchronous & asynchronous counters:

1. In this type of counter, flip-flops are 1. In this type, it has no connection between

connected in such a way that the output of the output of the first flip-flop and the clock

first flip-flop drives the clock for the next flip- input of the next flip-flop.

flop.

2. All the flip-flops are not simultaneously 2. All the flip-flops are clocked simultaneously.

clocked.

Programmable counters

• The truth table of the logic sequence for the counter which is intended to be designed is

obtained to obtain the state diagram of the counter.

• From the output state, K-map for simplification is used to derive the output functions of circuit

and flip flop.

Ripple counters

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an

external clock. Every subsequent flip-flops are clocked by the output of the preceding flip-flop.

The asynchronous counters are also known as ripple-counters since the clock pulse ripples

through the flip-flops.

The MOD of the asynchronous counter or ripple counter is 2n if n flip-flops are used. For a 4-bit

counter, the range of the count is 0000 to 1111 (2 4-1). The counter may count up or count down

depending on the input control.

Thus, the count sequence repeats itself. During the process of counting up, the count sequence

goes from 0000, 0001, 0010, ... 1110, 1111, 0000, 0001, ... etc., Counting down the count

sequence in the opposite manner is given as 1111, 1110, ... 0010, 0001, 0000, 1111, 1110, ...

etc.,

Thus, the complement of the count sequence counts in reverse direction. If the un-

complemented output counts up, the complemented output counts down and vice versa.

There are many ways to implement the ripple counter depending on the characteristics of the

flip flops used and requirements of the count sequence.

The clock trigger is either positive edged or negative edged. The flip flops used are JK or D flip-

flops. The count direction takes place are up, down or up/down.

The asynchronous counters are slower than synchronous counters because of the delay in

transmission of the pulses from flip-flop to flip-flop. In synchronous circuit, all the bits in the

counter changes synchronously with an assertion of the clock. The examples of synchronous

counters are the ring and Johnson counter.

The below circuit uses 2 D flip-flops to implement a divide-by-4 ripple counter (2 n = 22 = 4) which

counts down.

Divide-by-4 ripple

counter

State table

Count Q1 Q0

3 1 1

2 1 0

1 0 1

0 0 0

Timing

diagram

3.5

Modulo counters

2n = 50 i.e., n = 6 since 26 = 64

2n = 25 i.e., n = 5 since 25 = 32

Modulo-6 counter:

0 0 0 0 0 0 1 Yes 0

0 0 0 1 0 0 1 Yes 0

0 0 1 0 0 1 0 Yes 0

0 0 1 1 0 1 1 Yes 0

0 1 0 0 1 0 1 Yes 0

0 1 0 1 1 0 1 Yes 0

0 1 1 0 1 1 0 Yes 0

0 1 1 1 0 0 0 Yes 0

1 0 0 0 0 0 1 No 0

1 0 0 1 0 1 0 No 0

1 0 1 0 0 1 1 No 0

1 0 1 1 1 0 0 No 0

1 1 0 0 1 0 1 No 0

1 1 0 1 1 1 0 No 0

1 1 1 0 0 0 0 No 1

1 1 1 1 0 0 0 No 0

Representation of K-Map:

Mod 7 counter using D flip-flop:

A modulo-7 ripple counter is constructed using D flip flops without the NAND gate. This counter

functions as a modulo-8 binary counter. The presence of NAND gate alters the sequence as

follows.

1. The NAND gate output is connected to CLEAR (CLR) inputs of all the flip-flops. As long as NAND

gate output is HIGH, it will have no effect on counter. When the NAND gate output goes low, it

will clear all flip-flops and the counter immediately goes to 000 state.

2. The outputs of the counter QA, QB, Qc are given as inputs to the NAND gate. The output of

NAND gate goes low whenever Q A = QB = Qc=1. This condition will occur when the counter goes

from 110 state to 111 state. The low at the NAND gate output will clear the counter to the 000

state.

3. Therefore, the counting sequence is → 001 → 010 → 011 → 100 → 101 → 110 → 000 →

Mod 7 counter

using D flip-flop

Shift register

counters - ring

counter

A shift register can also be used as a counter. A shift register with a serial output connection to

the serial input is called as shift register counter.

i) Ring counter

ii) Johnson counter

Ring counter:

A ring counter is a circular shift register where one flip flop is set at any particular time and all

others are cleared.

A ring counter is a counter that counts up when it approaches the last number that it is designed

to count up which will reset itself back to the first number.

For example, a ring counter is designed using 3 JK flip flops which will count starting from 001 to

010 to 100 and back to 001. It will repeat itself in the form of a ring.

Johnson counter:

The Johnson counter is a K-bit switch-tail ring counter which has 2k decoding gates to provide

outputs for 2k timing signals.

A Johnson counter is a special case of shift register where the output from the last stage is

inverted and fed back as input to the first stage. A pattern of bits which is equal in length to the

shift register circulates indefinitely. These counters are sometimes known as walking ring

counters.

It is used in specialist applications including those similar to the decade counter, digital to analog

conversion, etc., and thus the name ring counter is obtained.

Shift counters

A synchronous counter that consists of clocked flip-flops is arranged as a shift register. Data is

propagated from left to right or vice versa between the flip-flops by the application of a count or

clock pulse.

Counting is achieved by setting the contents of the shift register to either logic 0 or logic 1 and

loading the leftmost or rightmost flip-flop with a logic 1 or a logic 0.

An m-bit counter has m flip-flops which require m clock pulses to shift this 1 or 0 to the

rightmost or the leftmost flip-flop.

The position in the register of the 1 or 0 acts as a count of the number of pulses received when

the load is applied.

The counter counts continuously by arranging the output of the rightmost or the leftmost flip-

flop to set the input of the leftmost or the rightmost flip-flop. The counter is then known as a

ring counter.

3.7 Design of synchronous sequential circuits - Moore and Melay models - Counters

The recommended steps for the design of a clocked synchronous sequential circuit are as

follows:

1. The state table from the given circuit information such as a state diagram, a timing-diagram or

other pertinent information is obtained.

2. The number of states may be reduced by state reduction technique if the sequential circuit

can be categorized by input-output relationships which are independent of the number of states.

4. The number of flip-flops needed is determined and a letter symbol to each flip-flop is

assigned.

6. The circuit excitation and output tables are derived from the state table.

7. The output functions of the circuit and the input functions of the flip-flop are derived using

the K-map or any other simplification method and the logic diagram are drawn.

Problems

1. Let us consider the following sequence that is to be realized by a counter consisting of 3 JK flip

flops.

A1 0 0 0 0 1 1 0

A2 0 1 1 0 0 1 0

A3 0 1 0 1 1 0 0

Solution:

Given:

A1 0 0 0 0 1 1 0

A2 0 1 1 0 0 1 0

A3 0 1 0 1 1 0 0

Truth table:

0 0 0 0 1 1 0 X 1 X 1 X

0 1 1 0 1 0 0 X X 0 X 1

0 1 0 0 0 1 0 X X 1 1 X

0 0 1 1 0 1 1 X 0 X X 0

1 0 1 1 1 0 X 0 1 X X 1

1 1 0 0 0 0 X 1 X 1 0 X

K-map:

State diagram

3.7.1 Moore and Melay models

Synchronous sequential circuits changes (affect) their states for every positive (or negative)

transition of the clock signal based on the input. So, this behavior of synchronous sequential

circuits can be represented in the graphical form and it is known as state diagram.

A synchronous sequential circuit is also called as finite state machine if it has finite number of

states. There are two types of finite state machine as follows,

A finite state machine is said to be Mealy state machine if output depends on both present

inputs & present states. The block diagram of Mealy state machine is shown in the below figure.

As shown in the above figure, there are two parts present in Mealy state machine namely

combinational logic and memory. Memory provides part of previous outputs (present states) as

inputs of combinational logic.

Based on the present inputs and present states, the Mealy state machine produces outputs.

Therefore, the outputs will be valid only at positive (or negative) transition of the clock signal.

The state diagram of Mealy state machine is shown in the below figure.

State

diagram

of

Mealy

state

machine

In the

above

figure,

there

are

three

states namely A, B & C. These states are labelled inside the circles & each circle corresponds to

one state. Transitions between these states are represented by a directed lines. Here, 0/0, 1/0 &

1/1 denotes input/output. In the above figure, there are two transitions from each state based

on the value of input, x.

In general, the number of states required in Mealy state machine is less than or equal to the

number of states required in Moore state machine. There is an equivalent Moore state machine

for each Mealy state machine.

A finite state machine is said to be a Moore state machine if outputs depend only on present

states. The block diagram of Moore state machine is shown in the below figure.

Moore state machine

As shown in the above figure, there are two parts present in Moore state machine namely

combinational logic and memory. In this case, the present inputs and present states determine

the next states. So, based on next states, Moore state machine produces the outputs. Therefore,

the outputs will be valid only after transition of the state.

The state diagram of Moore state machine is shown in the below figure.

In the above figure, there are four states namely A, B, C & D. These states and the respective

outputs are labelled inside the circles. Here, only the input value is labeled on each transition. In

the above figure, there are two transitions from each state based on the value of input, x.

In general, the number of states required in Moore state machine is more than or equal to the

number of states required in Mealy state machine. There is an equivalent Mealy state machine

for each Moore state machine. So, based on the requirement we can use one of them.

Problems

1. Let us draw the state transition diagram of a sequence detector circuit that detects ‘1010’

from input data stream using Moore model and Mealy model.

Solution:

Given:

Moore model Mealy model

State table

PS NS Y

A A B 0 0

B C B 0 0

C A D 0 0

D C B 1 0

3.7.2 Counters

Decoder counter has a count sequence from 0000 to 1001 (9). After 1001 state, it must recycle

to 0000 state. This counter requires four flip - flops and AND/OR logic gates.

J0 = K 0 = 1

J1 = K1 = Q0Q3

J2 = K 2 = Q 0 Q 1

J3 = K3 = Q0Q1Q2 + Q0Q3

4 - bit

Timing diagram

state reduction - state

assignment

status of the flip flops

in a sequential circuit. If there are n flip flops, then the circuit has 2n possible states.

State diagram

State diagram is

the graphical

representation of

the information

available in a

state table. In

state diagram, a

state is indicated

by a circle and the

transitions

between states are indicated by directed lines to connect the circles.

In addition to tables, graphical symbols or equations, flip-flops is represented graphically by a

state diagram. An example of a state diagram is shown in the above figure.

State table

The state table representation of a sequential circuit consists of three sections which are labelled

as present state, next state and output.

The present state designates the state of flip-flops before the occurrence of a clock pulse. The

next state shows the states of flip-flops after the clock pulse and the output section lists the

value of the output variables during the present state.

A state table gives the time sequence of inputs, outputs and flip-flop states. The table consists of

four sections labelled as input, output, present state and next state.

The partition consists of one or more blocks where each block consist of a subset of states that

may be equivalent but the states in a given block are not equal to the states in other blocks. Any

design process must consider the problem of minimizing the cost of the final circuit. The two

most obvious cost reductions are reductions in the number of gates and the number of flip-flops.

The number of states in a sequential circuit is closely related to the complexity of the resulting

circuit. Therefore, it is desirable to know when two or more states are equivalent. The process of

eliminating the redundant or equivalent states from a state table/diagram is known as the state

reduction.

The three main methods of state reduction include implication charts, row matching and

successive partitioning. Row matching is the easiest of the three which works well for state

transition tables that has an obvious next state and output equivalences for each of the present

states. This method does not give the most simplified state machine available but it is easy to

use and consistently fair results is a good reason to pursue the method.

The implication chart makes use of a graphical grid to find any implications or equivalences and

it is a great systematic approach in reducing the state machines. Successive partitioning is almost

a cross between implication chart and row matching where both the graphical table and

equivalent matching can be used. Each of these methods reduces the state machine into a

smaller number of states where one method may result in a simpler state machine than another.

• A second partition (P2) by separating the states into two blocks based on their output values is

formed.

• A third partition (P3) by separating the states into blocks corresponding to the next state values

is formed.

• Partitioning is continued until two successive partitions are same (i.e. PN-1 = PN).

State table:

X=0 X=1 X=0 X=1

A B C 1 0

B F D 0 0

C D E 1 1

D F E 0 1

E A D 0 0

F B C 1 0

X=0 X=1 X=0 X=1

A B C 1 0

B A D 0 0

C D E 1 1

D A E 0 1

E A D 0 0

It can be seen from the table that both the present state A and F have the same next states B

(when x=0) and C (when x=1). They also produce the same output 1 (when x=0) and 0 (when

x=1). Hence the states A and F are equivalent. Thus one of the states, A or F can be removed

from the state table. For instance, if we remove row F from the table and replace all F's by A's in

the columns, the state table is modified as shown above.

It is apparent that states B and E are equivalent. Removing E and replacing E's by B's results in

the reduced table shown in the following table.

X=0 X=1 X=0 X=1

A B C 1 0

B A D 0 0

C D B 1 1

D A B 0 1

The removal of equivalent states has reduced the number of states in the circuit from six to four.

Two states are considered to be equivalent if and only if every input sequence in the circuit

produces the same output sequence irrespective of which one of the two states is the starting

state.

Stat a a b c d e f f g f g a

e

Inpu 0 1 0 1 0 1 1 0 1 0 0

t

Outp 0 0 0 0 0 1 1 0 1 0 0

ut

Two states are said to be equivalent if every possible input produces exactly the same output

and have equivalent next state.

Present state Next state Output

a a b 0 0

b c d 0 0

c a d 0 0

d e f 0 1

e a f 0 1

f g f 0 1

g a f 0 1

a a b 0 0

b c d 0 0

c a d 0 0

d e f 0 1

e a f 0 1

f e f 0 1

After the first reduction, we can see that state d and state f will have the same output and next

state for both x=0 and x=1.

Reduced output sequence:

State a a b c d e d d e d e a

Input 0 1 0 1 0 1 1 0 1 0 0

Outpu 0 0 0 0 0 1 1 0 1 0 0

t

a d c 0

b f h 0

c e d 1

d a e 0

e c a 1

f f b 1

g b h 0

h c g 1

unsatisfied conditions

is deleted.

Step 3: Step 2 is repeated until all the equivalent states are found.

a a c 0

b f h 0

c c a 1

f f b 0

g b h 1

h c g 1

The cost of the combinational circuit of a sequential circuit can be reduced by using the known

simplification methods for combinational circuits. State assignment procedures are concerned

with methods for assigning binary values to states to reduce the cost of combinational circuit

that drives the flip-flops.

ii) One hot state assignment

Races can be avoided by making a proper binary assignment to the state variables. Here, the

state variables are assigned with binary numbers in such a way that only one state variable

change at any one time when a state transition occurs. To accomplish this, it is necessary that

states between which transition occur are given adjacent assignments. Two binary values are

said to be adjacent if they differ in only one variable. For example, 110 and 111 are adjacent

because they differ only in the third bit.

The below figure shows the transition diagram. The transition diagram shows that there is a

transition from state a to state b and transition from state a to state c. The state a is assigned

binary value 00 and state c is assigned a binary value of 11. This assignment will cause a critical

race during the transition from a to c because there are two changes in the binary state

variables. A race free assignment is obtained by introducing addition binary state say d with

binary value 10 which is adjacent to both a and c.

Transition diagram

modified transition diagram. As

shown in the below figure, the

transition from a to c will go

through d. This causes the

binary variables to change from 00 → 10 → 11 which satisfy the condition that only one binary

variable changes during each state transition to avoid the critical race.

row state assignment because, in

this technique, extra state, i.e.

extra row is introduced in a flow

table. This extra state is shared

between two stable states.

The one hot state assignment is another method for finding a race-free state assignment. In this

method, only one variable is active or hot for each row in the original flow table, i.e. it requires

one state variable for each row of the flow table. Additional rows are introduced to provide

single variable changes between internal state transitions. This is described in the following

example.

Let us consider a flow table given below where four state variables are used to represent the

four rows in the table. Each row is represented by a case where only one of the four state

variables is a 1. A transition from state A to state B requires two state variable changes i.e. F1

from 1 to 0 and F2 from 0 to 1. By directing the transition A to B through a new row E which

contains 1’s where both states A and B have 1’s. We require only one state variable change from

transition A to E and then from transition E to B. This permits the race-free transition between A

and B.

Flow table

state variable Fi is 1 and

all other state variables

are 0. When a transition

between row i and row j

is required, first state variable Fj is set to 1 (Both Fi and Fj are 1) and then Fi is set to 0. Thus each

transition between two rows in the flow table goes through one intermediate row. This permits

the race-free transition but requires two state transition times.

The below figure shows the complete one hot state assignment flow table. When X 1 X2 = 01, the

transition from A to B is passing through the dummy state E. Similarly, when X 1 X2 = 00, the

transition from C to A is passing through the dummy state F and so on. The original table gets

modified and it is shown in the below table.

assignment

flow table

UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABILITY LOGIC

DEVICES

Asynchronous sequential logic circuits-Transition stability, flow stability-race conditions, hazards

& errors in digital circuits; analysis of asynchronous sequential logic circuits introduction to

Programmability Logic Devices: PROM – PLA –PAL, CPLD-FPGA.

4.1 Asynchronous sequential logic circuits

Sequential circuits without clock pulses are called as asynchronous sequential circuits.

Block

diagram of

an

where,

E - Excitation

M - Memory

The fundamental mode asynchronous circuit design is based on the following assumptions.

(i) The inputs to the asynchronous circuit design are based on the following assumptions that

happens only when the circuit is stable where the state variables are not in their transition state.

(ii) Another assumption is that the inputs are levels but are not pulses.

(iii) The state variables in the circuit are characterized as delay elements. Delay is introduced by a

latch or simply the propagation delay inherent in the logic gates is used for realizing the

asynchronous circuits.

Procedure:

1. The transition table that specifies the excitation functions Y = Y 1, Y2,. . . Yk is given and a pair of

maps for Si and Ri for each i = 1, 2, ..., K is derived. This is done by using the condition specified in

the latch excitation table.

2. The Boolean functions for each Si and Ri are derived and care must be taken not to make S i and

Ri equal to 1 in the same minterm square.

3. The logic diagram is drawn using k latches together with the gates required to generate the S

and R Boolean functions.

In case of synchronous sequential circuit, we derive the excitation table from the state table,

whereas, it is reverse in the case of asynchronous sequential circuit.

ASM chart

may not be 1.

state is S1. For all other

combinations, the state

remains at S0.

state is S2 where output z

becomes 1.

When C becomes zero, the state goes to S3 and remains there until S becomes zero and when S =

0, the system returns to So state.

Timing diagram

State diagram

Flow table:

00 01 11 10

Transition table:

F2 F1

F2 (t + 1) = F2F1

+ F1C + F2S

z = F2F1C

The implementation can be done with DFF. F1 and F2 with C is their clock input and S is their

signal input.

Problems

1. Let us sketch the transition table and state table for an asynchronous sequential circuit

described by the following Boolean expressions.

Y1 = XY1 + X'Y2

Y2 = XY1' + X'Y2

Solution:

Given:

Y1 = XY1 + X'Y2

Y2 = XY1' + X'Y2

Y1 = XY1 +

X Y1 Y2 XY1

0 0 0 0 0 0 0 0

0 0 1 0 1 0 1 1

0 1 0 0 0 0 0 0

0 1 1 0 1 0 1 1

1 0 0 0 0 1 0 1

1 0 1 0 0 1 0 1

1 1 0 1 0 0 1 0

1 1 1 1 0 0 1 0

Transition table

sequential logic circuit for the

state transition diagram.

Solution:

Given:

Let Ps → Z

Ns → Z+

Input → XY

Transition table:

00 01 11 10

a a a b b

b a b b b

Present state Next state

00 01 11 10

0 0 0 1 1

1 0 1 1 1

K-Map:

Logic diagram

3. Let us design an

asynchronous

sequential circuit that will output only the first pulse received and any further pulses will be

ignored.

Solution:

Timing diagram

State diagram

Primitive flow

table:

0 1

a a, 0 b, 0

b c, - b, 1

c ©, 0 d, 0

d c, 0 d, 0

Minimized flow table is obtained by merging ‘c’ and ‘d’ states.

0 1

a a, 0 b, 0

b c, - b, 1

c, d ©, 0 d, 0

Binary assignment:

a → 00 b → 01 c → 11

Transition table

Map for Y1

Map for Y2

Output map

Logic diagram

4.2 Transition

stability, flow

stability-race

conditions

Transition

table

The transition table is obtained by combining the map for Y 1 and Y2. The transition table is a table

which gives the relation between present state, input and next state. The stable states are

indicated by circles. An uncircled entry represents an unstable state.

In a transition table, there will be at least one stable state in each row. Otherwise, all the states

in that row will be unstable.

Transition table

Flow table

states are named by letter symbols

without making specific reference to

their binary values. The flow also includes the output values of the circuit for each stable state.

Flow table in asynchronous sequential circuit

The state change in asynchronous machines occurs which is independent of clock based on the

logic propagation delay and it causes the states to flow from one to other. Hence, the name flow

tables are obtained.

• Flow table is the one in which the states are named by letter symbols without making specific

reference to their binary values. The flow also includes the output values of the circuit for each

stable state.

• Transition table is a table which gives the relation between present state, input and next state.

Problems

1. Let us design an asynchronous sequential circuit whose output responds for every even

numbered clock pulse.

Solution:

Timing diagram

Let us assign

binary values

and obtain

the transition

table and

output map.

a → 00

b → 01

c → 11

d → 10

Transition table

Next state

variables Y1Y2

2. Let us

design an

asynchronous

sequential

circuit that has

two inputs X2

and X1 and one output Z. The output remains as '0' as long as X 1 is '0'. The first change in X 2

that occurs while X1 is 1 will cause Z to be '1' where Z remains '1' until X1 returns to zero.

Solution:

Timing diagram

State

00 01 11 10 00 01 11 10

A (A) C - B 0 0 - 0

B A - D (B) 0 - 0 0

C A (C) E - 0 0 - -

D - F (D) B - - 0 0

E - F (E) B - 1 1 -

F A (F) (E) - - 1 1 -

Merger diagram

these states as well as the next

states.

For example, A has the next states as A, C and B with outputs 0, 0, -0. Similarly, C has the next

states A, C, E with outputs 0, 0, -, -. Thus, the total number of states reduces to three assigning

the states names as S0, S1 and S2.

A, C→ S0

B, D→ S1

E, F→ S2

Reduced state

diagram

State assignment

S0 – 00

S1 - 01

S2 - 11

S3 - 10 (destiny)

State assignment

Reduced flow table

00 01 11 10 00 01 11 10

S0 (S0) (S0) S2 S1 0 0 - 0

S1 S0 S2 (S1) (S1) 0 - 0 0

00 01 11 10 00 01 11 10

S0 0 0 S0 S0 S3 S1 0 0 - 0

S1 0 1 S0 S2 (S1) (S1) 0 - 0 0

S2 1 1 S3 (S2) (S2) S1 - 1 1 -

S3 1 0 S0 - S2 - - - - -

Transition table is constructed from the above table and after map reduction, the output and

state equations are arrived.

Transition table

Present

F2 F1 Next state Output

state

00 01 11 10

F2 F1 F2 F1 F2 F1 F2 F1 00 01 11 10

S0 0 0 0 0 0 0 1 0 0 1 0 0 - 0

S1 0 1 0 0 1 1 0 1 0 1 0 - 0 0

s2 1 - 1 0 1 1 1 1 0 1 1 - 1 -

S3 1 0 0 0 - - 1 1 - - - - - -

3. Let us derive the flow table for the circuit given in the below figure.

Solution:

Given:

• There is two

feedback path present

in the circuit where Y1

and Y2 are state

variables.

• X is the input

variable and Z is the

output variable.

Present total state Next total state Total stable state Output

0 0 0 0 1 0 No 0

0 0 1 0 0 0 No 0

0 1 0 0 1 0 Yes 1

0 1 1 0 0 0 No 1

1 0 0 1 0 1 No 0

1 0 1 1 0 1 Yes 0

1 1 0 1 0 0 No 0

1 1 1 1 0 0 No 0

table

When 2 or more binary state variables change their value in response to a change in an input

variable, race condition occurs in an asynchronous sequential circuit. In case of unequal delays, a

race condition causes the state variables to change in an unpredictable manner.

In JK flip flop, if both J and K are high and when clock is also 1, then output toggles continuously

between set and reset state. This condition is called as a race around condition. The clock should

be made zero before the output reaches the input side to avoid racing condition. The principle is

used in master slave and edge triggered flip flops.

Instability

The feedback connections that exist in an asynchronous circuit make the circuit unstable. If there

is an unstable condition, then it will force the circuit to oscillate between the unstable states.

When an asynchronous circuit makes a transition through a unique sequence of unstable states,

a cycle occurs.

In an asynchronous machine, a race condition occurs if two or more state variables change their

values when there is a state transition. When two or more binary state variables change their

value in response to a change in an input variable, race condition occurs in an asynchronous

sequential circuit.

In case of unequal delays, a race condition causes the state variables to change in an

unpredictable manner. There are two categories of races as follows.

(ii) Critical races

Non-critical races:

The final stable state that the circuit reaches does not depend on the order in which the state

variable changes where the race condition is not harmful and it is called as a non- critical race.

Critical race:

If the final stable state depends on the order in which the state variable changes, the race

condition is harmful and it is called as a critical race.

4.3 Hazards & errors in digital circuits - analysis of asynchronous sequential logic circuits

Hazard is an unwanted transient i.e., spike or glitch occurs due to unequal path or unequal

propagation delays through a combinational circuit.

Types of hazards:

There are 3 types of hazards as follows.

1. Static

2. Dynamic

3. Essential

Static:

Static hazard is a condition which results in a single momentary incorrect output due to

change in a single input variable when the output is expected to remain in the same state.

i. Static - 0 hazard

ii. Static - 1 hazard

If the output changes from 1 to 0 when there is no transition, it is called as static-1 hazard and if

it changes from 0 to 1 without any change, it is called as static-0 hazard.

0 - hazard

(c) Dynamic

hazard

Types of Hazards

Dynamic hazard:

Dynamic hazard occurs when the output of a network changes between its two logic states but a

false output signal occurs during the transient behaviour.

A dynamic hazard is defined as a transient change which occurs 3 or more times at an output

terminal of a logic network when the output changes only once during a transition between two

input states which differs in the value of one variable. If the output changes, there is more time

from 1 to 0 or from 0 to 1 where no transition is needed which is called as dynamic hazard.

Dynamic hazard

Essential hazard:

Essential hazard is a type of hazard that exists only in asynchronous sequential circuits with two

or more feedbacks. An essential hazard is caused by unequal delays along two or more paths

that originate from the same input.

An excessive delay through an inverter circuit in comparison to the delay associated with the

feedback path may cause an essential hazard. When a single variable change produces a

momentary change in output and there is no change in output, it is called as an essential hazard.

Example:

Initially, x1 = x2 = x3 =

1. The output of

gate 1 is 1 and gate

2 is 0 and output of

the above circuit is Y = 1. If X2 changes from 1 to 0, gate 1 becomes 0 and gate 2 becomes 1

where Y = 1. But the output may momentarily change from 1 to 0 if delay to NOT gate is

considered.

Hazards in combinational circuits

Let us assume

initially inputs X1

and X3 = 0 and X2

= 1. This causes

output of gate 1

to be 0, output of gate 2 to be 1 and the output of the circuit to be equal to 1. Let us consider a

change in X2 from 1 to 0. The output of gate 1 changes to 1 and that of gate 2 changes to 0

leaving the output at 1. However, the output goes to 0 if the propagation delay through the

inverter is taken into consideration.

Eliminating hazard

two minterms or maxterms. For example, if the circuit has minterms then these two minterms

must be enclosed by introducing another minterm.

Hazards in

sequential

circuits:

In the

normal combination where the circuit design is associated with synchronous sequential circuits,

hazards are not of concern since momentary erroneous signals are not troublesome. However, if

a momentary incorrect signal is fedback in an asynchronous sequential circuit, the circuit may go

to the wrong stable state. This is illustrated in the following example.

If the circuit is in total stable state and input X 2 changes from 1 to 0, the next total stable state

should be 110. However, because of the hazard, output Y may go to 0. If this false signal feeds

back into gate 2 before the output of the inverter goes to 1, the output of gate 2 will remain at 0

and the circuit will switch to the incorrect total stable state 010. This malfunction can be

eliminated by adding an extra gate.

Hazards are

eliminated by

adding

additional

gates

Problems

1. Let us draw the logic diagram for the product of sums expression given by Y = (x 1 + x2') (x2 +

x3). Let us show that there is a static 0 - hazard when x 1 and x3 are equal to 0 and x2 goes from 0

to 1. Let us also find a way to remove the hazard by adding one OR gate.

Solution:

Given:

output of gate 1

to be 0, output

of gate 2 to be 1

and the output

of the circuit to be 0. Let us consider a change in x2 from 1 to 0. The output of gate 1 changes to

1 and that of gate 2 changes to 0 leaving the output at 1. However, the output goes to 0 if the

propagation delay through the inverter is taken into consideration.

The delay in the inverter causes the output of gate 2 to change to 0 before the output of gate 1

changes to 1. In this situation, both inputs of gate 3 are equal to 0 causing the output to go to 0

for the short time which is equal to the propagation delay of the inverter.

The hazard exists because of the change of input which results in a different product terms

which covers two minterms or different sum terms to cover two maxterms. Whenever the circuit

move from one product term to another or from one sum term to another, there is a possibility

of an interval when neither term is equal to 1 giving rise to an undesirable 0 output.

Hazards can be eliminated by enclosing

two minterms (or) maxterms. The circuit has minterms then these two minterms must be

enclosed by introducing another minterm X1X3.

2. Let us find a circuit that has no static hazards and implement the Boolean function: F(A, B, C,

D) = (0, 26, 7, 8, 10, 12).

Solution:

Given:

given as,

4.3.1

The general steps for the analysis of asynchronous sequential circuit are as follows.

1) The output of the latches X1+, X2+,...... and their external feedback paths X 1, X2,..., etc., are

labelled.

latch and for every NAND latch in the above given circuit.

6) The individual maps are combined into one map for X+ such as X+= X1+, X2+, X3+ ... X+.

7) The stable states where X+ = X are circled. The resulting map to the transition table is given in

the below figure.

Truth table

0 0 0 0 0 1

1 0 0 0 1 1

2 0 0 1 0 1

3 0 0 1 1 1

4 0 1 0 0 1

5 0 1 0 1 1

6 0 1 1 0 1

7 0 1 1 1 1

8 1 0 0 0 0

9 1 0 0 1 0

10 1 0 1 0 0

11 1 0 1 1 0

12 1 1 0 0 0

13 1 1 0 1 0

14 1 1 1 0 0

15 1 1 1 1 0

K-map for reset logic

Logic diagram

Timing diagram

4.4 Introduction

to

programmability

logic devices:

PROM - PLA - PAL, CPLD - FPGA

Classification

of memory

ROM: Read-

only

memory

Information cannot be easily stored where the bits are initially decoded and are never changed.

ROM organization

It is a read only memory. We can't write data in this memory. It is non-volatile memory i.e., it can

hold data even if power is turned off. There are four types of ROM namely masked ROM, PROM,

EPROM and EEPROM or E2PROM.

ROM

Masked ROM:

In masked ROM, mask programming is done by the manufacturer during the last fabrication

process of the unit. The procedure for fabricating a ROM requires the truth table of the ROM.

PROM

Bits can be set on a programming bench by burning fusible links or equivalent. This technology is

also used for programmable array logic (PAL). The figure below shows four byte PROM. It has

diodes in every bit position, therefore, the output is initially 0.

Each diode has a fusible link in series with it. By addressing bit and applying proper current pulse

at the corresponding output, we can blow out the fuse by storing logic 1 at that bit position. The

PROM programmer burns the fuses according to the bit pattern to be stored. This process is

known as burning of PROM. It is one time programmable. Once programmed, the information

stored is permanent.

PROM

Programmable Logic Array (PLA)

A programmable logic array (PLA) is a kind of programmable logic device which implements the

combinational logic circuits. The PLA has a set of programmable AND gate planes which is

connected to a set of programmable OR gate planes which can then conditionally complement

an output. This layout permits a large number of logic functions to be synthesized in the sum of

products canonical forms.

PLA's differ from Programmable Array Logic devices (PALs and GALs) where both the AND and OR

gate planes are programmable. The logic gates can be two level AND-OR, NAND-NAND or NOR-

NOR configuration. The PLA consists of two level AND-OR circuit on the same chip. The AND

matrix implements the product terms in the SOP form and the OR matrix is used for

implementing the sum of product terms.

Input buffers::

Input buffer in a PLA avoids the loading of sources connected at the input.

Block diagram:

Internal construction:

In PLA, both the AND and OR gates are programmable. The internal construction of PLA ha s

3 inputs, 3 product terms and two outputs as shown in the below figure.

Internal construction of PLA

The size of PLA is specified by number of inputs, the number of product terms and the number

of outputs. A PLA can be mask-programmable or field programmable. PLA consists of inputs,

outputs, sum terms and product terms.

The product terms constitute a group of AND gate and sum terms constitute a group of OR gates.

Fuses are inserted between all inputs and their complement value to each of the AND gates.

Fuses are also provided between the output of AND gates and the inputs of OR gates. The third

set of fuses in the output inverters allows the output function to be generated either in AND-OR

form or in the AND-OR-INVERT form.

AND matrix:

There is 2M input (from) for each AND gate where P0 is the output of an AND gate. The Boolean

expression for P0 is given as,

There is a nichrome fuse link connected in series with each input. The above expression

produces P0 = 0 if all the fuse linker is intact.

OR matrix:

P0, P1, ....., PM-1 are the output of an AND matrix. They are used as the inputs to the OR matrix.

The OR gate is formed by parallel connected transistors and the load is common which is

connected in the emitters. S0, S1, ....., SN-1 are the output of the OR matrix.

Invert/Non-invert matrix:

The block following the OR matrix is the inverting/non-inverting matrix which is basically a

programmable buffer.

It can invert its input if active low output is required. The input is passed without any inversion if

active high output is required.

Output buffer:

The current sourcing capability of the PLX can be increased by using the output buffer.

Advantages of PLA:

(i) In PLA, the number of don’t care conditions are excessive as PLA is more economical than

ROM.

(ii) A PLA is similar to a ROM in concept, however, it does not provide full decoding of the

variables and does not generate all the minterms as in the ROM.

(iii) The PLA replaces the decoder by group of AND gates, each of which can be programmed

to generate a product term of input variables.

Programmable Array Logic (PAL) is a family of programmable logic device semiconductors which

is used to implement logic functions in digital circuits introduced by Monolithic memories, Inc.

(MMI) in March 1978. MMI is obtained as a registered trademark on the term PAL for use in

programmable semiconductor logic circuits. The trademark is currently held by a lattice

semiconductor.

PAL devices consist of a small PROM (programmable read-only memory) core and the additional

output logic implements particular desired logic functions with few components. Using

specialized machines, PAL devices were field-programmable. PAL was available in several

variants:

One-time programmable (OTP) devices cannot be updated and reused after initial programming.

UV erasable versions (e.g.: PALCxxxxx, e.g.: PALC22V10) had a quartz window over the chip die

and could be erased for reuse with an ultraviolet light source just like an EPROM.

Later versions (PALCExxx e.g.: PALCE22V10) were flash erasable devices.

PLA PAL

(i) PLA is a device with a programmable AND array and (i) PAL is a programmable logic device with a fixed

programmable OR array. OR array and array programmable AND array.

(ii) PLA is comparatively difficult to program as both (ii) PAL is easier to program as only AND gates are

AND and OR array are programmable. programmable.

CPLD:

Complex Programmable Logic Device (CPLD) is a programmable logic device and it can be

programmed by using VHDL. CPLD is based on EPROM or EEPROM technology. CPLD have

extended density than the SPLD.

CPLD have a few macrocells on a single chip with simple logic paths. CPLD are classified

depending on the architecture which gives rise to high speed, detailed timing and simple

software flow. The basic CPLD consists of configurable logic block (CLB) which consists of AND

gate arrays and interconnects.

The logic blocks are programmable AND, fixed OR devices. PAL and GAL are available only in

small sizes which is equivalent to a few hundred logic gates. CPLD is an arrangement of multiple

SPLD-like blocks on a single chip. CPLD consists of multiple circuit blocks in chip. The circuit block

in CPLD is same as that of PLA or PAL blocks.

The below figure below shows the example of a CPLD. This CPLD has four PAL blocks which are

connected through interconnection wires. The PAL block is also connected to a sub-circuit which

is known as I/O block. The I/O block is connected to number of input and output pins. The PAL

block consists of macrocells. The macrocell consists of flip-flop, a multiplexer and a tri-state

buffer. The flip-flop is used to store the output value produced by the OR gate.

The tri-state buffer acts as a switch. In function block, the AND array gets inputs from the I/O

blocks and other function blocks. The product terms are given to fixed OR gates. The outputs of

the multiplexer are sent through a clocked flip-flop. The function blocks are designed similar to a

PAL architecture. The I/O block drives signals to the pins of the CPLD device. The CPLD

interconnect is a programmable switch matrix. No switch can connect all internal function blocks

to all other function blocks, therefore, flexibility is achieved.

CPLD

Functional block of

CPLD:

shows the typical

CPLD architecture

which has four

functional blocks of PLD.

Functional block of

CPLD

have programmable

interconnections. A

switch matrix is used

for function blocks to

function blocks

interconnections. Further, switch matrix in a CPLD may or may not be fully connected. This

shows that some of the connections between function block outputs and inputs are not

supported in the CPLD.

The complexity of a typical PAL device is around few hundred logic gates, whereas, the

complexity of CPLD is around tens of thousands of logic gates.

The CPLD has predictable timing characteristics which are suitable for critical control applications

and other applications where a high performance level is required. Further, due to low power

consumption and low cost, CPLD is used for battery-operated portable applications such as

mobile phones, digital assistants etc.,

Advantages of CPLD:

1) Easy to design: CPLD gives a simple way to implement designs.

2) Lower cost: CPLD requires low costs due to the reprogrammable feature.

3) Large product profit: CPLD requires very short development cycles because of which products

time to market is faster and generates the profit.

4) Lower board area: CPLD has a high level of integration.

5) Simple design changes due to reprogramming.

6) CPLD is used in wide applications for prototyping small gate arrays

To increase the effective size and measure, the number of directions alternative architecture for

SPLD and CPLD have been developed which are called as field programmable gate array (FPGA).

Field Programmable Gate Array (FPGA) is a flexible architecture programmable logic device.

It is a single Very Large Scale Integrated (VLSI) circuit constructed on a single piece of silicon. It

consists of identical individually programmable rectangular modulus.

The modules are separated in both horizontal and vertical directions by horizontal and vertical

metallic conductors called as channels. In addition, each module has vertical and horizontal

conductors at its input and output that cross one or more of the channels.

The content of the modules depends on the type of FPGA for easy use where the modules need

to be programmable into the gates and sequential elements. A module may have both

combinational and sequential elements and components.

Architecture of FPGA:

Architecture of FPGA

3) and an OR gate whose output selects the MUX 3.

In an FPGA, there is no distinct input and output stages as in the AND-OR array and macro cell of

a PAL and GAL considers an exemplary FPGA with all the logic cells arranged in the array form

12×8 or 24×32 matrix which are examples of the array structures. A logic cell is also called as the

array structures. A logic cell is also called as CLB (Configurable Logic Block). A 12 × 8 matrix has

96 logic cells.

i) Two number six input AND gates, four number two input AND gates, three number 2 to 1 MUX

and clock input edge triggered DFF with the preset and clear inputs.

ii) Three number outputs from the AND, one output from the MUX and one output from D FF.

The total number of inputs are 21 and outputs are 5 for a logic cell. SOP function on the inputs

are obtained but the multiplex and decoding functions occur at the inputs of the logic cell.

FPGA is configurable

as JK FF, RS FF or FFF

which facilitates the

implementation of the

16 or 32 bit circuit for

the various types of

the shift registers and

counters. The number

of logic cells can be

very large.

Comparison between PROM, PLA, PAL:

PROM AND array is fixed and Both AND & OR arrays are AND array is programmable and

1.

OR array is programmable. programmable. OR array is fixed.

2. Cheaper and simple. Cheaper and simpler.

PAL & ROM.

AND array can be programmed to

3. All minterms are decoded. be programmed to get

get desired minterms.

desired minterms.

Only Boolean functions in Any Boolean function in Any Boolean function in standard

4. canonical SOP form can be standard SOP form can be SOP form can be implemented

implemented using PROM. implemented using PLA. using PAL.

Problems

1. Let us design a combinational circuit using ROM. The circuit accepts a 3-bit number and

generates an output binary number which is equal to the square of input number.

Solution:

A2 A1 A0 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 0 0 0 0

1 0 0 1 0 0 0 0 0 1

2 0 1 0 0 0 0 1 0 0

3 0 1 1 0 0 1 0 0 1

4 1 0 0 0 1 0 0 0 0

5 1 0 1 0 1 1 0 0 1

6 1 1 0 1 0 0 1 0 0

7 1 1 1 1 1 0 0 0 1

Implementation of PLA:

Using K-Map, let us derive the equation for B0, B1, B2, B3, B4 and B5.

A2 A1 A0 B5 B4 B3 B2 B1 B0

A2 1 - - - - - - 1

A1 Ā2 0 1 - - - - 1 -

Ā0 A1 A2 1 1 0 - - 1 - -

A0 Ā1 A2 1 0 1 - - 1 - -

A0 Ā1 - 0 1 - 1 - - -

A0 A2 1 - 1 - 1 - - -

A0 A1 - 1 1 1 - - - -

T T T T T

2. Let us design a large circuit for the following Boolean expressions using PROM.

F1 (x, y, z) = Σm (1, 2, 4, 7)

F2(x, y, z) = Σm (3, 5, 6, 7)

Solution:

Given:

F1 (x, y, z) = Σm (1, 2, 4, 7)

F2(x, y, z) = Σm (3, 5, 6, 7)

The truth table for the functions F1 and F2 are given below:

Inputs Outputs

X Y Z F1 F2

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Implementaion of

PROM

3. Let us implement the following functions using PLA.

F1 = AB’ + AC

F2 = AC + BC

Solution:

Given:

F1 = AB’ + AC

F2 = AC + BC

A B C F1 F2

0 0 0 0 0

0 0 1 0 0

0 1 0 0 0

0 1 1 0 1

1 0 0 1 0

1 0 1 1 1

1 1 0 0 0

1 1 1 1 1

Product term Inputs Outputs

AB’ 1 1 0 - 1 -

AC 2 1 - 1 1 1

BC 3 - 1 1 - 1

T T T/C

4. Let us implement

the following two

Boolean functions

with a PLA:

F1 (A, B, C) = Σ (0, 1,

2, 4)

F2 (A, B, C) = Σ (0, 5,

6, 7)

Solution:

Given:

F1 (A, B, C) = Σ (0, 1, 2, 4)

F2 (A, B, C) = Σ (0, 5, 6, 7)

Implementation:

5. Let us design an

AND - OR PLA that

implements the

following functions.

f(x, y, z) = Σm(0, 2, 4, 6)

g(x, y, z) = Σm(1, 3, 5,

7)

Solution:

Given:

f(x, y, z) = Σm(0, 2, 4, 6)

g(x, y, z) = Σm(1, 3, 5, 7)

X Y Z f g T/C

1 1

T C

- - 0

6. A combinational logic circuit is defined by the following function: f 1 (a, b, c) = Σ (0, 1, 6, 7), f2

(a, b, c) = Σ (2, 3, 5, 7). Let us implement the circuit with a PAL having three inputs, three

product terms and two outputs.

Solution:

Given:

f1 (a, b, c) = Σ (0, 1, 6, 7)

f2 (a, b, c) = Σ (2, 3, 5, 7)

No Term a b c

1 0 0 -

2 AB 1 1 -

1 ĀB 0 1 -

2 AC 1 - 1

Implementation:

7. Let

us

determine the minimum sum of products for each of the two function given below.

F = WY' + XY'Z

(ii) Let us implement the above function in the PLA using more than four terms.

Solution:

Given:

F = WY' + XY'Z

Implementation of ROM

UNIT V VHDL

RTL Design – combinational logic – Sequential circuit – Operators – Introduction to Packages –

Subprograms – Test bench (Simulation /Tutorial Examples: adders, counters, flip flops,

Multiplexers & De multiplexers).

5.1 RTL Design - combinational logic

A RTL (Register Transfer Level) description describes a circuit registers and the sequence of

transfers between these registers but does not describe the hardware used to carry out these

operations.

The basis of RTL design is that circuits can be thought of as a set of register and a set of transfer

function defining the data paths between registers.

The first stage of the design has to be specific at a system level that is to be achieved and logic

operations on data coming in at the primary inputs of the circuits. At this stage, there are no

hardware implementations that can be used as the formal specification of the design.

The second stage of the design transforms the system level design into an RTL design. It is rare

for a design to be directly implemented in exactly the same form as the system level model.

The resulting gate-level netlist or schematic can be simulated against the RTC design to confirm

that the synthesized circuit has the same behaviour.

Finally, the netlist or schematic produced by synthesis is supplied to the placement and routing

tools for circuit layout.

RTL in VHDL

VHDL is used to describe the architecture and behaviour of discrete electronic system.

Gate levels modeling is a lower level of abstraction in which the digital design is described in

terms of the logic gates such as AND, OR etc.,

Logic synthesis is a process of converting a high-level design into an optimized gate level

description by incorporating the given technology library and certain design constraints.

A technology library is provided by the IC fabrication foundry and it contains a set of basic logic

gates such as AND, OR etc., and micro cells such as adders, multiplexers and sequential logic

elements such as flip flops.

For the purpose of logic synthesis, the design is written in HDL at register transfer level.

Example:

begin

process (A, B)

begin

z<= 0

else

z<= 1

end if

end process;

end RTL

MDR: At time T1, signal ACC is assigned as an operation of ACC and MDR

• The VHDL description of a digital system can be transformed into a gate level implementation.

This process is referred to as synthesis.

Description Implementation

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity majconc is

end majconc;

begin

Y <= (A and B) or (A and C) or (B and C);

end a;

VHDL statements

entity model_name is

end model_name;

begin

concurrent statement 1

concurrent statement 2

end arch_name;

In digital circuit theory, sequential logic is a type of logic circuit whose output not only depends

on the present value of its input signals but on the sequence of the past inputs.

This is in contrast to combinational logic whose output is a function of the present input only.

Programs

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity decoder is

port(

b : out STD_LOGIC_VECTOR(3 downto 0)

);

end decoder;

begin

process(a)

begin

case a is

when "00" => b <= "0001"; when "01" => b <= "0010"; when "10" => b <= "0100"; when "11" =>

b <= "1000";

end case;

end process;

end bhv;

flop

Truth table

J K Clk Qn - 1

0 0 ↑ Qn

0 1 ↑ 0

1 0 ↑ 1

1 1 ↑ Qn

X X ↓ Qn

library IEEE;

entity JK_FF is

end JK_FF;

begin

PROCESS(CLOCK)

begin

if(CLOCK='1' and CLOCK'EVENT) then

TMP:=TMP;

TMP:='0';

else

TMP:='1';

end if;

end if;

Q<=TMP;

Q <=not TMP;

end PROCESS;

end behavioral;

library IEEE;

use IEEE. STD_LOGIC_UNSIGNED.ALL;

entity D_FF is

Q: out std_logic);

end D_FF;

begin

process(CLOCK)

begin

Q <= D;

end if;

end process;

end behavioral;

6 counter

library IEEE;

use

IEEE.STD_LOGIC_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity mod6_counter is

port( clk : in std_logic; reset: in std_logic; dout: out std_logic_vector(2 downto 0));

end mod6_counter;

begin

begin

if (reset='1') then

m:= 0;

m:= m + 1;

end if;

if (m=6) then

m:= 0;

end if;

end process counter;

end mod6_counter_arc;

5.2.1 Operators

VHDL has a set of operators which can be divided into groups of the same precedence level.

• Logical operators

• Arithmetic operators

• Relational operators

• Shift operators

Shift operators → sll, srl, sla, sra, rol, ror, =, /=, <, <=, >=, >, AND, OR, NAND, NOR, XOR, XNOR.

Miscellaneous operators

power and abs find the absolute value of numeric operand.

Arithmetic operators

* → Multiplication

/ → Division

mod → Modulo

rem → Remainder

+ → Addition

- → Subtraction

& → Concatenation

Logical operators

The logical operators AND, OR, NAND, NOR, XOR, XNOR and NOT are defined for BIT and Boolean

types and one-dimensional arrays contain the elements of bit and Boolean. All these operators

have the lowest priority where the NOT operator has the highest priority. The bit type is

represented by the values '0' and '1' and the Boolean type is represented as true and false.

OR → logical OR

Shift operators

The shift operators are defined for the one-dimensional array with the elements of the type bit

or Boolean. For the shift operator, the left operand L is an array and the right operand R is an

integer. The right operand represents the number of positions and the left operand is shifted. As

the result of shifting, the value of the same type as the left operand is returned.

sra → Shift right arithmetic

Relational operators

The relational operators check the relation between the operands i.e. to state whether they are

equal, not equal or ordered in a way defined by the operator. Both operands should be of the

same type and the result received is always of the Boolean type.

= Equality

The equality operator returns the value true only when both operands have the same values and

false when the values are different. The inequality operator returns the value true when the

operators are different and false when they are equal.

5.3 Introduction to packages - subprograms

Package

declarations. A package comprises of a package declaration and an optional package body.

There are some declarations which are common across many design units.

The package stores and shares such declarations. It is an optional design unit.

A set of declarations contained in a package declaration may be shared by many design units. It

defines the items that can be made visible to other design units.

• Package declaration

• Package body

Package declaration defines the interface to the package. The items declared in a package

declaration can also be accessed by other design units by using library and clauses.

Package body contains the details of a package i.e. the behavior of the subprograms and the

values of the deferred constants which are declared in a package declaration. It also consists of

other declarations.

5.3.1 Subprograms

There are two kinds of subprograms namely procedures and functions. Both functions and

procedures written in VHDL must have a body and may have declarations.

Procedures perform sequential computations and return the values in the global objects or by

storing values into formal parameters.

Functions perform sequential computations and then returns a value. Functions do not change

their formal parameters.

procedure declarations or a function declaration.

When the subprograms are provided in a package, the subprogram declaration will be placed in

the package declaration and the subprogram body will be placed in the body of the package.

• Function (Return single value)

• Conversion functions

• Resolution functions

Functions:

Example:

function add_bits (a, b: in bit) return bit is begin -- functions cannot return multiple values

end add_bits;

begin

end add_bits2;

A user defined function needs to be declared if it is called. When a function is called, values are

passed in through parameters just prior to its execution.

Function declaration:

Process

Return(F)

end C_TO_F;

Function definition:

begin

--Sequential statements;

end process;

5.4 Test bench (Simulation/Tutorial Examples: adders, counters, flip flops, Multiplexers & De

multiplexers)

A test bench is a VHDL model that verifies the design functioning. It uses files as input. It is used

for testing, counting the errors, verification and stimulation. It consists of a set of stimulus and

stimulator. The objective of test bench is to generate stimulus to test the system, apply them to

the system under test, monitor the output for correctness and log the transactions in a human

readable form. System under test can also be termed as unit under test(UUT).

An HDL description that provides the stimulus to a design is called as a test bench. A test bench

is an HDL program used for describing and applying a stimulus to an HDL model circuit in order

to test it and observe its response during simulation.

Test benches can be quite lengthy and complex which may take longer time to develop than the

design that is being tested. The results of a test are as good as the test bench that is used for

testing a circuit.

Architecture of test

bench

Test vector generator

generates the

stimulus for the UUT.

This module can also

take outputs coming

from the UUT to

interactively change the stimulus. Verifier takes the stimulus and the responses from UUT and

checks for correctness. Simple test bench will not have verifier modeled into it. So the designer

must manually check the correctness of the UUT output.

As the test bench becomes a part of the hierarchy in our code, the following is recommended:

• The test bench instantiates the unit under test (UUT) and stimulus is applied from the top-level

test bench to the lower-level design or portion of the design is tested.

• The instance name UUT for the instantiated unit under test is used.

Example

module t_simple_circuit_prop_delay;

Wire D, E;

reg A, B, C;

Initial

begin

end

initial#200$ finish;

end module

Programs

input A, B, C, CLK;

Output Q;

request Q, E;

begin

E⇐A&B

Q ⇐ E/C

end

end module

Solution:

Example

Programs:

AND gate

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

port (A, B: in std_logic;

begin

Y <= A and B

end;

Half adder

Half adder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity HA is

Port(A, B: in std_logic;

S, C: out std_logic);

end HA;

Architecture dataflow of HA is

begin

S = XOR B;

C = A and B;

end dataflow;

library IEEE;

use IEEE.STD_LOGIC_1164.0.11;

entity half_adder is

end half_adder

begin

library IEEE;

entity counter is

port (CLK, Reset: in std_logic;

end counter

begin

begin

Q ⇐ "0000"

Q ⇐ Q+ 1;

end if

end process

end behavioral

HDL for four bit adder

library IEEE;

entity adder 4 is

C1: in std_logic

end adder A;

component fulladder

end component;

begin

fa3 = fulladder Portmap (A(3), B(3), C(3), C0, S(3));

end structure

Full adder:

library IEEE;

begin

Full adder

to 1

multiplexers

module multiplexer (D, S0, S1, S2, Y);

output y;

not

and

or

0(y, e, f, g, h, i, j, k, l)

endmodule

8:1

multiplexer

VHDL

code for

8:1

multiplexer

library IEEE;

use IEEE.STD_LOGIC_1164.0.11;

entity mux is

Port (D7, D6, D5, D4, D3, D2, D1, D0; in std-logic;

F: Out std_logic);

end mux;

begin

F< = (not S(2) and not S(1) and not S(0) and D0) or

end;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;

DATA O: out Std logic

};

end MUX_16_l_SUBm;

component MUX F7

Port

IO: in Std_logic;

Il: in Std_logic;

S: in Std_logic;

O: out Std_logic;

};

end component;

_ _ Signal declarations;

__

begin

__

_ _ if synthesis tools support MUX F7;

_ _ begin

_ _ case SELECT_I is

_ _ When '1111' ⇒ DATA_0* DATA_I(15);

_ _ end case;

__

begin

end case;

__

end case;

__

_ _ MUX F7 instantiation

Port map

{

I0 ⇒ DATA_LSB,

I1 ⇒ DATA_MSB,

S ⇒ SELECT I(3)

O ⇒ DATA_O,

};

__

end mux_16_l_SUBM_arch;

4-Bit comparator

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity compare is

A it B = out STD_LOGIC);

end compare;

begin

A lt B ⇐ '1' when a < b else '0';

end behavior;

library IEEE;

entity comparator is

end comparator

begin

process (A, B)

begin

if (A < B) then

greater <=‘0’;

else if (A = B) then

else

end if;

end process;

end behavioural;

- Binary, Decimal and Hexadecimal NumbersUploaded byssgviji
- Digital Integrated Circuits – Logic FamiliesUploaded byangelo_lopez1993
- Digital ElectronicsUploaded byEduard
- 37XR Calibration ProcedureUploaded bymikedlt
- CSC 204 - 3.1 and 3.2 Study GuideUploaded byFVCproductions
- ch-2Uploaded bypankajusb
- va903m-3_smUploaded byYuri Chimouil
- Comparison of i c Logic FamiliesUploaded byVinod kumar
- Electronic CircuitUploaded byHowe Du
- Atmos Modbus Protocol 20131212Uploaded byEric Hall
- EC1312 & EC1362 SyllabusUploaded byhisms4u
- Nte 7482Uploaded byAdir Figueiredo
- 68000 - 68010 - 68020 Primer - eBook-ENG.pdfUploaded byAnonymous wCszHg
- Lecture 01Uploaded byAli Ahmad
- Dld Lecture 1Uploaded bysjbv.hardik582
- co_int_I_QPUploaded bypjayaprabha2008
- Ch03 Logic Gates (New).pdfUploaded byOryRgb
- ECONV-PT100 Manual.pdfUploaded byjorgecasalini
- question .pdfUploaded byjushwanth
- datasheetarchive max232Uploaded byJosé Adelino
- HammingUploaded bysuresh teja chatrapati
- series i (1).docxUploaded bymd1.star
- 430037693Uploaded bykskeerthi200
- 3rdreview-d7Uploaded byderangula ashok
- chap13Uploaded byRekha Rani
- RMUX2 PRJCT.pdfUploaded byraghav
- 10.1.1.259.3989Uploaded bythamy_15
- Truth Tables by Mark Jayson de LunaUploaded byJad Deluna
- 00b4952812d448fe6f000000.pdfUploaded byPrasanna Mathivanan
- HW1_Spring2014.pdfUploaded byRüşdi Işler

- CS6302-Database Management SystemsUploaded byRevathi Saravanan
- CS8392 Object Oriented Programming_MLMUploaded byRevathi Saravanan
- Graph Theory QBUploaded byRevathi Saravanan
- UNIT v Rejinpaul Pds2Uploaded byRevathi Saravanan
- 32456789765444443^&z^%&*&^%$%^&*&^%$%^&*&^%$%^&^%Uploaded byAlexandru Tripon
- Ex 3 lex using cUploaded byRevathi Saravanan
- Shell ProgramsUploaded byRevathi Saravanan
- Cg Lab Programs Final YearUploaded byRevathi Saravanan
- Question Bank_2013_regulation.pdfUploaded byRevathi Saravanan
- maths 2mUploaded byRevathi Saravanan
- CS6201 Digital Principles and System Design 2 Mark With Answers R2013Uploaded byHema Santhi

- What is a Sample Objective Statement for a ProgrammerUploaded byrajabilal
- SplatUploaded bydjkovcin
- 3 4 7 acutandfilloptional docUploaded byapi-299811796
- Capstone_ Kumar Saurav_1507 REUploaded bysauravsahai
- offensive-security.pdfUploaded byhariom bansiwal
- Qualitative-Quantitative Bayesian Belief Networks for ReliabilityUploaded bymeercat_alex
- 16f872.pdfUploaded byChen CY
- Robust damping of interarea oscillations with.pdfUploaded byAkshay Sharma
- Carlos Gomez Predictive Control for PMSMUploaded byIbrahimFaroukSolar
- Titanium Presentation 1Uploaded byavenauche
- Www Programiz ComUploaded byanis ansari
- DaknetUploaded byaditya127
- Fm Coherent Lidar TechnologyUploaded byjackjaxon
- Mark B Schnitzer ResumeUploaded byMark Schnitzer
- 3D Pop Up Effect in PhotoshopUploaded byCarlRivera
- Microsoft Enterprise Chapter 1 Study GuideUploaded bybrockz26
- blog 1 lesson planUploaded byapi-253838262
- 212_Kuliah 01 - Pengenalan Pemrograman Berorientasi Objek (Java)Uploaded byDmaz Hendratmo
- SAP MM Tables Link and FlowUploaded byApril Santiago
- Myphone q19i Duo (3)Uploaded byJohn Roque Aliazas
- U INS Sqlserver9 v8r1.7 Checklist 20100827Uploaded byChidi Okereke
- CD Intermediate Code 06012015 033437amUploaded bykiet edu
- a situational maintenance modelUploaded byTiberioFigueiroa
- The Rise of the Empowered 0Uploaded byFlorin Razvan Prihotin
- Atmospheric Modeling Data Assimilation and PredictabilityUploaded byJoao de Mattos
- CMMI in Contrast to PMBOKUploaded byMike Dixon
- course syllabus - business research 1st sem ay 2018-2019Uploaded byapi-194241825
- 2310_a3Uploaded byAnonymous KTOih3o
- Tutorial Glass EyeUploaded byGheorghe Ioana
- TCSUploaded byAdarsh Sharma