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representing binary numbers into proportional analog voltages.

Data Acquisition System

zahurul@me.buet.ac.bd

http://teacher.buet.ac.bd/zahurul/

Bangladesh University of Engineering & Technology

ME 475: Mechatronics

e566.eps

Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 1 / 24 Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 2 / 24

into a voltage or current that represents the binary number value

of the digital word.

An 8-bit DAC, for example, may produce an output signal of 0 V

when the binary word applied to its digital input is 000000002 ,

and 2.55 V when the digital inputs see a word of 111111112 .

I = Eref

X

N

m

cm

Similar to analog input configuration, a common DAC is shared =

M 1

2 1R

among multiplexed output signals.

Standard analog output ranges are essentially same as analog Eo = IRr

inputs: 5 V dc, 10 V dc, 0 - 10 V dc, and 4-20 mA dc.

Cm = 0 or 1:

depending on the mth

bit value of the register

that controls the switch

setting.

e570.eps

Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 3 / 24 Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 4 / 24

M -bit DAC

Digital to Analog Conversion (DAC) Digital to Analog Conversion (DAC)

The binary weighted resistor ladder suffers from a series drawback DAC0808 and 741 op amp connected to form a DAC

in actual practice. The values of input resistors tend to become

very large and very small at the ends of the range as the bit length

of the input word becomes larger.

reference potential E of 5.0 V, then I8 will be only 3.9 A which is

too small to be resolved because of the noise problems.

In commercial DACs, all the resistors have a value of either R or

2R. The gain of the amplifier is unity, so Eo can be expressed as:

Eo =E

Xn

ai

i =1

2i

between the ladder and RL can be safely neglected).

e602.eps

Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 5 / 24 Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 6 / 24

In A/D conversion process continuous electrical signals are

converted to the digital language of computers.

If a 8-bit ADC has a 0-to-2.55 V input signal range, then a 0 V

input could produce an output word of 000000002 , while the

+2.55 V level seen at the input would produce an output word of

111111112 .

Numbers

01010101

01010111

01100110

e054.eps

V

01111001

........ A/D conversion processes pose two primary challenges:

1 Quantization - refers to uncertainty introduced upon conversion

........

of an analog voltage to a digital number.

2 Sampling - refers to acquiring data only at discrete intervals,

τ

e048.eps with no informations in between.

Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 7 / 24 Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 8 / 24

Analog to Digital Converter (ADC) Analog to Digital Converter (ADC)

Amplitude

10.00

111

8.75

110

7.50

101

6.25

100

5.00

011

3.75

010

2.50

001

1.25

0 000

0 20 40 60 80 100 120 140

e055.eps

Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 9 / 24 Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 10 / 24

measurement system. It can be expressed in bits, in proportions,

on in percentage of full scale. No of bits Number of States Resolution (%)

Resolution Q =

EFull Scale

2Number of Bits

1 21 = 2 50

A system may have 12-bit resolution, one part in 4096 resolution, 2 22 = 4 25

and 0.0244% of full scale. 3 23 = 8 12.5

4 24 = 16 6.25

Quantization error is the inherent uncertainty in an A/D

8 28 = 256 0.391

conversion due to the finite resolution of the system.

10 210 = 1024 0.098

An 8-bit ADC with EFS of 10 V could detect a minimum of 12 212 = 4096 0.024

10/256 = 0.0391 V. The higher the resolution, the smaller the 16 216 = 65536 0.001526

detectable voltage change. 20 220 = 1048576 0.000095

How many bits are needed to obtain a resolution of 0.01%?

Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 11 / 24 Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 12 / 24

Analog to Digital Converter (ADC) Sampling Analog to Digital Converter (ADC) Sampling

that must be greater than Nyquist frequency, fN :

fs > fN 2fmax

Time interval between the digital samples is t 1=fs =

If fs < fN , aliasing can result and totally non-existent frequencies

may be indicated.

e571.eps

Adequately Sampled

e572.eps e056.eps

Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 13 / 24 Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 14 / 24

Analog to Digital Converter (ADC) Sampling Analog to Digital Converter (ADC) ADC Hardware

1 Successive Approximation (SA) ADC

2 Flash/Parallel ADC

3 Dual-slope Integrating ADC

4 Servo/Binary-counter/Ramp ADC

1. Medium 10-16 bits Poor Low

2. Fast 4-8 bits None High

3. Slow 12-18 bits Good Low

4. Slow 14-24 bits Good Medium

e574.eps

Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 15 / 24 Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 16 / 24

Analog to Digital Converter (ADC) ADC Hardware Analog to Digital Converter (ADC) ADC Hardware

e575.eps e569.eps

Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 17 / 24 Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 18 / 24

Analog to Digital Converter (ADC) ADC Hardware Analog to Digital Converter (ADC) ADC Hardware

A SA register(SAR) contains the control logic, a shift register, and

a set of output latches, one for each register section. The outputs

of the latches drive a DAC.

A start pulse sets D7 (first bit of the shift register, MSB) high.

DAC sees the word 100000002 & generates the output voltage,

=

Vout 1=2EFS . If VIN > Vout , then the D7 latch is set high, else

it is set low.

On the next clock pulse, D6 latch is set high. The process is

continued through to LSB. If, on any trial, it is found that

VIN < Vout , then the corresponding bit is reset low. The process

is continued until the voltages match within the least significant

bit.

e603.eps

Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 19 / 24 Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 20 / 24

Analog to Digital Converter (ADC) ADC Hardware Analog to Digital Converter (ADC) ADC Hardware

e579.eps

e568.eps

fixed period of time. Hence, it smooths out signal noise. e578.eps

Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 21 / 24 Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 22 / 24

Analog to Digital Converter (ADC) ADC Hardware Analog to Digital Converter (ADC) ADC Hardware

1 Acquisition: is the time required by the front-end analog

circuitry to acquire a signal. Also called aperture time, it is the

time for which the converter must see the analog voltage in order

to complete a conversion.

2 Conversion: is the time needed to produce a digital value

corresponding to the analog value.

3 Transfer: is the time needed to send the digital value to the host

computer’s memory.

Throughput, then, equals the number of channels being served divided

e577.eps by the time required to do all three functions.

Eref , initially at zero, is increased at a set time steps & the ramp level

is compared with the input voltage. The comparison is continued until

the two are equal. The comparator output then goes to zero. It flips a

flip-flop and the register count value will then indicate the digital

binary equivalent of the input voltage.

Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 23 / 24 Prof. Dr. M. Zahurul Haq (BUET) Data Acquisition System ME 475 24 / 24

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