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Design of a planar inductor for DC-DC converter

on flexible foil applications


Jurica Kundrata
University of Zagreb, Faculty of Electrical Engineering and Computing
Unska 3, 10000 Zagreb, Croatia
E-mail: jurica.kundrata@fer.hr

Abstract—This paper presents the design of a planar in- patterned in. Flexible foil application of the inductor implies
ductor for a DC-DC converter for flexible foil applications. a planar layout of the inductor as the multi-layered layouts
The design challenges related to the flexible foil structure and are unrealisable because of the limited total thickness of the
the DC-DC converter requirements are analysed. The main
design challenges are due to the constraints on the inductor foil. The physical constraint specific to this implementation
physical size, the proximity of a conductive plane to the is the limited available area for the placement of the planar
inductor and very high operating frequency of the DC-DC inductor. The OLED tile size ranges from 30 x 30 to 125
converter. The methodology of the inductor design is based x 35 mm2 and an inductor must be placed on the area of
primarily on EM simulations of the inductor structure and a single OLED tile. The area enveloped by an inductor is
on the evaluation of the simulation results in the context of
the resulting lumped-element electrical model. The simulations closely related to the maximally realizable inductance of
are verified by measurements of the inductors processed on the inductor thus the available area for the placement of the
the FR4 substrate which presently emulates the flexible foil inductor is an important design challenge.
substrate. The structure of the OLED tile and its application in
Index Terms—thick film inductor, electromagnetic modelling a flexible foil presents the next specific design challenge.
In the context of the inductor design the cathode of the
I. I NTRODUCTION OLED tile represents a uniform metal plane acting as a
ground plane. This ground plane is only separated from the
A. State of the art inductor by a thin foil. A ground plane in close proximity
The electronics on flexible foils is getting popular as it to the inductor presents a design challenge as the inductor
offers new innovative applications in the areas of wearable currents are mirrored over the ground plane. The mirrored
electronics, lightning devices and displays [1]–[4]. Such currents, i.e. eddy currents reduce the total magnetic flux
applications require power supplies embedded in the flexible induced by the inductor and consequentially the total self-
foil. Switching-mode power supplies are a de-facto standard inductance of the inductor.
in the present DC-DC power conversion applications [5]. The requirements of the DC-DC converter in the context
Switching-mode power supplies require an energy storage of the electrical characteristics of the inductor are the next
element to work properly and inductors are often used to important design challenge. The value of the inductance
fulfil the required function. In the case of the flexible foil of the inductor is vital to the operation of the DC-DC
applications this inductor has to be embedded on the foil converter. The resistance and the parasitic capacitance of the
as well. Usually, a planar inductor design based on spiral inductor directly affect the efficiency of power conversion.
geometry is used. Spiral planar inductors are modelled and The inductor has to preserve its inductive properties in
characterized quite well [6]–[9]. the frequency range that covers the switching frequency
Many conclusions based on the research of planar induc- of the converter as well as the first few higher harmonics
tors processed on the Si substrate in the integrated circuits of the driving PWM signal. It sets a requirement on the
can be applied on the inductors implemented in the flexible dynamic behaviour of the inductor, namely that the resonant
foil technology, but some specific power applications in the frequency of the inductor needs to be beyond that frequency
flexible foil can pose a set of unique design challenges. range. The planned DC-DC converter places the inductor
requirements that are shown in Table I. It should be noted
that the maximum resistance requirement will be treated
B. Design challenges as a requirement placed on the DC value of the inductor
The inductor is designed for a buck-type DC-DC con- resistance because the OLED tile behaves primarily as a
verter that drives an OLED tile realized on the flexible capacitive load thus stabilizing the current that runs through
foil. Numerous design challenges are related to designing the inductor and minimizing its ripple component.
an inductor for a flexible foil application.
The constraints placed on the physical size of the inductor II. M ATERIALS AND METHODS
are one of the design challenges. The most obvious physical
A. Electromagnetic simulations
constraint is the thickness of the metal layer the inductor is
The described flexible foil substrate requires a planar
This work was supported by the European Commision under the inductor structure because of its thin geometry. The thin in-
Seventh Framework Programme (FP7) through project IMOLA Intelligent
light management for OLED on foil applications (Grant Agreement No. ductor structure is simulated in the COMSOL Multiphysics.
288377). Its RF module is used as the 3D EM solver for this problem.
TABLE I TABLE II
THE INDUCTOR REQUIREMENTS OF THE DC-DC THE VALUES OF THE DESIGN PARAMETERS
CONVERTER
Design parameter Range value
Electrical characteristics Required value Track width, w 0.25 to 2 mm
Series inductance, Ls 3 to 5 µH Track spacing, s 0.25 to 1 mm
Series resistance, Rs <1Ω Number of turns, N 1 to max.
Parasitic capacitance, Cp < 50 pF Outer diameter, d 28 mm (const.)
Resonant frequency, fr > 50 MHz Track metal Cu
Track thickness 35 µm
Top/bottom dielectric thickness 200 µm

Fig. 2. The π-model of the inductor that accounts for the port and interport
capacitances and the skin effect.

B. Electrical model
Fig. 1. The geometry of the inductor model used in the electromagnetic
simulations. A lumped-element electrical model is developed to eval-
uate the electrical characteristics of the inductor in the
context of the requirements and to accurately describe the
The geometry of the model used in EM simulations is behaviour of the inductor in the frequency range relevant to
based on the smallest OLED tile dimensions as it represents the operation of the DC-DC converter.
the worst case scenario in the context of the inductor total In the analysis of the simulation and measurement results
area and thus its inductance. The inductor model is based a π-model was used and its topology is shown in Fig. 2.
on a spiral rectangular geometry and it is shown in Fig. 1. The π-model consists of the port capacitances C1 and C2 ,
The geometry is determined by the outer diameter of the the interport capacitance C3 , the interport inductance L1
rectangular spiral d, the track width w, the track spacing and the ladder network R1 -R2 -L2 . The capacitances C1 ,
s and the number of turns of the spiral N . The positions C2 and C3 account for different resonances of the inductor
of the ports P1 and P2 are also marked in the figure. The while the ladder network R1 -R2 -L2 describes the frequency
simulated substrate has two dielectric layers and three metal dependant resistance of the inductor, i.e. the skin effect
layers. The inductor is wound in M1 (top metal) and the exit present at the operating frequency of the DC-DC converter
towards the port P2 is performed in M2 layer. The bottom [10].
metal M3 serves as the ground plane if it is used. Physically, the capacitances C1 and C2 represent the ca-
The operating frequency of the DC-DC converter deter- pacitances of the inductor tracks towards the ground plane.
mines the frequency range of interest that is analysed in As the geometry of the inductor tracks is asymmetrical in
EM simulations. The inductor is driven by a PWM signal the context of its ports, it is expected that the capacitances
from the DC-DC converter which is essentially a rectan- C1 and C2 are not equal. The capacitance C3 represents the
gular waveform. The analysed frequency range includes interwinding capacitance of the inductor.
the switching frequency of the converter and its higher The parameters of the electrical model are extracted
harmonics and it is determined by the frequency from 1 using a developed algorithm implemented in MATLAB. The
to 200 MHz. The upper frequency limit is set to include algorithm is described by the flowchart shown in Fig. 3.
the resonant behaviour of the inductor in the analysis. The algorithm is based on three steps. In the first step the
The electromagnetic simulations are primarily used to inductance L1 is calculated from the interport impedance.
investigate the influence of the different design parameters In the following step the capacitances C1 , C2 and C3 are
on the electrical characteristics of the inductor. The design calculated from the resonant and antiresonant frequencies.
parameters are swept in different ranges. The values of the The third step is based on fitting the ladder network R1 -
design parameters are shown in the Table II. R2 -L2 .
Fig. 5. The amplitude frequency characteristics of the Z11 and Z12
Fig. 3. The algorithm used in the extraction of the electrical model parameters for the simulated data.
parameters.

Fig. 4. The layout of the inductor matrix used for verification of the Fig. 6. The amplitude frequency characteristics of the Z11 and Z22
electromagnetic simulations. parameters for the simulated data with marked resonant frequencies.

C. Physical verification III. R ESULTS

The results of the electromagnetic simulations are veri- A. Frequency characteristics


fied by measurements of the inductors. The inductors are The frequency characteristics of the inductor are analysed
processed on the FR4 substrate. The FR4 substrate has two on the inductor example determined by the following set of
200 µm thick dielectric layers and can be considered a good design parameters w = 1 mm, s = 1 mm, N = 7. The results
emulation of a flexible foil substrate. of the electromagnetic simulations in the context of its Z-
Multiple inductors with varied track width and spacing parameters are presented in Figs. 5 and 6.
are processed in the form of a matrix. The track widths are In Fig. 5 the frequency characteristics of the Z11 and Z12
0.5 mm, 1 mm and 2 mm and the track spacing 0.25 mm, parameters are presented. Several resonant frequencies can
0.5 mm and 1 mm. Both variations are made simultaneously be identified in these characteristics. The frequency charac-
thus accounting for 9 unique inductor designs, as shown in teristics of the interport impedance Z12 has a single local
Fig. 4. The same layout is processed in two versions. The maximum that can be identified as antiresonant behaviour.
first version is realized as a PCB with a single FR4 layer and This implies a parallel LC network between the ports of
two layers of metallization, while the second version was the inductor which is presented in the electrical model
realized with an additional FR4 layer with a metal sheet. with the interport capacitance C3 (Fig. 2). The frequency
This metal sheet acted as the ground plane. characteristic of the port impedance Z11 has two local
The measurements are made using a vector network extremes. One extreme is a local maximum and matches
analyser. The ports used in the layout are designed to the previously identified antiresonant behaviour of Z12 and
allow their de-embedding at the reference plane ∆-∆0 the second extreme is a local minimum. This local minimum
shown for the top-left inductor in Fig. 4. A separate layout can be identified as resonant behaviour and implies the
was developed and used for the Short-Open-Load-Through existence of the port capacitances. These port capacitances
(SOLT) calibration of the vector network analyser. are presented in the inductor model by the capacitances C1
Fig. 7. The dependence of the port capacitances C1 and C2 on the track Fig. 8. The dependence of the port capacitances C1 in the context of the
width with total turn spacing s + w = 1.25 mm and N = 11. track width and the number of turns of the inductor with total turn spacing
s + w = 1.25 mm.

and C2 .
The frequency characteristics of the Z11 and Z22 port
impedances are compared in Fig. 6. The identified reso-
nant and antiresonant behaviour is emphasized by separate
markers. It is to be noted that the antiresonant frequency fa
is identical for both ports, but the resonant frequencies fr1
and fr2 are slightly different. This was expected as the port
capacitances C1 and C2 are also slightly different because
of the asymmetrical inductor structure.
In the context of the DC-DC converter requirements the
resonant behaviour of this inductor design example is well
above the required frequency limit of 50 MHz.
B. Design parameter sweeps
The design parameter sweeps are the primary method of
exploring different inductor designs. The parameter sweeps
described in the methodology of this work yield a large Fig. 9. The dependence of the interport capacitances C3 in the context
database of simulation results. The analysis of this database of the track spacing and the number of turns of the inductor with total
turn spacing s + w = 1.25 mm.
is presented in a series of figures that represent only a
selection of simulation results and are later used for defining
a set of design guidelines for the planar inductors.
Figs. 7, 8 and 9 show the dependences of the electrical is expanded with the dependence on the number of turns.
model capacitances C1 , C2 and C3 w.r.t. different design The dependence of the port capacitance on the number
parameters, while Fig. 10 shows such a dependence of the of turns is expected because increasing the number of
series inductance Ls . turns increases the total track area as well. This effectively
The port capacitance dependence on the track width and increases the plate area of the capacitor that represents the
the interrelationship of the port capacitances C1 and C2 port capacitance in conjunction with the ground plane.
is shown in Fig. 7. Two observations of the results are The interport capacitance C3 dependence on the track
made. The first observation is that the port capacitances spacing and the number of turns is shown in Fig. 9.
are not equal. This asymmetry of the port capacitances is Two observations are made based on this figure. The first
in accordance to the asymmetric inductor structure. The observation is that the interport capacitance is inversely
second observation is that the value of the port capacitances proportional to the track spacing. The interport capacitance
is proportional to the track width. As the total spacing of is based primarily on the capacitance between neighbouring
the turns (s + w) and the number of turns are kept constant, inductor turns. It is expected that, if the space between the
the track width in this figure can be directly correlated with tracks is increased while maintaining the same track length,
the total track area. This observation is expected because the capacitance is decreased. The second observation is sim-
the capacitance of a capacitor is directly proportional to the ilar to the observation of the port capacitance dependence on
area of its plates. the number of turns. The interport capacitance is increased
The port capacitance C1 dependence on the track width as the number of turns is increased and thus the length of the
and the number of turns is shown in Fig. 8. In this figure the tracks is increased. It should be noted that the dependence of
observation concerning the port capacitance dependence on the interport capacitance on the number of turns is nonlinear
the track width from Fig. 7 is confirmed. This observation because the dependence of the track length on the number of
Fig. 10. The dependence of the series inductance Ls in the context of the Fig. 11. The correlation between the measured and simulated data in the
track width and the track spacing while maintaining the series resistance context of the extracted inductance of the inductor.
constant Rs = 1 Ω.

turns is nonlinear as well, i.e. the inner turns of the inductor


spiral contribute the least to the track length.
The dependence of the series inductance Ls on the track
width and the track spacing is shown in Fig. 10. These
simulation results are made in the context of the DC-
DC converter requirements for the series resistance of the
inductor. The required number of turns to achieve the upper
resistance limit for each combination of the track width and
track spacing was calculated and used in the simulations. An
observation is made based on these results. The inductance
achievable in the context of the resistance requirement is at
the maximum for the combination of minimal track width
and minimal track spacing. When the track width and/or
the track spacing increase, the inductance of the inductor
decreases. This observation is interpreted by understanding Fig. 12. The correlation between the measured and the simulated data in
that a narrower turn with minimal spacing can envelope a the context of the resonant frequency of the inductor.
greater area and thus produce greater inductivity. Another
effect should be considered; while the wider turns can
support a greater number of turns in the context of limited by a factor of 5 because of the mirroring of the inductor
inductor resistance, the number of turns in the case of currents and reduction of the magnetic flux.
a planar inductor suffers from the effect of diminishing The correlation of the resonant frequency fa is shown in
returns. The inner turns are contributing the least to the Fig. 12. The simulated resonant frequency correlates with
total inductance of the planar inductor. the measured resonant frequency rather well with a slight
In the context of the DC-DC converter requirements the offset. The probable cause to the offset is the uncertainty of
capacitances of the inductor are significantly lower than the processed substrate thickness compared to the one used
the required maximum capacitance, while the inductance in the simulations.
is below the required range of values. In the context of the DC-DC converter requirements the
inductance of a few inductor designs without the metal
C. Physical verification plane falls within the required range of values. With the
The results of the electromagnetic simulations are verified introduction of the metal plane in the substrate design, none
by measuring a set of inductors with different design param- of the design cases conform to the requirements, i.e. the
eters. The results of the physical verification are presented inductor is too small.
in Figs. 11 and 12. These figures show the correlations IV. D ISCUSSION
between the measured and simulated data.
The correlation of the extracted inductance L of the A. Design guidelines
inductor is given in Fig. 11. The simulated inductance Based on the observations made on the results of the sim-
correlates with the measured inductance well. ulations several guidelines for designing a planar inductor
The effect of the metal plane on the inductance and the can be set. Each guideline corresponds to a single design
resonant frequency can be observed in these results. As parameter of the inductor.
expected introducing the metal plane in the substrate of the The first design guideline corresponds to the track width.
designed inductors decreases its inductance approximately Based on the observations of the results the track width
should be minimized. This guideline minimizes the value the electrical model parameters is presented. The electro-
of the port capacitances and maximizes the value of the magnetic simulations are physically verified by measuring
inductance in the context of the required inductor resistance. the inductor designs processed on the FR4 substrate. Based
The second guideline is related to the track spacing. The on the analysis of the results a set of design guidelines is
observations of the results imply that the track spacing presented. The design guidelines recommend minimizing
should be optimized between the requirements on the reso- the track width and the track spacing while adapting the
nant frequency and the requirements on the inductance. The number of turns to the resistance requirement to achieve
resonant frequency of the inductor is closely related to the the maximal inductance. The degrading effect of the ground
value of the interport capacitance. If the requirements on plane on the inductance of the inductor is analysed. The so-
the resonant frequency are more relaxed, then the general lutions using the patterned ground shields or ferrite polymer
guideline is to minimize the track spacing in order to composite are proposed.
maximize the inductance of the inductor.
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